TM VIA C3 Samuel 2 Processor Datasheet VIA C3 Samuel 2 Processor Datasheet October 2004 This is Version 1.12 of the VIA C3 Samuel 2 Processor Datasheet. © 2002-2004 VIA Technologies, Inc All Rights Reserved. VIA reserves the right to make changes in its products without notice in order to improve design or performance characteristics. This publication neither states nor implies any representations or warranties of any kind, including but not limited to any implied warranty of merchantability or fitness for a particular purpose. No license, express or implied, to any intellectual property rights is granted by this document. VIA makes no representations or warranties with respect to the accuracy or completeness of the con- tents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. VIA disclaims responsibility for any consequences resulting from the use of the information included herein. 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Life support devices are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. This policy covers any component of a life support device or system whose failure to perform can cause the failure of the life support device or system, or to affect its safety or effectiveness. October 2004 VIA C3 Samuel 2 Processor Datasheet Table of Contents 1 INTRODUCTION 1.1 DATASHEET OUTLINE .................................................... 1-1 1.2 BASIC FEATURES............................................................ 1-1 1.3 PROCESSOR VERSIONS................................................ 1-2 1.4 COMPETITIVE COMPARISONS ...................................... 1-3 1.5 COMPATIBILITY ............................................................... 1-4 2 ARCHITECTURE 2.1 INTRODUCTION............................................................... 2-1 2.2 COMPONENT SUMMARY................................................ 2-2 GENERAL ARCHITECTURE & FEATURES..................................... 2-2 2.2.2 INSTRUCTION FETCH .................................................. 2-5 2.2.3 INSTRUCTION DECODE ............................................... 2-5 2.2.4 BRANCH PREDICTION ................................................. 2-6 2.2.5 INTEGER UNIT............................................................ 2-6 2.2.6 D-CACHE & DATAPATH ............................................... 2-7 2.2.7 L2 CACHE ................................................................. 2-8 2.2.8 FP UNIT..................................................................... 2-8 2.2.9 MMX UNIT.................................................................. 2-9 2.2.10 3DNOW! UNIT ............................................................ 2-9 2.2.11 BUS UNIT .................................................................. 2-9 2.2.12 POWER MANAGEMENT................................................ 2-9 3 PROGRAMMING INTERFACE 3.1 GENERAL ......................................................................... 3-1 3.2 ADDITIONAL FUNCTIONS............................................... 3-2 3.3 MACHINE-SPECIFIC FUNCTIONS .................................. 3-2 3.3.1 GENERAL .................................................................. 3-2 3.3.2 STANDARD CPUID INSTRUCTION FUNCTIONS ................. 3-2 3.3.3 EXTENDED CPUID INSTRUCTION FUNCTIONS ................. 3-5 3.3.4 PROCESSOR IDENTIFICATION ...................................... 3-7 3.3.5 EDX VALUE AFTER RESET. .......................................... 3-7 3.3.6 CONTROL REGISTER 4 (CR4) ...................................... 3-7 3.3.7 MACHINE-SPECIFIC REGISTERS.................................. 3-8 3.4 OMITTED FUNCTIONS .................................................... 3-8 Table of Contents i VIA C3 Samuel 2 Processor Datasheet October 2004 4 HARDWARE INTERFACE 4.1 BUS INTERFACE..............................................................4-1 4.1.1 DIFFERENCES............................................................4-1 4.1.2 CLARIFICATIONS ........................................................4-2 4.1.3 OMISSIONS................................................................4-3 4.2 PIN DESCRIPTION ...........................................................4-4 4.3 POWER MANAGEMENT ..................................................4-6 4.4 TEST & DEBUG ................................................................4-6 4.4.1 BIST..........................................................................4-6 4.4.2 JTAG.........................................................................4-7 4.4.3 DEBUG PORT .............................................................4-7 5 ELECTRICAL SPECIFICATIONS 5.1 AC TIMING TABLES .........................................................5-1 5.2 DC SPECIFICATIONS.......................................................5-2 5.2.1 RECOMMENDED OPERATING CONDITIONS .....................5-2 5.2.2 MAXIMUM RATINGS.....................................................5-2 5.2.3 DC CHARACTERISTICS ................................................5-3 5.2.4 POWER DISSIPATION...................................................5-3 6 MECHANICAL SPECIFICATIONS 6.1 CPGA PACKAGE ..............................................................6-1 7 THERMAL SPECIFICATIONS 7.1 INTRODUCTION ...............................................................7-1 7.2 TYPICAL ENVIRONMENTS..............................................7-1 7.3 MEASURING T ................................................................7-1 C 7.4 MEASURING T .................................................................7-2 J 7.5 ESTIMATING T ................................................................7-2 C APPENDIX A MACHINE SPECIFIC REGISTERS.................... A-1 A.1 GENERAL......................................................................... A-1 A.2 CATEGORY 1 MSRS ....................................................... A-3 A.3 CATEGORY 2 MSRS ....................................................... A-5 ii Table of Contents October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION INTRODUCTION The VIA C3 Samuel 2 processor is based on a unique internal architecture and is manufactured using an advanced 0.15µ CMOS technology. This architecture and process technology provides a highly compati- ble, high-performance, low-cost, and low-power solution for the desktop PC, notebook, and Internet Appliance markets. The VIA C3 Samuel 2 processor is available in several MHz versions. When considered individually, the compatibility, function, performance, cost, and power dissipation of the VIA C3 Samuel 2 processor family are all very competitive. When considered as a whole, the VIA C3 Samuel 2 processor family offers a breakthrough level of value. 1.1 DATASHEET OUTLINE The intent of this datasheet is to make it easy for a direct user—a board designer, a system designer, or a BIOS developer—to use the VIA C3 Samuel 2 processor. Section 1 of the datasheet summarizes the key features of the VIA C3 Samuel 2 processor. Section 2 pro- vides a detailed description of the internal architecture of the VIA C3 Samuel 2 processor. Section 3 specifies the primary programming interface. Section 4 does the same for the bus interface. Sections 5, 6 and 7 specify the classical datasheet topics of AC timings, pinouts, and mechanical specifications. Appendix A documents the VIA C3 Samuel 2 processor machine specific registers (MSRs). 1.2 BASIC FEATURES The VIA C3 Samuel 2 processor family currently consists of one basic model with several different MHz versions. Due to its low power dissipation, the single model is ideally suited for both desktop and mobile applications. All versions share the following common features: � Plug-compatible with Socket 370 processors in terms of bus protocol, electrical interface, and physical package Section 1 Introduction 1-1 VIA C3 Samuel 2 Processor Datasheet October 2004 � Software-compatible with thousands of x86 software applications available � MMX-compatible instructions � AMD-compatible 3DNow! instructions � Two large (64-KB each, 4-way) on-chip caches � 64-KB Level 2 victim cache � Two large TLBs (128 entries each, 8-way) with two page directory caches � Unique and sophisticated branch prediction mechanisms � Bus speeds up to 133 MHz � Extremely low power dissipation 2 � Very small die (52 mm in TSMC 0.15µ technology) 1.3 PROCESSOR VERSIONS Typically, there are five specification parameters that characterize different versions of a processor family: package, voltage, maximum case temperature, external bus speed, and internal MHz The VIA C3 Samuel 2 processor family currently is offered in only one package (a Flex370-compatible ceramic PGA), with nominal voltage (1.6V/1.65V), and with only one maximum specified case tempera- ture (85°C). The voltage is defined by the Flex370 VID pins. The internal MHz of a particular VIA C3 Samuel 2 processor chip is defined by two parameters: the specified external bus speed, and the internal bus-clock multiplier. VIA C3 Samuel 2 processors come in two bus-speed versions: either 100MHz bus or 133 MHz bus. (Either version can also operate at 66MHz bus speeds.) Bus frequency select pins (BSEL 0 and BSEL 1) identify the appropriate bus speed (100 MHz or 133 MHz). The bus-clock multiplier is hardwired into each VIA C3 Samuel 2 processor chip. That is, the ratio of the 1 internal processor clock speed to the externally supplied bus clock is frozen for a particular chip . Several different clock-multiplier versions are currently offered. 1 Actually, it is semi-frozen. A VIA-unique machine specific register allows programming to temporarily change the hard-wired multiplier. This capability, documented in Appendix A, is intended for special BIOS situations and test and debug usage. 1-2 Introduction Section 1 October 2004 VIA C3 Samuel 2 Processor Datasheet More information on these topics is included in Sections 4, 5, and 6 of this datasheet � The VIA C3 Samuel 2 processor is initially available in a variety of speed grades: • 700 (7.0 x 100-MHz bus) • 733 (5.5 x 133-MHz bus) • 750 (7.5 x 100-MHz bus) • 800 (6.0 x 133-MHz bus) • 800 (8.0 x 100-MHz bus) � Future versions of the VIA C3 Samuel 2 processor may provide other speed grades and bus speed combinations. � Future versions of the VIA C3 Samuel 2 processor may have different voltages 1.4 COMPETITIVE COMPARISONS Section 2 of this datasheet contains considerable detail about the unique internal design of the VIA C3 Samuel 2 processor. Such an internal architecture comparison, however, does not directly address the most important consid- erations of users: compatibility, availability, price, MHz, application performance, and power dissipation. For that reason, we do not provide a detailed architecture comparison with other processors in this data- sheet. Instead, following is the high-level summary of an internal-architecture comparison: � The VIA C3 Samuel 2 processor has better cache and TLB capabilities. These are critical to system performance for modern PC operating systems and applications. � The VIA C3 Samuel 2 processor has a generally simpler internal architecture. However, the VIA C3 Samuel 2 processor implements many advanced features critical to performance (such as so- phisticated branch prediction) and is highly tuned for good application performance, especially on “integer” or office applications. 2 � The VIA C3 Samuel 2 processor has a much smaller die size (52 mm ) � The VIA C3 Samuel 2 processor has lower power dissipation at the same MHz. Section 1 Introduction 1-3 VIA C3 Samuel 2 Processor Datasheet October 2004 1.5 COMPATIBILITY A VIA C3 Samuel 2 processor can plug into existing Socket 370 motherboards and can operate without requiring changes to the system hardware (with one theoretical difference discussed in the next para- graph). No special jumpers or different board wiring is required. In most cases, however, a special BIOS is needed. Currently, BIOS support for the VIA C3 Samuel 2 processor is available from Award, AMI, Phoenix, and Insyde. The VIA C3 Samuel 2 processor requires external termination of bus signals. Physical and bus compati- bility is covered in more detail in Section 4 of this datasheet. The VIA C3 Samuel 2 processor supports 3DNow! instructions. The VIA C3 Samuel 2 processor does NOT support multiple processors. These functions, are defined as optional by and are identified to soft- ware via the CPUID instruction. The VIA C3 Samuel 2 processor carefully follows the protocol for defining the availability of these optional features. Both the additional and omitted optional features are covered in more detail in Section 3 of this datasheet. To verify compatibility of the VIA C3 Samuel 2 processor with real PC applications and hardware, VIA have performed extensive testing of hundreds of PC boards, and peripherals, thousands of software appli- cations, and all known operating systems. Indicative of this high compatibility, the VIA C3 Samuel 2 will soon obtain Windows 98 and Windows NT certification. 1-4 Introduction Section 1 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION ARCHITECTURE 2.1 INTRODUCTION The VIA C3 Samuel 2 processor architecture is an extension of the VIA C3 Samuel (formerly known as VIA Cyrix III) processor architecture, which is different from any other x86 processor architecture. This unique processor architecture provides a significantly smaller die size using less power than any other x86 processor. The new VIA C3 Samuel 2 processor improves performance (MHz and CPI) and further re- duces die size and power over the base VIA C3 Samuel. (The major differences between the VIA C3 Samuel processor and the VIA C3 Samuel 2 processor are highlighted in the descriptions below.) The VIA C3 Samuel 2 processor architecture is based on, and directly exploits, some basic “facts” about the current x86 market, applications, and bus environment. While seemingly straightforward, these con- cepts are not exploited in other processor architectures. The major concepts that shape the VIA C3 Samuel 2 processor architecture are: � A few instructions dominate x86 instruction execution time. Over 90% of instruction execution time is due to a few basic x86 instructions. Most x86 instructions have no significant impact on performance. The VIA C3 Samuel 2 processor design optimizes performance of the most important x86 instruc- tions while minimizing the hardware provided for the little-used x86 functions (these are primarily implemented in microcode). The resulting instruction execution speed of highly used instructions is as good or better than comparable processors. For example, the VIA C3 Samuel 2 processor exe- cutes x86 load-ALU-store instructions in only one clock as compared to several clocks on other processors. The execution time of little-used instructions is impacted to reduce die size, but this has no effect on real application performance. � Improving clock frequency has higher leverage than improving CPI. The result of advanced computer design approaches over the last few years has been that the improvements in cycles-per- instruction (CPI) often impact MHz improvements, and certainly impact die size. Our belief is that the best way to improve total performance and keep a small low-power die is to improve MHz Section 2 Architecture 2-1 VIA C3 Samuel 2 Processor Datasheet October 2004 Thus, the VIA C3 Samuel 2 processor family architecture provides improved performance by op- timizing MHz via a 12-stage pipeline while maintaining a good CPI. Complex CPI-driven features such as out-of-order instruction execution are not implemented because they (1) impact MHz, (2) they require a lot of die area and power, and (3) they have little impact on real performance since… (the next point) � Memory performance is the limiting CPI performance factor. In modern PCs, the processor bus is slow compared to the internal clock frequency. Thus, off-chip memory-accesses dominate processor CPI as opposed to internal instruction execution performance. The VIA C3 Samuel 2 processor family addresses this phenomenon by providing many specific features designed to reduce bus activity: large primary caches, large TLBs, aggressive prefetching, an efficient level-2 cache (new to the VIA C3 Samuel 2 processor), and so forth. � Different market segments have different workload characteristics. The hardware, operating systems and applications used in our target market (low-end desktop and mobile PCs) have differ- ent technical characteristics than those in the high-end, workstation, or server market. The VIA C3 Samuel 2 processor family exploits these differences by implementing very specific design tradeoffs providing high performance with low cost in the target environments. These op- timizations are based on extensive analysis of actual behavior of target-market hardware and software. � Small is beautiful. VIA C3 Samuel 2 processors are highly optimized for small die size. In addi- tion to the obvious cost benefits, this small size reduces power consumption and improves reliability. 2.2 COMPONENT SUMMARY 2.2.1 GENERAL ARCHITECTURE & FEATURES Figure 1 illustrates the basic 12-stage (integer) pipeline structure of the VIA C3 Samuel 2 processor fam- ily. At a high level, there are four major functional groups: I-fetch, decode and translate, execution, and data cache. The I-fetch components deliver x86 instruction bytes from the large I-cache or the external bus. Large buffers allow fetching to proceed asynchronously to other operations. The decode and translate compo- nents convert x86 instruction bytes into internal execution forms. Branches are also identified, predicted, and the targets prefetched. Large buffers allow decoding and translating to proceed asynchronously to other operations. The execution components issue, execute, and retire internal instructions. The data cache components manage the efficient loading and storing of execution data to and from the caches, bus, and internal components. At one level the VIA C3 Samuel 2 processor architecture seems simple; instructions are issued, executed, and retired in order, only one instruction can be issued per clock, and most data cache misses stall the pipeline. However, the design is actually highly optimized and highly tuned to achieve high performance in the targeted environment. Some of the significant features providing this performance are: � High internal clock frequency. The 12-stage pipeline facilitates high MHz 2-2 Architecture Section 2 October 2004 VIA C3 Samuel 2 Processor Datasheet � Large on-chip caches and TLBs. VIA C3 Samuel 2 processors implement large caches and TLBs that significantly reduce stalls due to bus traffic. These primary caches and TLBs are larger than those on any other x86 processor: • Two 64-KB primary (L1) caches with 4-way associativity • A (new to the VIA C3 Samuel 2 processor) 4-way 64-KB unified level-2 (L2) cache. • Two 128-entry TLBs with 8-way associativity • Two 8-entry page directory caches that effectively eliminate loads of page directory entries upon TLB misses. • A four-entry (8 bytes each) store queue that also forwards store data to subsequent loads • A four-entry write buffer that also performs write combining � Extensive features to further minimize bus stalls. These include: • Full memory type range registers (MTRRs) • A non-stalling write-allocate implementation • Implementation of the “cache lock” feature • Non-blocking out-of-order retirement of pipeline stores • Implementation of x86 prefetch instruction (3DNow!) • Implicit speculative data prefetch into D-cache • Aggressive implicit instruction prefetch into I-cache • Highly asynchronous execution with extensive queuing to allow fetching, decoding and trans- lating, executing, and data movement to proceed in parallel � High-performance bus implementation. The VIA C3 Samuel 2 processor (socket 370) compati- ble bus implementation includes the following performance enhancements: • No stalls on snoops • Up to 8 transactions can be initiated by the processor • Aggressive write pipelining • Smart bus allocation prioritization • 100MHz and 133MHz bus operation � Good performance for highly used instructions. Heavily used instructions—including complex functions such as protect-mode segment-register loads and string instructions—are executed fast. In particular, the pipeline is arranged to provide one-clock execution of the heavily used register– memory and memory–register forms of x86 instructions. Many instructions require fewer pipeline clocks than on comparable processors. Section 2 Architecture 2-3 VIA C3 Samuel 2 Processor Datasheet October 2004 I I-Cache & I-TLB 128-ent 8-way I-Fetch 64 KB 4-way B 8-ent PDC V predecode Return stack decode buffer 3 BHTs Decode F Branch Decode Prediction 4-entry inst Q & Translate BTB Translate X Socket L2 cache Bus 4-entry inst Q ROM 370 Bus Unit 64 Kb 4-way Register File R address calculation A D-Cache & D-TLB D 128-ent 8-way 64 KB 4-way 8-ent PDC G Execute FP Integer ALU E Q Store-Branch S MMX/ FP 3D Unit Writeback W Unit Store Buffers Write Buffers Figure 1. The VIA C3 Samuel 2 Processor Pipeline Structure 2-4 Architecture Section 2 October 2004 VIA C3 Samuel 2 Processor Datasheet 2.2.2 INSTRUCTION FETCH The first three pipeline stages (I, B, V) deliver aligned instruction data from the I-cache or external bus into the instruction decode buffers. These stages are fully pipelined such that on each clock cycle a new instruction fetch address is fetched from the I-cache and either 16 bytes (I-cache) or 8-bytes (bus) of in- struction data is delivered for decode. The primary I-cache contains 64 KB organized as four-way set associative with 32-byte lines. The associ- ated large I-TLB contains 128 entries organized as 8-way set associative. In addition, the I-TLB includes an eight-entry page directory cache that significantly reduces the TLB miss penalty. The cache, TLB, and page directory cache all use a pseudo-LRU replacement algorithm. As opposed to many other contemporary x86 processors, the data in the I-cache is exactly what came from the bus; that is, there are no “hidden” predecode bits. This allows a large cache capacity in a small physical size. The instruction data is predecoded as it comes out of the cache; this predecode is over- lapped with other required operations and, thus, effectively takes no time. The fetched instruction data is placed sequentially into multiple buffers. Starting with a branch, the first branch-target byte is left adjusted into the instruction decode buffer (the XIB). As instructions are decoded, they are removed from the XIB. New incoming fetch data each clock is concatenated with the remaining data in the XIB. Once the XIB is filled, fetching continues to fill three 16-byte buffers that feed the XIB. If an I-cache miss occurs during the filling of the fetch buffers, up to four 32-byte lines are speculatively prefetched from the external bus into the cache. These prefetches are pipelined on the bus for optimal bus efficiency. This aggressive prefetch algorithm exploits the large size and four-way structure of the I-cache as well as the high-bandwidth bus implementation. 2.2.3 INSTRUCTION DECODE Instruction bytes in the XIB are decoded and translated into the internal format by two pipeline stages (F, X). These units are fully pipelined such that, in general, an x86 instruction is decoded and translated every clock cycle. The F stage decodes and “formats” an x86 instruction (completely contained in the XIB) into an interme- diate x86 format. This process requires only one clock cycle for every x86 instruction. However, instruction prefixes other than 0F require an additional cycle for each prefix. The internal-format instruc- tions are placed into a five-deep FIFO queue: the FIQ. The FIQ facilitates the asynchronous fetch and “lookahead” capability of the formatter such that the extra cycles for prefixes rarely result in a bubble in the execution pipeline. The FIQ also allows for branch prediction to proceed even if the pipeline ahead of the branch is stalled. The X-stage “translates” an intermediate-form x86 instruction from the FIQ into the internal micro- instruction format. The output of the translator contains: (1) the internal micro-instruction stream to per- form the x86 instruction function, (2) the immediate data fields from the x86 instruction, and (3) various x86 state information used to control execution (for example, operand size). The internal micro- instruction stream consists of micro-instructions directly generated by the translator plus, in some cases, an on-chip ROM address. The translator can generate up to three micro-instructions per clock plus a ROM address. Most x86 instructions except for repetitive string operations are translated in one clock. Executable micro-instructions can come from either the XIQ or the on-chip ROM. For performance- sensitive instructions, there is no delay due to access of micro-code from ROM. The microcode ROM ca- pacity is larger than most x86 microcode ROMs to allow unimportant (relative to performance) functions to be performed in microcode (versus in hardware). The large size also allows the inclusion of extensive self-test microcode and extensive built-in debugging aids (for processor design debug). Section 2 Architecture 2-5 VIA C3 Samuel 2 Processor Datasheet October 2004 Instruction fetch, decode, and translation are made asynchronous from execution via a five-entry FIFO queue (the XIQ) between the translator and the execution unit. This queue allows the formatter and trans- lator to “look-ahead” and continue translating x86 instructions even though the execution unit is stalled. 2.2.4 BRANCH PREDICTION The VIA C3 Samuel 2 processor implements a very unique and sophisticated, yet relatively small, branch prediction mechanism. Several different mechanisms predict all basic types of branches: jumps and calls using a displacement, returns, indirect jumps and calls, and “far” (inter-segment) branches (new to the VIA C3 Samuel 2 processor). These types of jumps represent almost 25% of all instructions executed. The prediction starts when the branch is decoded in the F stage. If a branch is predicted taken, the target is fetched such that a four-clock “bubble” appears to occur. In practice however, this bubble averages less than two clocks due to the extensive instruction queuing below the F stage; the delay in fetching the pre- dicted branch target is absorbed by execution of these queued instructions. There is also a special case: short forward branches that “hit” in the XIB require only one clock delay. For displacement-form branches, the target address is directly calculated. This direct calculation of the target address eliminates the need for a large branch-target buffer (a BTB or BTAC). The direct calculation always produces the correct address whereas a BTB often mispredicts the address, or fails to predict at all. Two different prediction algorithms are used to predict the direction of conditional branches. The under- lying theory behind this approach is that, in practice, branches tend to fall into two categories. Most branches can be accurately predicted by a classic mechanism using a counter associated with the branch location. The associated VIA C3 Samuel 2 processor mechanism is a simple array of predictors with 8K entries (versus 4K in the VIA C3 Samuel processor). However, about 20% of branches are hard to predict because whether they branch or not depends on dy- namic execution state. The VIA C3 Samuel 2 processor mechanism for predicting these pattern-based branches uses a 13-bit global branch history XOR’d with the branch instruction address to index a branch history table with 8K entries (versus 4K in the VIA C3 Samuel processor). This branch-history mecha- nism is called g-share in the technical literature. A third 4K-entry table selects which predictor (simple or history-based) to use for a particular branch based on the previous behavior of the branch. All three predictor tables actually use a one-bit “agree/disagree” predictor rather than the conventional two-bit counter. This unique approach uses a static predictor that considers the type of conditional branch and what type of instruction previously set the condition flag being tested. Rather than indicate taken or not, the one-bit entry in the predictor tables predicts whether the conditional branch direction agrees with the static prediction. The static predictor is accurate about 70% of the time, and the dynamic predictor is accurate about 95% of the time. In addition, x86 return instructions are predicted by a 16-entry return-address stack. This prediction is about 90% accurate. Finally, indirect jump and call instructions are predicted using a conventional 128-entry (8-way) BTB (versus 64 and 4-way in the VIA C3 Samuel processor). This small array predicts about 75% of indirect branches correctly. The BTB is also used to predict inter-segment (“far”) branches. 2.2.5 INTEGER UNIT Internal micro-instructions are executed in a tightly coupled seven-stage (integer) pipeline that is similar in structure to a basic four-stage RISC pipeline with extra stages for memory loads and stores inserted. These extra stages allow instructions that perform a load and ALU operation, or a load, ALU, and store operation to execute in one clock. 2-6 Architecture Section 2 October 2004 VIA C3 Samuel 2 Processor Datasheet The micro-instructions and associated execution units are highly tuned for the x86 architecture. The mi- cro-instructions closely resemble highly used x86 instructions. Examples of specialized hardware features supporting the x86 architecture are: hardware handling of the x86 condition codes, segment descriptor manipulation instructions, and hardware to automatically save the x86 floating-point environment. The integer execution stages are: � Decode stage (R): Micro-instructions are decoded, integer register files are accessed and resource dependencies are evaluated. � Addressing stage (A): Memory addresses are calculated and sent to the D-cache. The VIA C3 Samuel 2 processor is capable of calculating most x86 instruction address forms in one clock; a few forms containing two registers or a shifted index register require two clocks. Addresses can be automatically incremented or decremented for implementing stack and string operations. Some ALU operations are duplicated in this stage to reduce AGI (address generation interlock) stalls. For example, the sequence of adding to the stack pointer register followed by using it in a re- turn does not cause an AGI. IN general, register adds and moves are performed in the A-stage. � Cache Access stages (D, G): The D-cache and D-TLB are accessed and aligned load data returned at the end of the G-stage. The cache is fully pipelined such that a new load or store can be started and data returned each clock. � Execute stage (E): Integer ALU operations are performed. All basic ALU functions take one clock except multiply and divide. Load-ALU and Load-ALU-store instructions require only one clock (the data is loaded before the ALU stage). Results from the ALU can be forwarded to any instruc- tion following the ALU instruction using a unique result-forwarding cache. Branch instructions are evaluated in this stage and, if incorrectly predicted, the corrected branch address is sent to the I-cache during the next clock. No additional action is required for correctly predicted branches. During this stage the floating-point, MMX and 3DNow! execution units access their registers or consume the load data just delivered. These execution units “hang off” the end of the main execu- tion unit so that load-ALU operations for these units can be pipelined in one clock. � Store stage (S): Integer store data is grabbed in this stage and placed into a store buffer. Position- ing stores in this stage allows a one-clock load–ALU–store instruction. MMX and floating-point stores, however, are placed in the store buffer in a subsequent cycle due to their deep pipelines. � Write-back stage (W): The results of operations are committed to the register file. 2.2.6 D-CACHE & DATAPATH The D-cache contains 64 KB organized as four-way set associative with 32-byte lines. The associated large D-TLB contains 128 entries organized as 8-way set associative. In addition, the D-TLB includes an eight-entry page directory cache that significantly reduces the TLB miss penalty. The cache, TLB, and page directory cache all use a pseudo-LRU replacement algorithm. Associated with the D-cache are store and write buffers. All stores that pass the W-stage are placed in a four-entry store buffer (8 bytes each). Stores from the store buffer are drained to the D-cache or bus in actual program order regardless of when the data appeared in the store buffers. Stores that miss the D- cache percolate to the write buffers where they wait for the bus. If the memory region is defined as write- combining, the stores can combine in the write buffers. Section 2 Architecture 2-7 VIA C3 Samuel 2 Processor Datasheet October 2004 2.2.7 L2 CACHE The VIA C3 Samuel 2 processor contains an efficient level-2 cache. This L2 cache is exclusive (this ap- proach is sometimes called a “victim” cache). This means that the contents of the L2 cache at any point in time are not contained in the two 64-KB L1 caches. As lines are displaced from the L1 caches (due to bringing in new lines from memory), the displaced lines are placed in the L2 cache. Thus, a future L1- cache miss on this displaced line can be satisfied by returning the line from the L2 cache instead of hav- ing to access the external memory. Thus, the total effective cache size on the VIA C3 Samuel 2 processor is 192 KB (two 64-KB L1 caches and the 64-KB L2). Processors, such as the Intel Celeron processor, that have an inclusive L2 cache have a total effective cache size equal to the L2 size (128 KB in the case of the current Intel Celeron processor). This is because the contents of the L1 caches are duplicated within an inclusive L2 cache. The L2 cache is also “unified”; that is, it contains lines displaced from both the L1 I-cache and the l1 D- cache. Thus the L2 cache provides a significant assist for the cases where an I-fetch hits in the L1 data cache, or a data reference hits in the L1 I-cache. To provide correct execution semantics, these cases re- quire the hit line to be ejected from the L1 cache. The VIA C3 Samuel 2 processor L2 cache is 64 KB organized as four-way set associative with 32-byte lines and uses a use a pseudo-LRU replacement algorithm. 2.2.8 FP UNIT In addition to the integer execution unit, the VIA C3 Samuel 2 processor has a separate 80-bit floating- point execution unit that can execute x86 floating-point instructions in parallel with integer instructions. The FP unit is clocked at ½ the processor clock speed; that is, in a 800-mhz VIA C3 Samuel 2 processor, the FP-unit runs at 400 MHz. Floating-point instructions proceed through the integer R, A, D and G stages. Thus, load-ALU x86 float- ing-point instructions do not require an extra clock for the load. Floating-point instructions are then passed from the integer pipeline to the FP-unit through an 8-instruction FIFO queue (new to the VIA C3 Samuel 2 processor). This queue, which runs at the processor clock speed, decouples the slower running FP unit from the integer pipeline so that the integer pipeline can continue to process instructions over- lapped with up to eight FP instructions. Basic arithmetic floating-point instructions (add, multiply, divide, square root, compare, etc.) are repre- sented by a single internal floating-point instruction. Certain little-used and complex floating point instructions (sin, tan, etc.), however, are implemented in microcode and are represented by a long stream of instructions coming from the ROM. These instructions “tie up” the integer instruction pipeline such that integer execution cannot proceed until they complete. One floating-point instruction can issue form the FP queue to the FP unit every two clocks. The FP pipe- line is six-stages deep following the E stage. It is partially pipelined: a non-dependent add or multiply can start every two clocks. 2.2.9 MMX UNIT The VIA C3 Samuel 2 processor contains a separate execution unit for the MMX-compatible instructions. MMX instructions proceed through the integer R, A, D and G stages. Thus, load-ALU x86 MMX instruc- tions do not require an extra clock for the load. One MMX instruction can issue into the MMX unit every clock. 2-8 Architecture Section 2 October 2004 VIA C3 Samuel 2 Processor Datasheet The MMX multiplier is fully pipelined and can start one non-dependent MMX multiply[-add] instruction (which consists of up to four separate multiplies) every clock. Other MMX instructions execute in one clock. Multiplies followed by a dependent MMX instruction require two clocks. Architecturally, the MMX registers are the same as the floating-point registers. However, there are actu- ally two different register files (one in the FP-unit and one in the MMX units) that are kept synchronized by hardware. 2.2.10 3DNOW! UNIT The VIA C3 Samuel 2 processor contains a separate execution unit for the 3DNow! instructions. These instructions are compatible with the AMD K6-II processor 3DNow! instructions and provide perform- ance assists for graphics transformations via new SIMD single-precision floating-point capabilities. 3DNow! instructions proceed through the integer R, A, D and G stages. Thus, load-ALU x86 3DNow! in- structions do not require an extra clock for the load. One 3DNow! instruction can issue into 3DNow! unit every clock The 3DNow! unit has two single-precision floating-point multipliers and two single-precision floating- point adders. Other functions such as conversions, reciprocal, and reciprocal square root are provided. The multiplier and adder are fully pipelined and can start any non-dependent 3DNow! instruction every clock. 2.2.11BUS UNIT The VIA C3 Samuel 2 processor bus unit provides an external bus interface supporting bus speeds of 100 MHz and 133 MHz. The VIA C3 Samuel 2 processor bus implementation has no stalls on snoops, up to eight transactions can be generated (versus four), and stores are more heavily pipelined on the bus. 2.2.12POWER MANAGEMENT Power management is not a component but rather a pervasive feature in all components. There are two major modes: powering down components based on bus signals such as stop clock and sleep, and dy- namically powering off components during execution when they are not needed. The VIA C3 Samuel 2 processor implements the bus-controlled power management modes including: autoHALT power down state, stop grant state, sleep state, and deep sleep, or stop clock, state. While in normal running state, all major functional components are powered off when not in use. All caches, tags and TLBs are turned on and off on a clock-by-clock basis based on their usage. Other major components such as the MMX unit, the 3DNow! unit, the FP unit, and the ROM are turned on and off as used. In addition, even in blocks that are powered up, internal buses and latches hold their values when not needed to reduce dynamic power consumption. Section 2 Architecture 2-9 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION PROGRAMMING INTERFACE 3.1 GENERAL The VIA C3 Samuel 2 processor’s functions include: � All basic x86 instructions, registers, and functions � All floating-point (numeric processor) instructions, registers and functions � All basic operating modes: real mode, protect mode, virtual-8086 mode � System Management Interrupt (SMI) and the associated System Management Mode (SMM) � All interrupt and exception functions � All debug functions (including the new I/O breakpoint function) � All input/output functions � All tasking functions (TSS, task switch, etc.) � Processor initialization behavior � Page Global Enable feature The VIA C3 Samuel 2 processor, in addition to the MMX instructions, also includes instructions to boost the performance of 3D graphics compatible with the AMD 3DNow! Technology. However, there are some differences between the VIA C3 Samuel 2 processor and the Celeron processor. These differences fall into three groups: � Implementation-specific differences. Examples are cache and TLB testing features, and perform- ance monitoring features that expose the internal implementation features. These types of functions are incompatible among all different x86 implementations. Section 3 Programming Interface 3-1 VIA C3 Samuel 2 Processor Datasheet October 2004 � Omitted functions. Some Intel Celeron processor functions are not provided on the VIA C3 Sam- uel 2 processor because they aren’t used or aren’t needed in the targeted PC systems. Examples are some specific bus functions such as functional redundancy checking and performance monitoring. Other examples are architectural extensions such as support for 4-MByte pages, Page Attribute Ta- bles, etc. These types of differences are similar to those among various versions of the processors. The CPUID instruction is used by system software to determine whether these features are supported. � Low-level behavioral differences. A few low-level VIA C3 Samuel 2 processor functions are dif- ferent from Intel Celeron because the results are (1) documented in the documentation as undefined, and (2) known to be different for different x86 implementations. That is, compatibility with the In- tel Celeron processor for these functions is clearly not needed for software compatibility (or they wouldn’t be different across different implementations). This chapter summarizes the first three types of differences: additional functions, implementation-specific functions, and omitted functions. Appendix A contains more details on machine-specific functions. 3.2 ADDITIONAL FUNCTIONS The VIA C3 Samuel 2 processor includes AMD-compatible 3DNow! instructions to boost the perform- ance of 3D applications. These instructions are not defined in this datasheet but are defined in the appropriate AMD documentation. 3.3 MACHINE-SPECIFIC FUNCTIONS 3.3.1 GENERAL All x86 processor implementations provide a variety of machine-specific functions. Examples are cache and TLB testing features, and performance monitoring features that expose the internal implementation features. This section describes the VIA C3 Samuel 2 processor machine-specific functions that are most likely used by software and compares them to related processors where applicable. Appendix A describes the VIA C3 Samuel 2 processor machine-specific registers (MSRs). This section covers those features of Intel Pentium-compatible processors that are used to commonly identify and control processor features. All Pentium-compatible processors have the same mechanisms, but the bit-specific data values often differ. 3.3.2 STANDARD CPUID INSTRUCTION FUNCTIONS The CPUID instruction is available on all contemporary x86 processors. The CPUID instruction has two standard functions requested via the EAX register. The first function returns a vendor identification string in registers EBX, ECX and EDX. The second CPUID function returns an assortment of bits in EAX and EDX that identify the chip version and describe the specific features available. 3-2 Programming Interface Section 3 October 2004 VIA C3 Samuel 2 Processor Datasheet The EAX:EBX:ECX:EDX return values of the CPUID instruction executed with EAX == 0 are: Table 3-1. CPUID Return Values (EAX = 0) REGISTER[BITS] – VIA C3 SAMUEL 2 MEANING EAX (highest EAX input 1 value understood by CPUID) EBX:EDX:ECX “Centaur (vendor ID string) Hauls” The EAX return values of the CPUID instruction executed with EAX == 1 are: Table 3-2. CPUID EAX Return Values (EAX = 1) EAX BITS - MEANING VIA C3 SAMUEL 2 3:0 - Stepping ID Same as the return 7:4 - Model ID value in EDX after Reset (see next section) 11:8 - Family ID 13:12 – Type ID The EDX return values of the CPUID instruction with EAX == 1 are: Table 3-3 CPUID EDX Return Values (EAX = 1) VIA C3 EDX BITS – MEANING NOTES SAMUEL 2 0 - FPU present 1 1 - Virtual Mode Extension 0 2 - Debugging Extensions 1 3 - Page Size Extensions (4MB) 0 4 - Time Stamp Counter (TSC) supported 1 5 - Model Specific Registers present 1 6 - Physical Address Extension 0 7 - Machine Check Exception 1 8 - CMPXCHG8B instruction 0/1 1 9 - APIC supported 0 2 10- Reserved 11- Fast System Call 0 12- Memory Range Registers 1 13 - PTE Global Bit supported 1/0 3 14- Machine Check Architecture supported 0 Section 3 Programming Interface 3-3 VIA C3 Samuel 2 Processor Datasheet October 2004 VIA C3 EDX BITS – MEANING NOTES SAMUEL 2 15- Conditional Move supported 0 16- Page Attribute Table 0 17- 36-bit Page Size Extension 0 18- Processor serial number 0 19:22 - Reserved 23- MMX supported 1 24- FXSR 0 25- Streaming SIMD Extension supported 0 26:31 - Reserved Notes On CPUID Feature Flags: General: an “x/y” entry means that the default setting of this bit is x but the bit (and the underlying func- tion) can be set to y using the FCR MSR. 1. The CMPXCHG8B instruction is provided and always enabled, however, it appears disabled in the corre- sponding CPUID function bit 0 to avoid a bug in an early version of Windows NT. However, this default can be changed via a bit in the FCR MSR. 2. SMP is not supported, it has no utility in the target system environment. 3. The VIA C3 Samuel 2 processor’s support for Page Global Enable can be enabled or disabled by a bit in the FCR. The CPUID bit reports the current setting of this enable control. 3-4 Programming Interface Section 3 October 2004 VIA C3 Samuel 2 Processor Datasheet 3.3.3 EXTENDED CPUID INSTRUCTION FUNCTIONS The VIA C3 Samuel 2 processor supports extended CPUID functions. These functions provide additional information about the VIA C3 Samuel 2 processor. Extended CPUID functions are requested by execut- ing CPUID with EAX set to any value in the range 0x80000000 through 0x80000005. The following table summarizes the extended CPUID functions. Table 3-4. Extended CPUID Functions EAX TITLE OUTPUT 80000000 Largest Extended Function EAX=80000006 Input Value EBX,ECX,EDX=Reserved 80000001 Processor Signature and Fea- EAX=Processor Signature ture Flags EBX,ECX=Reserved EDX=Extended Feature Flags 80000002 Processor Name String EAX,EBX,ECX,EDX 80000003 Processor Name String EAX,EBX,ECX,EDX 80000004 Processor Name String EAX,EBX,ECX,EDX 80000005 TLB and L1 Cache Information EAX = Reserved EBX = TLB Information ECX = L1 Data Cache Information EDX = L1 Instruction Cache Information 80000006 L2 Cache Information EAX, EBX, EDX = Reserved ECX = L2 Cache Information Largest Extended Function Input Value (EAX==0x80000000) Returns 0x80000006 in EAX, the largest extended function input value. Processor Signature and Feature Flags (EAX==0x80000001) Returns processor version information in EAX, this value is identical to the value of EDX after RESET. Returns feature flags in EDX, this value is identical to the value in EDX after CPUID standard function 1, with the exception of bit 31: EDX[31]=0 3DNow! instructions not supported. EDX[31]=1 3DNow! instructions supported. Note that if FCR[20]=0 then 3DNow! instructions are not supported and EDX[31] will be 0. Processor Name String (EAX==0x80000002–0x80000004) Returns the name of the processor, suitable for BIOS to display on the screen (ASCII). The string can be up to 48 characters in length. If the string is shorter, the rightmost characters are padded with zero. The leftmost characters go in EAX, then EBX, ECX, and EDX. The leftmost character goes in least signifi- cant byte (little endian). Section 3 Programming Interface 3-5 VIA C3 Samuel 2 Processor Datasheet October 2004 For example, the string “VIA Samuel 2” would be returned by extended function EAX=0x80000002 as follows: EAX = 0x20414956 EBX = 0x756D6153 ECX = 0x32206C65 EDX = 0x00000000 Since the string is less than 17 bytes, the extended functions EAX=0x80000003 and EAX=0x80000004 return zero in EAX, EBX, ECX, and EDX. L1 Cache Information (EAX == 0x80000005) Returns information about the implementation of the TLBs and caches: Table 3-5. L1 Cache & TLB Configuration Encoding REGISTER DESCRIPTION VALUE EAX Reserved EBX TLB Information EBX[31:24] D-TLB associativity 8 EBX[23:16] D-TLB # entries 128 EBX[15: 8] I-TLB associativity 8 EBX[ 7: 0] I-TLB # entries 128 ECX L1 Data Cache Information ECX[31:24] Size (Kbytes) 64 ECX[23:16] Associativity 4 ECX[15: 8] Lines per Tag 1 ECX[ 7: 0] Line Size (bytes) 32 EDX L1 Instruction Cache Information EDX[31:24] Size (Kbytes) 64 EDX[23:16] Associativity 4 EDX[15: 8] Lines per Tag 1 EDX[ 7: 0] Line Size (bytes) 32 L2 Cache Information (EAX == 0x80000006) Returns information about the implementation of the L2 cache: Table 3-6. L2 Cache Configuration Encoding REGISTER DESCRIPTION VALUE EAX, EBX, EDX Reserved 3-6 Programming Interface Section 3 October 2004 VIA C3 Samuel 2 Processor Datasheet ECX L2 Data Cache Information ECX[31:24] Size (Kbytes) 64 ECX[23:16] Associativity 4 ECX[15: 8] Lines per Tag 1 ECX[ 7: 0] Line Size (bytes) 32 3.3.4 PROCESSOR IDENTIFICATION The VIA C3 Samuel 2 processor provides several machine-specific features. These features are identified by the standard CPUID function EAX=1. Other machine-specific features are controlled by VIA C3 Samuel 2 MSRs. Some of these features are not backward-compatible with the predecessors in the IDT WinChip family. System software must not assume that all future processors in the VIA processor family will implement all of the same machine-specific features or even that these features will be implemented in a backward- compatible manner. In order to determine if the processor supports particular machine-specific features, system software should follow the following procedure. Identify the processor as a member of the VIA processor family by checking for a Vendor Identification String of “CentaurHauls” using CPUID with EAX=0. Once this has been verified, system software must determine the processor version in order to properly configure the machine-specific registers. In general system software can determine the processor version by comparing the Family and Model Identification fields returned by the CPUID standard function EAX=1. If the processor version is not recognized then system software must not attempt to activate any machine- specific feature. 3.3.5 EDX VALUE AFTER RESET. After reset the EDX register holds a component identification number as follows: 31:14 13:12 11:8 7:4 3:0 EDX Reserved Type ID Family ID Model ID Stepping ID 18 2 4 4 4 The specific values for the VIA C3 Samuel 2 processor are: PROCESSOR TYPE ID FAMILY ID MODEL ID STEPPING ID VIA C3 Samuel 2 0 6 7 Varies 3.3.6 CONTROL REGISTER 4 (CR4) Control register 4 (CR4) controls some of the advanced features of the Celeron processor. The VIA C3 Samuel 2 processor provides a CR4 with the following specifics: Section 3 Programming Interface 3-7 VIA C3 Samuel 2 Processor Datasheet October 2004 Table 3-7. CR4 Bits VIA C3 CELERON CELERON CR4 BITS - MEANING NOTES SAMUEL 2 MODEL 6 MODEL 8 0: VME: Enables VME feature 0 0/1 0/1 1 1: PVI: Enables PVI feature 0 0/1 0/1 1 2: TSD: Makes RDTSC inst privileged 0/1 0/1 0/1 3: DE: Enables I/O breakpoints 0/1 0/1 0/1 4: PSE: Enables 4-MB pages 0 0/1 0/1 1 5: PAE: Enables address extensions r r r 6: MCE: Enables machine check exception 0/1 0/1 0/1 2 7: PGE: Enables global page feature 0/1 0/1 0/1 8: PCE: Enables RDPMC for all levels 0/1 0/1 0/1 9: OSFXSR: Enables FXSAVE//FXRSTOR Support r r 0/1 10: OSXMMEXCPT: O/S Unmasked Exception Support r r 0/1 31:11 - reserved r r r Notes On CR4 General: a “0/1” means that the default setting of this bit is 0 but the bit can be set to (1). A “0” means that the bit is always 0; it cannot be set. An “r” means that this bit is reserved. It appears as a 0 when read, and a GP exception is signaled if an attempt is made to write a 1 to this bit. 1. The VIA C3 Samuel 2 processor does not provide this “Appendix H” function and this CR4 bit cannot be set. However, no GP exception occurs if an attempt is made to set this bit. The Cyrix 6x86MX processor also does not provide this function. 2. The VIA C3 Samuel 2 processor Machine Check has different specifics than the Machine Check function of compatible processors. 3.3.7 MACHINE-SPECIFIC REGISTERS The VIA C3 Samuel 2 processor implements the concept of Machine Specific Registers (MSRs). RDMSR and WRMSR instructions are provided and the CPUID instruction identifies that the VIA C3 Samuel 2 processor supports MSRs. In general, the MSRs have no usefulness to application or operating system software and are not used. (This is to be expected since the MSRs are different on each processor). Appendix A contains a detailed description of the VIA C3 Samuel 2 processor’s MSRs. 3.4 OMITTED FUNCTIONS This section summarizes those functions are not in the VIA C3 Samuel 2 processor. Symmetric Multiprocessing Support: APIC This bus function is omitted since the target market for the VIA C3 Samuel 2 processor is portables and typical desktop systems (which do not support APIC multiprocessing). 3-8 Programming Interface Section 3 October 2004 VIA C3 Samuel 2 Processor Datasheet A bit in the feature identification return from the CPUID instruction indicates whether this feature is pre- sent or not. This enhancement is not provided on the VIA C3 Samuel 2 processor. Other Functions There are other functions that are not implemented in the VIA C3 Samuel 2 processor. These are identi- fied accordingly in the CPUID feature flags, Conditional Move instructions, Page Attribute Tables, 4- Mbyte pages, 36-bit Page Size Extension and FXSAVE/FXRSTOR instructions. The VIA C3 Samuel 2 processor does contain an L2 cache. Model specific registers pertaining to the L2 cache are detailed in Appendix A. Model specific registers pertaining to APIC, Machine Check, and De- bug and Trace features are not supported. Section 3 Programming Interface 3-9 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION HARDWARE INTERFACE 4.1 BUS INTERFACE The VIA C3 Samuel 2 processor bus interface is commonly referred to as the Socket 370 interface. The majority of the pins within the bus interface are involved with the physical memory and I/O interface. The remaining pins are power and ground pins, test and debug support pins and various ancillary control functions. The pins and associated functions are listed and described in this section. 4.1.1 DIFFERENCES The areas where the VIA C3 Samuel 2 processor differs from compatible processors should not cause op- erational compatibility issues. These differences are: � Bus-to-core Ratio Control � Bus Frequency Control � Probe Mode / JTAG / TAP Port (see Test and Debug Section) Bus-to-Core Frequency Ratio Control The VIA C3 Samuel 2 processor supports both fused and software control of the bus-to-core frequency ratio. At reset, the factory-set, fused ratio is used. This ratio can then be adjusted via software. This ad- justment lasts until the next reset. Software can adjust the bus-to-core ratio by writing the desired ratio into the second bus control register (BCR2), enabling software ratio control, configuring the programmable interrupt controller to cause an interrupt in 1ms, and executing the HALT instruction. Further information is contained in Appendix A. Sample code and more detailed description of this mechanism is described in the VIA C3 Samuel 2 Proc- essor BIOS Writers' Guide. Section 4 Hardware Interface 4-1 VIA C3 Samuel 2 Processor Datasheet October 2004 Bus Frequency Selection The VIA C3 Samuel 2 processor supports automated bus frequency selection through the BSEL pins. The BSEL pins are used as a mechanism whereby the processor and the system board can negotiate to support high frequency bus frequencies. The standard BSEL decoding is shown in Table 4-1. While the VIA C3 Samuel 2 processor is designed to operate at bus frequencies of 66, 100, or 133 MHz, performance is improved by running at higher bus frequencies. Various speed bins preclude 133 MHz op- eration because the available bus-to-core ratios do not permit operation at the desired core MHz. Processors from these speed bins indicate this by shorting the BSEL[1] pin to ground internal to the pack- age. For these processors the BSEL[0] pin is left floating. Processors from speed bins which permit 133 MHz bus operation indicate this by allowing both BSEL[1] and BSEL[0] to float. It is anticipated that motherboards will pull up both BSEL pins. The resulting BSEL-indicated bus fre- quency will then be either 100 MHz or 133 MHz according to speed bin. Bus operation at 66MHz is not desirable. Table 4-1. BSEL Frequency Mapping BSEL[1] BSEL[0] BUS FREQUENCY 0 0 66 MHz 0 1 100 MHz 1 0 Reserved 1 1 133 MHz 4.1.2 CLARIFICATIONS Power Supply Voltage The VIA C3 Samuel 2 processor automatically controls its core processor power supply voltage with the VID pins. The VID mapping is in Table 4-2. Note that the VIA C3 Samuel 2 does not specify a VID4 pin. 4-2 Hardware Interface Section 4 October 2004 VIA C3 Samuel 2 Processor Datasheet Table 4-2. Core Voltage Settings VID3 VID2 VID1 VID0 VCORE 1 1 1 1 1.30V 1 1 1 0 1.35V 1 1 0 1 1.40V 1 1 0 0 1.45V 1 0 1 1 1.50V 1 0 1 0 1.55V 1 0 0 1 1.60V 1 0 0 0 1.65V 0 1 1 1 1.70V 0 1 1 0 1.75V 0 1 0 1 1.80V 0 1 0 0 1.85V 0 0 1 1 1.90V 0 0 1 0 1.95V 0 0 0 1 2.00V 0 0 0 0 2.05V VCCCMOS The VIA C3 Samuel 2 processor routes the VCC1.5 pin to the VCCCMOS pin via the package. This signal is not used by the processor, but is intended to be used by the system as the power supply for CMOS level signals. VCCCMOS should not be expected to source more than 250mA. RESET# The VIA C3 Samuel 2 processor is reset by the assertion of the RESET# pin. Current versions of the VIA C3 Samuel 2 processor connect this pin to X-4 in the Socket370 pinout. Future versions of the VIA C3 Samuel 2 processor may relocate RESET# to AH-4 in the Socket370 pin- out. Board designers should always connect RESET# to both AH-4 and X-4 to ensure compatibility with all VIA processors. Thermal Monitoring The VIA C3 Samuel 2 processor supports thermal monitoring via the THERMDN and THERMDP pins. However, it does not support the THERMTRIP# pin. The THERMTRIP# pin should be treated as re- served. 4.1.3 OMISSIONS Driver Termination The VIA C3 Samuel 2 processor requires external termination. Section 4 Hardware Interface 4-3 VIA C3 Samuel 2 Processor Datasheet October 2004 System boards must terminate signals to ensure correct operation. Advanced Peripheral Interrupt Controller (APIC) The APIC is not supported by the VIA C3 Samuel 2 processor. The APIC pins (PICCLK, PICD0, and PICD1) are specified as reserved, and should not be connected on the motherboard. Breakpoint and Performance Monitoring Signals The VIA C3 Samuel 2 processor internally supports instruction and data breakpoints. However, the VIA C3 Samuel 2 processor does not support the external indication of breakpoint matches via the BP3-BP0 pins. Similarly, the VIA C3 Samuel 2 processor contains performance monitoring hooks internally, but it does not support the indication of performance monitoring events on PM1-PM0. The associated pins are unconnected on the VIA C3 Samuel 2 processor package. Error Checking The VIA C3 Samuel 2 processor does not support error checking. The BERR#, BINIT#, AERR#, AP#[1:0], DEP#[7:0], IERR#, RP#, and RSP# pins do not exist and should be treated as reserved. V COREDET The VIA C3 Samuel 2 processor does not connect to the VCOREDET pin. RTTCTRL The VIA C3 Samuel 2 processor does not connect to the RTTCTRL pin. Future VIA processors may use the RTTCTRL pin to control integrated I/O pull-ups. SLEWCTRL The VIA C3 Samuel 2 processor does not connect to the SLEWCTRL pin. Future VIA processors may connect to the SLEWCTRL pin. EDGCTRL The VIA C3 Samuel 2 processor does not connect to the EDGECTRL pin. PWDGD The VIA C3 Samuel 2 processor does not connect to the PWRGD pin. Future VIA processors may con- nect to the PWRGD pin. 4.2 PIN DESCRIPTION Table 4-3. Pin Descriptions Pin Name Description I/O Clock A[31:3]# The address Bus provides addresses for physical memory and external I/O devices. I/O BCLK During cache inquiry cycles, A31#-A3# are used as inputs to perform snoop cycles. A20M# A20 Mask causes the CPU to make (force to 0) the A20 address bit when driving the I(1.5V) ASYNC external address bus or performing an internal cache access. A20M# is provided to emulate the 1 MByte address wrap-around that occurs on the 8086. Snoop addressing is not affected. ADS# Address Strobe begins a memory/I/O cycle and indicates the address bus (A31#-A3#) I/O BCLK and transaction request signals (REQ#) are valid. 4-4 Hardware Interface Section 4 October 2004 VIA C3 Samuel 2 Processor Datasheet Pin Name Description I/O Clock BCLK Bus Clock provides the fundamental timing for the VIA C3 Samuel 2 CPU. The fre- I(2.5V) -- quency of the VIA C3 Samuel 2 CPU input clock determines the operating frequency of the CPU’s bus. External timing is defined referenced to the rising edge of CLK. BNR# Block Next Request signals a bus stall by a bus agent unable to accept new transac- I/O BCLK tions. BPRI# Priority Agent Bus Request arbitrates for ownership of the system bus. I BCLK BSEL[1:0] Bus Selection Bus provides system bus frequency data to the CPU. I BCLK BR0# BR0# drives the BREQ[0]# signal in the system to request access to the system bus. I/O None CPUPRES# CPU Present is grounded inside the processor to indicate to the system that a proces- O None sor is present. D[63:0]# Data Bus signals are bi-directional signals which provide the data path between the VIA I/O BCLK C3 Samuel 2 CPU and external memory and I/O devices. The data bus must assert DRDY# to indicate valid data transfer. DBSY# Data Bus Busy is asserted by the data bus driver to indicate data bus is in use. I/O BCLK DEFER# Defer is asserted by target agent (e.g., north bridge) and indicates the transaction can- I BCLK not be guaranteed as an in-order completion. DRDY# Data Ready is asserted by data driver to indicate that a valid signal is on the data bus. I/O BCLK FERR# FPU Error Status indicates an unmasked floating-point error has occurred. FERR# is O(1.5V) ASYNC asserted during execution of the FPU instruction that caused the error. FLUSH# Flush Internal Caches writing back all data in the modified state. I(1.5V) ASYNC HIT# Snoop Hit indicates that the current cache inquiry address has been found in the cache I/O BCLK (exclusive or shared states). HITM# Snoop Hit Modified indicates that the current cache inquiry address has been found in I/O BCLK the cache and dirty data exists in the cache line (modified state). IGNNE# Ignore Numeric Error forces the VIA C3 Samuel 2 CPU to ignore any pending un- I(1.5V) ASYNC masked FPU errors and allows continued execution of floating point instructions. INIT# Initialization resets integer registers and does not affect internal cache or floating point I(1.5V) ASYNC registers. INTR Maskable Interrupt I(1.5V) ASYNC NMI Non-Maskable Interrupt I(1.5V) ASYNC LOCK# Lock Status is used by the CPU to signal to the target that the operation is atomic. I/O BCLK REQ[4:0]# Request Command is asserted by bus driver to define current transaction type. I/O BCLK RESET# Resets the processor and invalidates internal cache without writing back. I BCLK RS[2:0]# Response Status signals the completion status of the current transaction when the I BCLK CPU is the response agent. SLP# Sleep, when asserted in the stop grant state, causes the CPU to enter the sleep state. I(1.5V) ASYNC SMI# System Management (SMM) Interrupt forces the processor to save the CPU state to I(1.5V) ASYNC the top of SMM memory and to begin execution of the SMI services routine at the be- ginning of the defined SMM memory space. An SMI is a high-priority interrupt than NMI. STPCLK# Stop Clock causes the CPU to enter the stop grant state. I(1.5V) ASYNC TRDY# Target Ready indicates that the target is ready to receive a write or write-back transfer I BCLK from the CPU. VID[3:0] Voltage Identification Bus informs the regulatory system on the motherboard of the O(1.5V) ASYNC CPU Core voltage requirements. Section 4 Hardware Interface 4-5 VIA C3 Samuel 2 Processor Datasheet October 2004 4.3 POWER MANAGEMENT The VIA C3 Samuel 2 processor provides both static and dynamic power management. The VIA C3 Samuel 2 processor supports five power management modes: NORMAL state, STOP GRANT state, AUTOHALT state, SLEEP state, and DEEPSLEEP state. The VIA C3 Samuel 2 processor uses dynamic power management techniques to reduce power consump- tion in the NORMAL state. In NORMAL state, the on-chip arrays, selected datapaths, and the associated control logic are powered down when not in use. In addition, units which are in use attempt to minimize switching of inactive nodes. � NORMAL state is the normal operating state for the processor � STOP GRANT state is the low power state where most of the processor clocks do not toggle. It is entered when the STPCLK# signal is asserted. Snoop cycles are supported in this state. � AUTO HALT state is the low power state where most of the processor clocks do not toggle. It is entered when the processor executes the HALT instruction. Snoop cycles are supported in this state. � SLEEP state is the very low power state where only the processor's PLL (phase lock loop) toggles. It is entered from STOP GRANT state when the processor samples the SLP# signal asserted. Snoop cycles that occur while in SLEEP state or during a transition into or out of SLEEP state will cause unpredictable behavior. � DEEP SLEEP state is the lowest power state. It is entered when the BCLK signal is stopped while the processor in is the SLEEP state. Snoop cycles will be completely ignored in this state. 4.4 TEST & DEBUG 4.4.1 BIST A Built-in Self-Test (BIST) can be requested as part of the VIA C3 Samuel 2 processor reset sequence by holding INIT# asserted as RESET# is de-asserted. The VIA C3 Samuel 2 processor BIST performs the following general functions: � A hardware-implemented exhaustive test of (1) all internal microcode ROM, and (2) the X86 in- struction decode, instruction generation and entry point generation logic. � An extensive microcode test of all internal registers and datapaths. � An extensive microcode test of data and instruction caches, their tags, and associated TLBs. BIST requires about four million internal clocks. EAX Value After Reset The result of a BIST is indicated by a code in EAX. Normally EAX is zero after reset. If a BIST is re- quested as part of the Reset sequence, EAX contains the BIST results. A 0 in EAX after BIST Reset means that no failures were detected. Any value other than zero indicates an error has occurred during BIST. 4-6 Hardware Interface Section 4 October 2004 VIA C3 Samuel 2 Processor Datasheet 4.4.2 JTAG The VIA C3 Samuel 2 processor has a JTAG scan interface that is used for test functions and the proprie- tary Debug Port. However, the VIA C3 Samuel 2 processor does not provide a fully compatible IEEE 1149.1 JTAG function. From a practical user viewpoint, JTAG does not exist and the associated pins (TCLK, and so forth) should not be used. 4.4.3 DEBUG PORT Certain processors have a proprietary Debug Port which uses the JTAG scan mechanism to control inter- nal debug features (“probe mode”). These interfaces are not documented and are available (if at all) only under a non-disclosure agreement. The VIA C3 Samuel 2 processor does not have a debug interface. Section 4 Hardware Interface 4-7 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION ELECTRICAL SPECIFICATIONS 5.1 AC TIMING TABLES Table 5-1. Clock Switching Characteristics SYMBOL PARAMETER MIN MAX UNIT FIGURENOTES F BCLK Frequency 66 133 MHz t BCLK Period 7.5 15 ns 1 t BCLK High Time 1.4 ns 2V 2 t BCLK Low Time 1.4 ns 0.8V 3 t BCLK Fall Time 0.4 1.6 ns 2V-0.8V 4 t BCLK Rise Time 0.4 1.6 ns 2V-0.8V 5 T BCLK Period Stability ps 7 ±250 Table 5-2. Output Delay Timings SYMBOL PARAMETER MIN MAX UNIT FIGURENOTES t Output Valid Delay H->L 0.40 3.25 ns (1) 7A t Output Valid Delay L->H 3.25 ns (1) 7B t Input Setup Time 0.95 ns (1) 8 t Input Hold Time 1.0 ns (1) 9 t RESET# Pulse Width 1.0 ms (1) 10 Notes: 1. Valid delay timings for these signals are specified into an idealized 50ohm resistor to 1.5V with VREF at 1.0V. Minimum values guaranteed by design. Section 5 Electrical Specifications 5-1 VIA C3 Samuel 2 Processor Datasheet October 2004 5.2 DC SPECIFICATIONS 5.2.1 RECOMMENDED OPERATING CONDITIONS Functional operation of the VIA C3 Samuel 2 processor is guaranteed if the conditions in Table 5-3 are met. Sustained operation outside of the recommended operating conditions may damage the device. Table 5-3. Recommended Operating Conditions PARAMETER MIN NOM MAX UNITS NOTES Operating Case Temperature 0 85 °C V Voltage 1.60/1.65 V CORE V Static Tolerance -0.080 0.040 V (1) CORE V Dynamic Tolerance -0.130 0.080 V (2) CORE V Voltage 1.365 1.635 V TT V -2% 2/3 V +2% V REF TT V – 2.5 V Supply Voltage 2.375 2.625 V 2.5 V – 1.5V Supply Voltage 1.365 1.635 V 1.5 Notes: 1. DC measurement 2. AC noise measured with bandwidth limited to 20MHz. 5.2.2 MAXIMUM RATINGS While functional operation is not guaranteed beyond the operating ranges listed in Table 5-4, the device may be subjected to the limits specified in Table 5-5 without causing long-term damage. These conditions must not be imposed on the device for a sustained period—any such sustained imposi- tion may damage the device. Likewise exposure to conditions in excess of the maximum ratings may damage the device. Table 5-4. Maximum Ratings PARAMETER MIN MAX UNITS NOTES Operating Case Temperature -65 110 °C Storage Temperature -65 150 °C Supply Voltage (V) -0.5 4.0 V CC CMOS I/O Voltage -0.5 V+0.5 V CMOS I/O Voltage -0.5 V+0.5 V TT 5-2 Electrical Specifications Section 5 October 2004 VIA C3 Samuel 2 Processor Datasheet 5.2.3 DC CHARACTERISTICS Table 5-5. DC Characteristics PARAMETER MINMAXUNITSNOTES I – Low level output current -9.0 mA @ V = V OL OL(max) V - High Level Output Voltage V V OH TT V - Low Level Output Voltage 0 0.4 V @ I = -8mA OL ol I – Input Leakage Current L ± 15 µA I – Input Leakage Current for inputs with pull-ups 200 µA LU I – Input Leakage Current for inputs with pull-downs -400 µA LD Table 5-6. CMOS DC Characteristics PARAMETER MIN MAX UNITSNOTES V - Input Low Voltage -0.58 0.700 V IL V - Input High Voltage V + 0.2 V V (2) IH1.5 REF TT V - Input High Voltage 2.0 3.18 V (3) IH2.5 V – Low Level Output Voltage 0.40 V @ I OL OL V - High Level Output Voltage V V (1) OH CMOS I - Low Level Output Current 9 mA @ V OL OL I - Input Leakage Current LI ±100 µA I - Output Leakage Current ±100 µA LO Notes: 1. All CMOS signals are open drain. 2. Applies to all CMOS signals except BCLK. 3. Applies only to BCLK. 5.2.4 POWER DISSIPATION Table 5-7 through Table 5-11 give the core power consumption for the VIA C3 Samuel 2 processor at the various operating frequencies at 1.6 Volts. Note that this does not include the power consumed by the I/O pads. Section 5 Electrical Specifications 5-3 VIA C3 Samuel 2 Processor Datasheet October 2004 Table 5-8. Normal Mode V Power Consumption @ 1.6V DD 3,4 1,2 PARAMETER TYPICAL MAX UNITS NOTES P - Normal Mode Operating Power Con- DD sumption VIA C3 Samuel 2 700 (7.0 X 100 MHz) 5.81 9.88 W VIA C3 Samuel 2 733 (5.5 X 133 MHz) 6.09 10.35 W VIA C3 Samuel 2 750 (7.5 X 100 MHz) 6.23 10.59 W VIA C3 Samuel 2 800 (6.0 X 133 MHz) 6.65 11.30 W VIA C3 Samuel 2 800 (8.0 X 100 MHz) 6.65 11.30 W Notes: 1. Not 100% tested or guaranteed. Consider these power numbers as an average of all parts and some deviation is expected. 2. The above power consumption is preliminary and based on 85°C case and 1.6 Volts. 3. Typical power is defined as the average power dissipated while running WinStone99 Win98. Contact your VIA Sales Representative for further information. 4. Thermal solutions must be designed to account for worst-case core and I/O power consumption. Table 5-9. StopGrant V Power Consumption @ 1.6V DD 1,2 PARAMETER MAX UNITS NOTES P – StopGrant / AutoHalt Mode Operating No snooping activ- DD Power Consumption ity VIA C3 Samuel 2 700 (7.0 X 100 MHz) 0.99 W VIA C3 Samuel 2 733 (5.5 X 133 MHz) 1.04 W VIA C3 Samuel 2 750 (7.5 X 100 MHz) 1.06 W VIA C3 Samuel 2 800 (6.0 X 133 MHz) 1.13 W VIA C3 Samuel 2 800 (8.0 X 100 MHz) 1.13 W Notes: 1. Not 100% tested or guaranteed. Consider these power numbers as an average of all parts and some deviation is expected. 2. The above power consumption is preliminary and based on 85°C case and 1.6 Volts. Table 5-10. Sleep V Power Consumption @ 1.6V DD 1 PARAMETER MAX UNITS NOTES P – Sleep Mode Operating Power Consump- DD tion VIA C3 Samuel 2 700 (7.0 X 100 MHz) 0.98 W VIA C3 Samuel 2 733 (5.5 X 133 MHz) 1.02 W VIA C3 Samuel 2 750 (7.5 X 100 MHz) 1.05 W VIA C3 Samuel 2 800 (6.0 X 133 MHz) 1.12 W VIA C3 Samuel 2 800 (8.0 X 100 MHz) 1.12 W Notes: 1. Not 100% tested or guaranteed. Consider these power numbers as an average of all parts and some deviation is expected. 5-4 Electrical Specifications Section 5 October 2004 VIA C3 Samuel 2 Processor Datasheet 2. The above power consumption is preliminary and based on 85°C case and 1.6 Volts. Table 5-11. Deep Sleep VDD Power Consumption @ 1.6V 1 PARAMETER MAX UNITS NOTES P – Deep Sleep Mode Operating Power DD Consumption VIA C3 Samuel 2 700 (7.0 X 100 MHz) 0.46 W VIA C3 Samuel 2 733 (5.5 X 133 MHz) 0.46 W VIA C3 Samuel 2 750 (7.5 X 100 MHz) 0.46 W VIA C3 Samuel 2 800 (6.0 X 133 MHz) 0.46 W VIA C3 Samuel 2 800 (8.0 X 100 MHz) 0.46 W Notes: 1. Not 100% tested or guaranteed. Consider these power numbers as an average of all parts and some deviation is expected. 2. The above power consumption is preliminary and based on 85°C case and 1.6 Volts. Table 5-12. VSS-I/O Power Consumption PARAMETER TYPICAL MAX UNITS NOTES Pss-I/O – I/O Operating 300 820 mW Power Consumption Section 5 Electrical Specifications 5-5 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION MECHANICAL SPECIFICATIONS 6.1 CPGA PACKAGE The VIA C3 Samuel 2 processor is available in a Ceramic Pin Grid Array (CPGA) package. The VIA C3 Samuel 2 processor’s CPGA package is mechanically compatible with the ceramic and plastic staggered pin grid array (SPGA and PPGA) packages. Section 6 Mechanical Specifications 6-1 VIA C3 Samuel 2 Processor Datasheet October 2004 Figure 6-1. CPGA Pinout (Pinside View) 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 34 35 36 37 AN AN VSS A12# A16# A6# VTT RSV VTT BPRI# DEFER# VTT RSV TRDY# DRDY# BR0# ADS# RSV RSV RSV AM AM RSV VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1 AL AL VSS VSS A15# A13# A9# RSV VTT A7# REQ4# REQ3# VTT HITM# HIT# DBSY# THRMDN THRMDP RSV VID0 VID2 AK AK VCC VSS A28# A3# A11# VREF6 A14# VTT REQ0# LOCK# VREF7 RSV RSV RS2# RSV RSV VCC VSS AJ AJ A21# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BSEL1# BSEL0# SMI# VID3 AH AH VSS RSV A10# A5# A8# A4# BNR# REQ1# REQ2# VTT RS1# VCC RS0# RSV SLP# VCC VSS VCC AG AG RSV A19# VSS INIT STPCLK# IGNNE# AF AF VCC RSV A25# VSS VCC VSS AE AE A17# A22# VCC A20M# RSV FLUSH# AD AD VREF5 VCC VSS A31# VSS V1.5 AC AC RSV A20# VSS VSS FERR# RSV AB AB VCC A24# A23# VSS VCC VCMOS AA AA A27# A30# VCC VTT VTT VCC Z Z A18# VCC VSS A29# VSS V2.5 Y Y RSV A26# VSS RSV VCC VSS X X RSV RESET# RSV VSS VCC VSS W W D0# RSV VCC PLL1 RSV BCLK VIA Cyrix III V V VSS RSV VREF4 VCC VSS VCC U U D4# D15# VSS PLL2 VTT VTT CPGA T T VCC D1# D6# VSS VCC VSS S S (PIN SIDE VIEW) VTT VTT D8# D5# VCC RSV R R VREF3 VCC RSV D17# VSS VCC Q Q D12# D10# VSS RSV RSV RSV P P VCC D18# D9# VSS VCC VSS N N D2# D14# VCC RSV RSV RSV M M D3# VCC VSS D11# VSS INTR L L D13# D20# VSS RSV RSV NMI K K VCC VREF2 D24# VCC VCC VSS J J D7# D30# VCC RSV RSV RSV H H VSS D16# D19# VCC VSS VCC G G D21# D23# VSS RSV VTT RSV F F D32# VCC VCC D22# RSV D27# VCC D63# VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS E E D26# VSS VCC VSS VCC VSS VCC VSS RSV VTT D62# RSV D25# VCC RSV RSV VREF0 RSV RSV D D VSS VSS VCC D38# D39# D42# D41# D52# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC C C D33# VCC D31# D34# D36# D45# D49# D40# D59# D55# D54# D58# D50# D56# RSV RSV RSV RSV CPUPRES# B B D35# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC RSV A A D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# RSV RSV RSV RSV VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 6-2 Mechanical Specifications Section 6 October 2004 VIA C3 Samuel 2 Processor Datasheet Table 6-1. CPGA Pin Cross Reference Address Data Control Power/Other V V V Reserved CC TT ss Pin Pin No. Pin Pin No. Pin Name Pin No. Pin Name Pin No. Pin No. Pin No. Pin No. Pin No. Name Name A3# AK-8 D0# W-1 A20M# AE-33 CPUPRES# C-37 AA-37 AH-20AM-22 AK-24 A4# AH-12 D1# T-4 ADS# AN-31 PLL1 W-33 AA-5 AK-16AM-26 AL-11 A5# AH-8 D2# N-1 BCLK W-37 PLL2 U-33 AB-2 AL-13AM-30 AN-13 A6# AN-9 D3# M-6 BNR# AH-14 AD-36 AB-34 AL-21 AM-34 V-4 V 1.5 A7# AL-15 D4# U-1 BPRI# AN-17 Z-36 AD-32 AN-11 AM-6 B-36 V 2.5 A8# AH-10 D5# S-3 BR0# AN-29 AB-36 AE-5 AN-15 AN-3 G-33 V CMOS A9# AL-9 D6# T-6 BSEL0 AJ-33 VID0 AL-35 E-5 G-35 B-12 E-37 A10# AH-6 D7# J-1 BSEL1 AJ-31 VID1 AM-36 E-9 AA-33 B-16 C-35 A11# AK-10 D8# S-1 DBSY# AL-27 VID2 AL-37 F-14 AA-35 B-20 E-35 A12# AN-5 D9# P-6 DEFER# AN-19 VID3 AJ-37 F-2 AN-21 B-24 X-2 A13# AL-7 D10# Q-3 DRDY# AN-27 V E-33 F-22 E-23 B-28 C-33 REF0 A14# AK-14 D11# M-4 FERR# AC-35 V F-18 F-26 S-33 B-32 C-31 REF1 A15# AL-5 D12# Q-1 FLUSH# AE-37 V K-4 F-30 S-37 B-4 A-33 REF2 A16# AN-7 D13# L-1 HIT# AL-25 R-6 F-34 U-35 B-8 A-31 V REF3 A17# AE-1 D14# N-3 HITM# AL-23 V-6 F-4 U-37 D-18 E-31 V REF4 A18# Z-6 D15# U-3 IGNNE# AG-37 AD-6 H-32 D-2 C-29 V REF5 A19# AG-3 D16# H-4 INIT# AG-33 AK-12 H-36 D-22 E-29 V REF6 A20# AC-3 D17# R-4 INTR M-36 AK-22 J-5 D-26 A-29 V REF7 A21# AJ-1 D18# P-4 NMI L-37 THERMDN AL-29 K-2 D-30 J-33 A22# AE-3 D19# H-6 LOCK# AK-20 THERMDP AL-31 K-32 D-34 J-35 A23# AB-6 D20# L-3 REQ0# AK-18 K-34 D-4 L-35 A24# AB-4 D21# G-1 REQ1# AH-16 M-32 Z-34 A-35 A25# AF-6 D22# F-8 REQ2# AH-18 N-5 E-11 G-37 A26# Y-3 D23# G-3 REQ3# AL-19 P-2 E-15 L-33 A27# AA-1 D24# K-6 REQ4# AL-17 P-34 E-19 N-33 A28# AK-6 D25# E-3 RESET# X-4 R-32 E-7 N-35 A29# Z-4 D26# E-1 RS0# AH-26 R-36 F-20 N-37 A30# AA-3 D27# F-12 RS1# AH-22 S-5 F-24 Q-33 A31# AD-4 D28# A-5 RS2# AK-28 T-2 F-28 Q-35 D29# A-3 SLP# AH-30 T-34 F-32 Q-37 D30# J-3 SMI# AJ-35 V-32 F-36 R-2 D31# C-5 STPCLK# AG-35 V-36 G-5 W-35 D32# F-6 TRDY# AN-25 W-5 H-2 Y-1 D33# C-1 X-34 H-34 AK-30 D34# C-7 Y-35 K-36 AM-2 D35# B-2 Z-32 L-5 F-10 D36# C-9 AF-2 M-2 AN-23 D37# A-9 AH-24 M-34 AC-37 Section 6 Mechanical Specifications 6-3 VIA C3 Samuel 2 Processor Datasheet October 2004 Address Data Control Power/Other V V V Reserved CC TT ss Pin Pin No. Pin Pin No. Pin Name Pin No. Pin Name Pin No. Pin No. Pin No. Pin No. Pin No. Name Name D38# D-8 AH-32 P-32 AL-33 D39# D-10 AH-36 P-36 AN-35 D40# C-15 AJ-13 A-37 AN-37 D41# D-14 AJ-17 AB-32 AH-28 D42# D-12 AJ-21 AC-33 AK-32 D43# A-7 AJ-25 AC-5 AN-33 D44# A-11 AJ-29 AD-2 AK-26 D45# C-11 AJ-5 AD-34 S-35 D46# A-21 AK-2 AF-32 E-27 D47# A-15 AK-34 AF-36 AG-1 D48# A-17 AM-12 AG-5 AH-4 D49# C-13 AM-16 AH-2 E-21 D50# C-25 AM-20 AH-34 AC-1 D51# A-13 AM-24 AJ-11 W-3 D52# D-16 AM-28 AJ-15 AF-4 D53# A-23 AM-32 AJ-19 X-6 D54# C-21 AM-4 AJ-23 Y-33 D55# C-19 AM-8 AJ-27 J-37 D56# C-27 B-10 AJ-3 AE-35 D57# A-19 B-14 AJ-7 D58# C-23 B-18 AK-36 D59# C-17 B-22 AK-4 D60# A-25 B-26 AL-1 D61# A-27 B-30 AL-3 D62# E-25 B-34 AM-10 D63# F-16 B-6 AM-14 C-3 AM-18 D-20 Q-5 D-24 R-34 D-32 T-32 D-36 T-36 D-6 U-5 E-13 V-2 E-17 V-34 AJ-9 X-32 D-28 X-36 AF-34 Y-37 Y-5 Z-2 6-4 Mechanical Specifications Section 6 October 2004 VIA C3 Samuel 2 Processor Datasheet Table 6-2. CPGA with Heat Slug Dimensions Table 6-3. CPGA Package Dimensions Millimeters Inches Symbol Typical Min Max Notes Typical Min Max Notes A 1.96 1.76 2.16 0.077 0.069 0.085 A1 1.00 typical 0.039 typical A2 2.96 2.72 3.33 0.116 0.107 0.131 B 0.046 0.41 0.51 0.018 0.016 0.020 φ D 49.53 49.28 49.83 1.950 1.940 1.962 D1 45.72 45.47 45.97 1.8 1.790 1.810 D2 25.4 25.02 25.78 1.00 0.985 1.015 e1 2.54 2.41 2.67 0.100 0.095 0.105 L 3.18 2.98 3.38 0.125 0.117 0.133 N 370 Lead 370 Lead count count S1 1.905 1.65 2.16 0.075 0.065 0.085 Section 6 Mechanical Specifications 6-5 VIA C3 Samuel 2 Processor Datasheet October 2004 Table 6-4. Non Heat Slug CPGA Package Dimensions 6-6 Mechanical Specifications Section 6 October 2004 VIA C3 Samuel 2 Processor Datasheet SECTION THERMAL SPECIFICATIONS 7.1 INTRODUCTION The VIA C3 Samuel 2 is specified for operation with device case temperatures in the range of 0°C to 85°C. Operation outside of this range will result in functional failures and potentially damage the device. Care must be taken to ensure that the case temperature remains within the specified range at all times dur- ing operation. An effective heat sink with adequate airflow is therefore a requirement during operation. 7.2 TYPICAL ENVIRONMENTS Typical thermal solutions involve three components: a heat sink, an interface material between the heat sink and the package, and a source of airflow. The best thermal solutions rely on the use of all three com- ponents. To the extent that any of these components are not used, the other components must be improved to compensate for such omission. In particular, the use of interface material such as thermal grease, silicone paste, or graphite paper can make a 40°C difference in the case temperature Likewise, the imposition of airflow is realistically a requirement. 7.3 MEASURING T C The case temperature (T ) should be measured by attaching a thermocouple to the center of the VIA C3 C Samuel 2 package. The heat produced by the processor is very localized so measuring the case tempera- ture anywhere else will underestimate the case temperature. The presence of a thermocouple is inherently invasive; effort must be taken to minimize the effect of the measurement. The thermocouple should be attached to the processor through a small hole drilled in the Section 7 Thermal Specifications 7-1 VIA C3 Samuel 2 Processor Datasheet October 2004 heat sink. Thermal grease should be used to ensure that the thermocouple makes good contact with the package, but the thermocouple should not come in direct contact with the heat sink. Physical Test Conditions Case temperature measurements should be made in the worst case operating environments. Ideally, sys- tems should be maximally configured, and tested at the worst-case ambient temperature. Test Patterns During normal operation the processor attempts to minimize power consumption. Consequently, normal power consumption is much lower than the maximum power consumption. Thermal testing should be done while running software which causes the processor to operate at its thermal limits. 7.4 MEASURING T J The junction temperature of the die can be measured by using the processor’s on-chip diode. 7.5 ESTIMATING T C The VIA C3 Samuel 2 processor’s case temperature can be estimated based on the general characteristics of the thermal environment. This estimate is not intended as a replacement for actual measurement. Case temperature can be estimated from Table 7-1 below, where, T ≡ Ambient Temperature A T ≡ Case Temperature C θ ≡ case-to-ambient thermal resistance CA θ ≡ junction-to-ambient thermal resistance JA θ ≡ junction-to-case thermal resistance JC P ≡ power consumption (Watts) and, T = T + (P * θ ) J C JC T = T – (P * θ ) A J JA T = T – (P * θ ) A C CA θ = θ – θ CA JA JC 7-2 Thermal Specifications Section 7 October 2004 VIA C3 Samuel 2 Processor Datasheet Table 7-1. CPGA θ and θ JC JA θ (°C/WATT) VS. LAMINAR AIRFLOW JA (LINEAR FT/MIN) Heat Sink in Inches 0 100 200 400 600 800 θ (°C/Watt) JC (height) 0.25 0.8 9.1 8.0 6.6 4.5 3.6 3.0 0.35 0.8 8.8 7.5 6.0 4.0 3.3 2.8 0.45 0.8 8.4 7.0 5.3 3.6 2.9 2.5 0.55 0.8 8.1 6.5 4.7 3.2 2.6 2.3 0.65 0.8 7.7 6.0 4.3 3.0 2.4 2.1 0.80 0.8 7.0 5.3 3.9 2.8 2.2 2.0 1.00 0.8 6.3 4.7 3.6 2.6 2.1 1.8 1.20 0.8 5.9 4.3 3.3 2.4 2.0 1.8 1.40 0.8 5.4 3.9 3.0 2.2 1.9 1.7 No Heat Sink 1.2 14.3 13.0 11.6 8.7 7.3 6.4 Environment: these estimates assume the use of thermal grease between the processor and the heat sink. Heat sinks are 1.95” square. Section 7 Thermal Specifications 7-3 October 2004 VIA C3 Samuel 2 Processor Datasheet APPENDIX MACHINE SPECIFIC REGISTERS A.1 GENERAL Tables A-1 and A-2 summarize the VIA C3 Samuel 2 processor machine-specific registers (MSRs). Fur- ther description of each MSR follows the table. MSRs are read using the RDMSR instruction and written using the WRMSR instruction. There are four basic groups of MSRs (not necessarily with contiguous addresses). Other than as defined below, a reference to an undefined MSR causes a General Protection exception. 1. Generally these registers can have some utility to low-level programs (like BIOS). Note that some of the MSRs (address 0 to 0x4FF) have no function in the VIA C3 Samuel 2 proces- sor. These MSRs do not cause a GP when used on the VIA C3 Samuel 2 processor; instead, reads to these MSRs return zero, and writes are ignored. Some of these undocumented MSRs may have ill side effects when written to indiscriminately. Do not write to undocumented MSRs. 2. There are some undocumented internal-use MSRs used for low-level hardware testing purposes. At- tempts to read or write these undocumented MSRs cause unpredictable and disastrous results; so don’t use MSRs that are not documented in this datasheet! 3. MSRs used for cache and TLB testing. These use MSR addresses that are not used on compatible processor. These test functions are very low-level and complicated to use. They are not documented in this datasheet but the information will be provided to customers given an appropriate justification MSRs are not reinitialized by the bus INIT interrupt; the setting of MSRs is preserved across INIT. Table A-1. Category 1 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES Appendix A Machine Specific Registers A-1 VIA C3 Samuel 2 Processor Datasheet October 2004 MSR MSR NAME ECX EDX EAX TYPE NOTES TSC Time Stamp Counter 10h TSC[63:32] TSC[31:0] RW EBL_CR_POWERON EBL_CR_POWERON 2Ah n/a Control bits RW PERFCTR0 Performance counter 0 C1h TSC[39:32] TSC[31:0] RW 1 PERFCTR1 Performance counter 1 C2h 0 Count[31:0] RW BBL_CR_CTL3 L2 Hardware Disabled 11Eh n/a 00800000h RO EVNTSEL0 Event counter 0 select 186h n/a 00470079h RO 1 EVNTSEL1 Event counter 1 select 187h n/a Control bits RW MTRR MTRRphysBase0 200h Control bits Control bits RW MTRR MTRRphysMask0 201h Control bits Control bits RW MTRR MTRRphysBase1 202h Control bits Control bits RW MTRR MTRRphysMask1 203h Control bits Control bits RW MTRR MTRRphysBase2 204h Control bits Control bits RW MTRR MTRRphysMask2 205h Control bits Control bits RW MTRR MTRRphysBase3 206h Control bits Control bits RW MTRR MTRRphysMask3 207h Control bits Control bits RW MTRR MTRRphysBase4 208h Control bits Control bits RW MTRR MTRRphysMask4 209h Control bits Control bits RW MTRR MTRRphysBase5 20Ah Control bits Control bits RW MTRR MTRRphysMask5 20Bh Control bits Control bits RW MTRR MTRRphysBase6 20Ch Control bits Control bits RW MTRR MTRRphysMask6 20Dh Control bits Control bits RW MTRR MTRRphysBase7 20Eh Control bits Control bits RW MTRR MTRRphysMask7 20Fh Control bits Control bits RW MTRR MTRRfix64K_00000 250h Control bits Control bits RW MTRR MTRRfix16K_80000 258h Control bits Control bits RW MTRR MTRRfix16K_A0000 259h Control bits Control bits RW MTRR MTRRfix4K_C0000 268h Control bits Control bits RW MTRR MTRRfix4K_C8000 269h Control bits Control bits RW MTRR MTRRfix4K_D0000 26Ah Control bits Control bits RW MTRR MTRRfix4K_D8000 26Bh Control bits Control bits RW MTRR MTRRfix4K_E0000 26Ch Control bits Control bits RW MTRR MTRRfix4K_E8000 26Dh Control bits Control bits RW MTRR MTRRfix4K_F0000 26Eh Control bits Control bits RW MTRR MTRRfix4K_F8000 26Fh Control bits Control bits RW MTRR MTRRdefType 2FFh Control bits Control bits RW Notes: 1. PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR that reflects this limitation. A-2 Machine Specific Registers Appendix A October 2004 VIA C3 Samuel 2 Processor Datasheet Table A-2. Category 2 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES FCR Feature Control Reg 1107h n/a FCR value RW FCR2 Feature Control Reg 2 1108h FCR2_Hi FCR2 value RW 1 FCR3 Feature Control Reg 3 1109h FCR3_Hi FCR3 value WO 1 Notes: 1. FCR2 and FCR3 provide system software with the ability to specify the Vendor ID string returned by the CPUID instruction. A.2 CATEGORY 1 MSRS 10H: TSC (TIME STAMP COUNTER) VIA C3 Samuel 2 processor has a 64-bit MSR that materializes the Time Stamp Counter (TSC). System increments the TSC once per processor clock. The TSC is incremented even during AutoHalt or Stop- Clock. A WRMSR to the TSC will clear the upper 32 bits of the TSC. 2AH: EBL_CR_POWERON 31:27 26 25:22 21:20 19:18 17:15 14 13 12:0 Res LowPow- BF Res BSEL Res 1MPOV IOQDepth Reserved '11000 erEn (Ignored on write; ' returns 0 on '1' read) 5 1 4 2 2 3 1 1 13 IOQDepth: 0 = In Order Queue Depth with up to 8 transactions 1 = 1 transaction 1MPOV: 0 = Power on Reset Vector at 0xFFFFFFF0 (4Gbytes) 1 = Power on Reset Vector at 0x000FFFF0 (1 Mbyte) BSEL: 01 = 133 MHz Bus 10 = 100 MHz Bus Appendix A Machine Specific Registers A-3 VIA C3 Samuel 2 Processor Datasheet October 2004 BF: Bus Clock Frequency Ratio 0000 5.0 0010 4.0 0011 10.0 0100 5.5 0101 3.5 0110 4.5 0111 11.0 1000 9.0 1001 7.0 1010 8.0 1011 6.0 1100 12.0 1101 7.5 1110 13.0 1111 6.5 LowPowerEn: This bit always set to '1' C1H-C2H: PERFCTR0 & PERFCTR1 These are events counters 0 and 1. VIA C3 Samuel 2 processor’s PERFCTR0 is an alias for the lower 40 bits of the TSC. 11EH: BBL_CR_CTL3 31:24 23 22:0 Reserved L2_Hdw_Disable Reserved (Ignored on write; ‘1’ returns 0 on read) 8 1 23 The VIA C3 Samuel 2 processor does contain an L2 cache. For compatibility, this read-only MSR indi- cates to the BIOS or system software that the L2 is disabled even if the L2 is enabled. L2_Hdw_Disable: This bit always set to '1' A-4 Machine Specific Registers Appendix A October 2004 VIA C3 Samuel 2 Processor Datasheet 186H: EVNTSEL0 (EVENT COUNTER 0 SELECT) 31:24 23:16 15:9 8:0 Reserved Reserved Reserved CTR0 Event Select = 79h 8 8 7 9 PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR which reflects this limitation. The CTR0_Event Select field always returns 0x0079, which corresponds to counting of processor clocks. 187H: EVNTSEL1 (EVENT COUNTER 1 SELECT) 31:24 23:16 15:9 8:0 Reserved Reserved Reserved CTR1 Event Select 8 8 7 9 VIA C3 Samuel 2 processor have two MSRs that contain bits defining the behavior of the two hardware event counters: PERFCTR0 and PERFCTR1. The CTR1_Event_Select control field defines which of several possible events is counted. The possible Event Select values for PERFCTR1 are listed in the table below. Note that CTR1_Event_Select is a 9-bit field. The EVNTSEL1 register should be written before PERFCTR1 is written to initialize the counter. The counts are not necessarily perfectly exact; the counters are intended for use over a large number of events and may differ by one or two counts from what might be expected. Most counter events are internal implementation-dependent debug functions having no meaning to soft- ware. The counters that can have end-user utility are: EVENT DESCRIPTION C0h Instructions executed 1C0h Instructions executed and string iterations 79h Internal clocks (default event for CTR0) A.3 CATEGORY 2 MSRs 1107H: FCR (FEATURE CONTROL REGISTER) The FCR controls the major optional feature capabilities of the VIA C3 Samuel 2 processor. Table A-3 contains the bit values for the FCR. The default settings shown for the FCR bits are not necessarily exact. The actual settings can be changed as part of the manufacturing process and thus a particular VIA C3 Samuel 2 processor version can have slightly different default settings than shown here. All reserved bit values of the FCR must be preserved by using a read-modify-write sequence to update the FCR. Appendix A Machine Specific Registers A-5 VIA C3 Samuel 2 Processor Datasheet October 2004 Table A-3. FCR Bit Assignments BIT NAME DESCRIPTION DEFAULT 0 ALTINST Reserved for test & special uses 0 1 ECX8 Enables CPUID reporting CX8 0 2 Reserved 0 3 Reserved 0 4 Reserved 0 5 DSTPCLK Disables supporting STPCLK 0 6 Reserved 0 7 EPGE Enables CR4.PGE and CPUID.PGE (Page Global Enable) 1 8 DL2 Disables L2 Cache 0 9 Reserved 1 10 Reserved 0 11 DPDC Disables Page Directory cache 0 12 EBRPRED Enables Branch Prediction 1 13 DIC Disables I-Cache 0 14 DDC Disables D-Cache 0 15 1 Reserved 16 Reserved 1 17 Reserved 1 18 Reserved 0 19 Reserved 1 20 Reserved 1 21 Reserved 1 22:25 SID Stepping ID 0 26 Reserved 0 27 Reserved 0 28 Reserved 1 29 0 Reserved 30 Reserved 0 31 Reserved 1 A-6 Machine Specific Registers Appendix A October 2004 VIA C3 Samuel 2 Processor Datasheet ALTINST: 0 = Normal x86 instruction execution. 1 = Alternate instruction set execution is enabled (see details below) ECX8: 0 = The CPUID instruction does not report the presence of the CMPXCHG8B instruction (CX8 = 0). The instruction actually exists and operates correctly, however. 1 = The CPUID instruction reports that the CMPXCHG8B instruction is supported (CX8 = 1). DSTPCLK: 0 = STPCLK interrupt properly supported. 1 = Ignores SPCLK interrupt. EPGE: 0 = The processor does not support Page Global Enable and therefore CPUID Feature Flags reports EDX[13]=0; attempts to set CR4.PGE are ignored. 1 = The processor supports Page Global Enable and therefore CPUID Feature Flags re- ports EDX[13]=1; CR4.PGE can be set to 1. DL2: 0 = L2 Cache enabled. 1 = L2 Cache disabled. DPDC: 0 = Enables use of internal Page Directory Cache. 1 = Disables use of internal Page Directory Cache. EBRPRED: 0 = Disables branch prediction function. 1 = Enables branch prediction function. DIC: 0 = Enables use of I-Cache. 1 = Disables use of I-Cache: cache misses are performed as single transfer bus cycles, PCD is de-asserted. This overrides any setting of CR0.CD and CR0.NW. DDC: 0 = Enables use of D-Cache. 1 = Disables use of D-Cache: same semantics as for DIC except for D-Cache. ALTERNATE INSTRUCTION EXECUTION When set to 1, the ALTINST bit in the FCR enables execution of an alternate (not x86) instruction set. While setting this FCR bit is a privileged operation, executing the alternate instructions can be done from any protection level. This alternate instruction set includes an extended set of integer, MMX, floating-point, and 3DNow! in- structions along with additional registers and some more powerful instruction forms over the x86 instruction architecture. For example, in the alternate instruction set, privileged functions can be used from any protection level, memory descriptor checking can be bypassed, and many x86 exceptions such as alignment check can be bypassed. This alternate instruction set is intended for testing, debug, and special application usage. Accordingly, it is not documented for general usage. If you have a justified need for access to these instructions, contact your VIA representative. The mechanism for initiating execution of this alternate set of instructions is as follows: Appendix A Machine Specific Registers A-7 VIA C3 Samuel 2 Processor Datasheet October 2004 1. Set the FCR ALTINST bit to 1 using WRMSR instruction (this is a privileged instruction). This should be done using a read-modify-write sequence to preserve the values of other FCR bits. 2. The ALTINST bit enables execution of a new x86 jump instruction that starts execution of alter- nate instructions. This new jump instruction can be executed from any privilege level at any time that ALTINST is 1. The new jump instruction is a two-byte instruction: 0x0F3F. If ALTINST is 0, the execution of 0x0F3F causes an Invalid Instruction exception. 3. When executed, the new 0x0F3F x86 instruction causes a near branch to CS:EAX. That is, the branch function is the same as the existing x86 instruction � jmp [eax] � In addition to the branch, the 0x0F3F instruction sets the processor into an internal mode where the target bytes are not interpreted as x86 instructions but rather as alternate instruction set instructions. 4. The alternate instructions fetched following the 0x0F3F branch should be of the form � 0x8D8400XXXXXXXX where 0xXXXXXXXX is the 32-bit alternate instruction � That is, the alternate instructions are presented as the 32-bit displacement of a � LEA [EAX+EAX+disp] � instruction. This example assumes that the current code segment size is 32-bits, if it is 16-bits, then an address size prefix (0x67) must be placed in front of the LEA opcode. 5. Upon fetching, the LEA “wrapper” is stripped off and the 32-bit alternate instruction contained in the displacement field is executed. 6. The alternate instruction set contains a special branch instruction that returns control to x86 fetch and execute mode. The x86 state upon return is not necessarily what it was when alternate instruc- tion execution is entered since the alternate instructions can completely modify the x86 state. While all VIA C3 processor processors contain this alternate instruction feature, the invocation details (e.g., the 0x8D8400 “prefix”) may be different between processors. Check the appropriate processor data- sheet for details. 1108H: FCR2 (FEATURE CONTROL REGISTER 2) This MSR contains more feature control bits — many of which are undefined. It is important that all re- served bits are preserved by using a read-modify-write sequence to update the MSR. 63:32 Last 4 characters of Alternate Vendor ID string 31:15 14 13:12 11:8 7:4 3:0 Reserved AVS Res Family ID Model ID Res 17 1 2 4 4 4 AVS: 0 = The CPUID instruction vendor ID is “CentaurHauls” 1 = The CPUID instruction returns the alternate Vendor ID. The first 8 characters of the alternate Vendor ID are stored in FCR3 and the last 4 characters in FCR2[63:32]. These A-8 Machine Specific Registers Appendix A October 2004 VIA C3 Samuel 2 Processor Datasheet 12 characters are undefined after RESET and may be loaded by system software using WRMSR. Family ID: This field will be returned as the family ID field by subsequent uses of the CPUID in- struction Model ID: This field will be returned as the model ID field by subsequent uses of the CPUID in- struction 1109H: FCR (FEATURE CONTROL REGISTER 3) This MSR contains the first 8 characters of the alternate Vendor ID. The alternate Vendor ID is returned by the CPUID instruction when FCR2[AVS] is set to ‘1’. FCR3 is a write-only MSR. 63:32 First 4 characters of Alternate Vendor ID string 31:0 Middle 4 characters of Alternate Vendor ID string 1147H: BCR2 (BUS CONTROL REGISTER 2) Certain bits in BCR2 register are used to program the processor’s clock multiplier. The table below con- tains the bit values for the BCR2. The default settings shown for the BCR2 bits are not necessarily exact within a VIA C3 Samuel 2 model line. The actual settings can be changed as part of the manufacturing process and the thus a particular VIA C3 Samuel 2 processor version can have slightly different default settings than shown here. All reserved bit values of BCR2 must be preserved by using a read-modify- write sequence to update the BCR2. Table A-3. VIA C3 Samuel 2 BCR2 Assignments BIT Name Description Default 18:0 Reserved 0/1 19 ESOFTBF Enables Software Clock Multiplier 0 22:20 Reserved 0/1 26:23 CLOCKMUL Software Clock Multiplier 0 31:27 Reserved 0/1 ESOFTBF: 0 = Software Clock Multiplier is disabled. 1 = Software Clock Multiplier is enabled. Once this is set, the processor will switch to the value in [26:23] on the next AUTOHALT transition. The duration of the AUTOHALT should be >=1ms to ensure the CPU’s internal PLL is resynchronized. For AUTOHALT, this means interrupts must be disabled except for the time tick, which should be reset to >=1ms. Care must be taken to avoid other system events that could interfere with this op- eration. A few examples are snooping, NMI, INIT, SMI and FLUSH. Appendix A Machine Specific Registers A-9