VIA TECHNOLOGIES C3 Nehemiah

VIA C3 Nehemiah Processor Datasheet Revision 1.13 September 29, 2004 VIA TECHNOLOGIES, INC. VIA C3 Nehemiah Processor Datasheet September 29, 2004 This is Version 1.13 of the VIA C3 Nehemiah Processor Datasheet. © 2003-2004 VIA Technologies, Inc All Rights Reserved. VIA reserves the right to make changes in its products without notice in order to improve design or performance characteristics. This publication neither states nor implies any representations or warranties of any kind, including but not limited to any implied warranty of merchantability or fitness for a particular purpose. No license, express or implied, to any intellectual property rights is granted by this document. VIA makes no representations or warranties with respect to the accuracy or completeness of the con- tents of this publication or the information contained herein, and reserves the right to make changes at any time, without notice. VIA disclaims responsibility for any consequences resulting from the use of the information included herein. Cyrix and VIA C3 are trademarks of VIA Technologies, Inc. CentaurHauls is a trademark of Centaur Technology Corporation. AMD, AMD K6, and Athlon are trademarks of Advanced Micro Devices, Inc. Microsoft and Windows are registered trademarks of Microsoft Corporation. Intel, Pentium, Celeron, and MMX are registered trademarks of Intel Corporation. Other product names used in this publication are for identification purposes only and may be trade- marks of their respective companies. LIFE SUPPORT POLICY VIA processor products are not authorized for use as components in life support or other medical devices or systems (hereinafter life support devices) unless a specific written agreement pertaining to such intended use is executed be- tween the manufacturer and an officer of VIA. 1. Life support devices are devices which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. This policy covers any component of a life support device or system whose failure to perform can cause the failure of the life support device or system, or to affect its safety or effectiveness. September 29, 2004 VIA C3 Nehemiah Processor Datasheet Revision History Document Release Date Revision Initials Initial external release 1.0 11/26/03 EY Updated table 5-3 1.10 3/11/04 JW Updated POWERGOOD information in figures 4-5, 4-6 and 1.11 07/30/04 JW table 3-3 Updated table 4-13 1.12 9/1/04 JW Updated table A-3 1.13 9/29/04 JW Revision History i VIA C3 Nehemiah Processor Datasheet September 29, 2004 This page is intentionally left blank. ii Revision History September 29, 2004 VIA C3 Nehemiah Processor Datasheet Table of Contents INTRODUCTION .........................................................................................................................................................1-1 1.1 DATASHEET OUTLINE ....................................................................................................................1-1 1.2 BASIC FEATURES ...........................................................................................................................1-2 1.3 PROCESSOR VERSIONS...................................................................................................................1-3 1.4 COMPATIBILITY.............................................................................................................................1-4 PROGRAMMING INTERFACE..................................................................................................................................2-1 2.1 GENERAL .......................................................................................................................................2-1 2.2 ADDITIONAL FUNCTIONS...............................................................................................................2-3 2.3 ACHINE-SPECIFIC FUNCTIONS........................................................................................................2-4 2.3.1 general.......................................................................................................................................2-4 2.3.2 standard cpuid instruction functions.........................................................................................2-4 2.3.3 extended cpuid instruction functions.........................................................................................2-6 2.3.4 centaur extended cpuid instruction functions............................................................................2-9 2.3.5 processor identification...........................................................................................................2-10 2.3.6 edx value after reset ................................................................................................................2-10 2.3.7 control register 4 (cr4)............................................................................................................2-11 2.3.8 Machine-Specific Registers.....................................................................................................2-11 2.4 OMITTED FUNCTIONS...................................................................................................................2-12 HARDWARE INTERFACE .........................................................................................................................................3-1 3.1 BUS INTERFACE .............................................................................................................................3-1 3.1.1 differences .................................................................................................................................3-2 3.1.2 clarifications .............................................................................................................................3-3 3.1.3 omissions...................................................................................................................................3-6 3.2 PIN DESCRIPTION ...........................................................................................................................3-7 3.3 POWER MANAGEMENT.................................................................................................................3-10 3.4 TEST & DEBUG ............................................................................................................................3-12 3.4.1 bist...........................................................................................................................................3-12 3.4.2 jtag ..........................................................................................................................................3-12 3.4.3 debug port ...............................................................................................................................3-12 ELECTRICAL SPECIFICATIONS .............................................................................................................................4-1 4.1 AC TIMING TABLES ........................................................................................................................4-1 4.2 DC SPECIFICATIONS .....................................................................................................................4-12 4.2.1 recommended operating conditions ........................................................................................4-12 4.2.2 maximum ratings.....................................................................................................................4-14 4.2.3 dc characteristics ....................................................................................................................4-15 4.2.4 power dissipation ....................................................................................................................4-16 MECHANICAL SPECIFICATIONS............................................................................................................................5-1 5.1 CPGA PACKAGE .............................................................................................................................5-1 5.2 EBGA PACKAGE .............................................................................................................................5-7 THERMAL SPECIFICATIONS ...................................................................................................................................6-1 6.1 INTRODUCTION..............................................................................................................................6-1 6.2 TYPICAL ENVIRONMENTS..............................................................................................................6-1 6.3 MEASURING T ..............................................................................................................................6-2 C Table of Contents i VIA C3 Nehemiah Processor Datasheet September 29, 2004 6.4 MEASURING T ...............................................................................................................................6-2 J 6.5 ESTIMATING T ..............................................................................................................................6-3 C MACHINE SPECIFIC REGISTERS.......................................................................................................................... A-1 A.1 GENERAL ...................................................................................................................................... A-1 A.2 CATEGORY 1 MSRS ....................................................................................................................... A-4 A.3 CATEGORY 2 MSRS ....................................................................................................................... A-8 ii Table of Contents September 29, 2004 VIA C3 Nehemiah Processor Datasheet List of Figures Figure 4-1. BCLK Generic Clock Timing Waveform.....................................................................................................4-5 Figure 4-2. Valid Delay Timings.....................................................................................................................................4-5 Figure 4-3. Setup and Hold Timings ...............................................................................................................................4-6 Figure 4-4. Cold/Warm Reset and Configuration Timings .............................................................................................4-6 Figure 4-5. Power-on Sequence and Reset Timings........................................................................................................4-7 Figure 4-6. Power Down Sequencing and Timings (VCC Leading)...............................................................................4-8 Figure 4-7. Power Down Sequencing and Timings (VTT Leading) ...............................................................................4-9 Figure 4-8. Stop Grant/Sleep Timing (SLP# assertion method)....................................................................................4-10 Figure 4-9. Stop Grant/Deep Sleep Timing (BCLK Stopping method) ........................................................................4-11 Figure 5-1. CPGA Pinout (Pinside View) .......................................................................................................................5-2 Figure 5-2. CPGA with Heat Slug Dimensions...............................................................................................................5-5 Figure 5-3. CPGA Top Marking Design .........................................................................................................................5-6 Figure 5-4. EBGA Ball Diagram (Bottom View)............................................................................................................5-8 Figure 5-5. EBGA Mechanical Specification................................................................................................................5-13 Figure 5-6. EBGA Top Marking Design.......................................................................................................................5-14 List of Figures i VIA C3 Nehemiah Processor Datasheet September 29, 2004 List of Tables Table 3-1. BSEL Frequency Mapping.............................................................................................................................3-2 Table 3-2. Core Voltage Settings ....................................................................................................................................3-4 Table 3-3. Pin Descriptions .............................................................................................................................................3-7 Table 3-4. BGA only Pin Descriptions............................................................................................................................3-8 Table 3-5. Clock Ratio ....................................................................................................................................................3-9 1 Table 4-1: System Bus Clock AC Specifications (133 MHz) ........................................................................................4-1 1 Table 4-2. System Bus Clock AC Specifications (100 MHz) ........................................................................................4-2 1,8 Table 4-3. Bus Signal Groups AC Specifications ........................................................................................................4-2 1,2 Table 4-4. CMOS and Open-drain Signal GROUPS AC Specifications .....................................................................4-3 Table 4-5. Reset Configuration AC Specifications and Power On/Power Down Timings .............................................4-3 1 Table 4-6. APIC Bus Signal AC Specifications .............................................................................................................4-4 1, 3, 4 Table 4-7. StopGrant / Sleep / Deep Sleep AC Specifications .................................................................................4-4 Table 4-8. Recommended Operating Conditions ..........................................................................................................4-12 Table 4-9. V Static and Transient Tolerance..............................................................................................................4-13 CC Table 4-10. Maximum Ratings......................................................................................................................................4-14 Table 4-11. DC Characteristics .....................................................................................................................................4-15 Table 4-12. CMOS DC Characteristics .........................................................................................................................4-15 Table 4-13. Thermal Design Power Information...........................................................................................................4-16 Table 4-14. VTT-I/O Power Consumption......................................................................................................................4-16 Table 5-1. CPGA Pin Cross Reference ...........................................................................................................................5-3 Table 5-2. CPGA Package Dimensions...........................................................................................................................5-5 Table 5-3. EBGA Ball Cross Reference..........................................................................................................................5-9 Table A-1. Category 1 MSRs ......................................................................................................................................... A-2 Table A-2. Category 2 MSRs ......................................................................................................................................... A-3 Table A-3. FCR Bit Assignments................................................................................................................................... A-8 ii List of Tables September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION INTRODUCTION The VIA C3 Nehemiah processor is based on a unique internal architecture and is manufactured using an advanced 0.13µ CMOS technology. This architecture and process technology provides a highly compati- ble, high-performance, low-cost and low-power solution for the desktop PC, notebook and Internet Appliance markets. The VIA Nehemiah family also provides Padlock, a suite a security technologies. The VIA C3 Nehemiah processor is available in several GHz versions. When considered individually, the compatibility, function, performance, cost and power dissipation of the VIA C3 Nehemiah processor family are all very competitive. When considered as a whole, the VIA C3 Nehemiah processor family offers a breakthrough level of value. 1.1 DATASHEET OUTLINE The intent of this datasheet is to make it easy for a direct user—a board designer, a system designer, or a BIOS developer—to use the VIA C3 Nehemiah processor. In the datasheet, Section 1 summarizes the key features of the VIA C3 Nehemiah processor. Section 2 specifies the primary programming interface and Section 3 does the same for the bus interface. Sections 4, 5, and 6 specify the classical datasheet topics of AC timings, pinouts and mechanical specifications. Appendix A documents the VIA C3 Nehemiah processor machine specific registers (MSRs). Section 1 Architecture 1-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 1.2 BASIC FEATURES The VIA C3 Nehemiah processor family currently consists of two basic models with several different GHz versions. Due to its low power dissipation, the two models are ideally suited for both desktop and mobile applications. All versions share the following common features (except as noted): � Padlock Advanced Cryptography Engine (available in Stepping 8 and higher). � Padlock Random Number Generator (available in Stepping 3 and higher). � Plug-compatible with Socket 370 processors in terms of bus protocol, electrical interface, and physical package � Software-compatible with thousands of x86 software applications available � MMX-compatible instructions � SSE-compatible instructions � Two large (64-KB each, 4-way) on-chip caches (2-way in Stepping 8 and higher) � 64-KB Level 2 victim cache (16-way) � Two large TLBs (128 entries each, 8-way) � Branch Target Address Cache with 1k entries each identifying 2 branches � Unique and sophisticated branch prediction mechanisms � Bus speeds up to 133 MHz � Extremely low power dissipation 2 2 � Very small die-52 mm in TSMC 0.13µ technology (47 mm for Stepping 8 and higher) 1-2 Architecture Section 1 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 1.3 PROCESSOR VERSIONS Typically, there are five specification parameters that characterize different versions of a processor family: package, voltage, maximum case temperature, external bus speed and internal MHz. The VIA C3 Nehemiah processor family is offered in a variety of packages: a Universal370-compatible ceramic PGA and an enhanced BGA (EBGA). The current nominal voltage is defined based on the dif- ferent versions available. The Universal370 VID pins define the voltage. The internal MHz of a particular VIA C3 Nehemiah processor chip is defined by two parameters: the specified external bus speed and the internal bus-clock multiplier. VIA C3 Nehemiah processors operate the bus at 133 MHz bus. (VIA C3 Nehemiah can also operate at 66 or 100 MHz bus speeds.) Bus fre- quency select pins (BSEL 0 and BSEL 1) identify the appropriate bus speed. The bus-clock multiplier is hardwired into each VIA C3 Nehemiah processor chip. That is, the ratio of the 1 internal processor clock speed to the externally supplied bus clock is frozen for a particular chip . Several different clock-multiplier versions are currently offered. More information on these topics is included in Sections 4, 5, and 6 of this datasheet � The VIA C3 Nehemiah processor is initially available with a variety of speeds: • 1.00 GHz (7.5 x 133-MHz bus) • 1.13 GHz (8.5 x 133-MHz bus) • 1.20 GHz (9.0 x 133-MHz bus) � The VIA C3 Nehemiah processor will provide other speed grades, bus speed combinations and dif- ferent core voltages for the future. 1 Actually, it is semi-frozen. A VIA-unique machine specific register allows programming to temporarily change the hard-wired multiplier. This capability, documented in Appendix A, is intended for special BIOS situations as well as test and debug usage. Section 1 Architecture 1-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 1.4 COMPATIBILITY A VIA C3 Nehemiah processor can plug into existing Socket 370 motherboards and it can operate with- out any changes on the system. No special jumper or different board wiring is required. In some cases, however, a special BIOS is needed. Currently, BIOS support for the VIA C3 Nehemiah processor is available from Award, AMI, Phoenix and Insyde. The VIA C3 Nehemiah processor integrates external termination of bus signals. Physical and bus com- patibility is covered in more detail in Section 4 of this datasheet. The VIA C3 Nehemiah processor supports SSE instructions. The VIA C3 Nehemiah processor currently does not support multiple processors; however future versions may implement dual processors support. These functions are defined as optional by, and are identified to software via, the CPUID instruction. The VIA C3 Nehemiah processor carefully follows the protocol for defining the availability of these optional features. Both the additional and omitted optional features are described in detail in Section 2 of this data- sheet. To verify compatibility of the VIA C3 Nehemiah processor with real PC applications and hardware, VIA has performed extensive testing of hundreds of PC boards and peripherals, thousands of software applica- tions and all known operating systems. 1-4 Architecture Section 1 September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION PROGRAMMING INTERFACE 2.1 GENERAL The VIA C3 Nehemiah processor’s functions include: � All basic x86 instructions, registers, and functions � All floating-point (numeric processor) instructions, registers and functions � All basic operating modes: real mode, protect mode, virtual-8086 mode � System Management Interrupt (SMI) and the associated System Management Mode (SMM) � All interrupt and exception functions � All debug functions (including the new I/O breakpoint function) � All input/output functions � All tasking functions (TSS, task switch, etc.) � Processor initialization behavior � Page Global Enable feature Besides the MMX instructions, the VIA C3 Nehemiah processor also includes SSE instructions to boost the performance of 3D graphics. Section 2 Programming Interface 2-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 However, there are some differences between the VIA C3 Nehemiah processor and the Celeron processor. These differences fall into three groups: � Implementation-specific differences. Examples are cache and TLB testing features, and perform- ance monitoring features that expose the internal implementation features. These types of functions are incompatible among all different x86 implementations. � Omitted functions. Some Intel Celeron processor functions are not provided on the VIA C3 Ne- hemiah processor because they are not used or unnecessary for the targeted PC systems. Examples of some specific bus functions: functional redundancy checking and performance monitoring. Other examples of architectural extensions: support for Physical Address Extensions and JTAG boundary scan. These types of differences are similar to those among various versions of the processors. With the CPUID instruction, the system software can determine whether these features are supported. � Low-level behavioral differences. A few low-level VIA C3 Nehemiah processor functions are dif- ferent from Intel Celeron because the results are (1) documented in the documentation as undefined, and (2) known to be different for different x86 implementations. That is, compatibility with the In- tel Celeron processor for these functions is clearly not needed for software compatibility (or they would not be different across different implementations). This chapter summarizes the first three types of differences: additional functions, implementation-specific functions, and omitted functions. Appendix A contains more details on machine-specific functions. 2-2 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 2.2 ADDITIONAL FUNCTIONS Virtual 8086 Mode Enhancements: VME VME has been added to VIA C3 Nehemiah stepping ID 8 and above. The function is omitted in VIA C3 Nehemiah stepping ID 7 and below. The CPUID feature flag bit 1 will indicate if Virtual Mode En- hancements are present. SYSENTER and SYSEXIT: SEP This function has been added to VIA C3 Nehemiah stepping ID 8 and above. The function is omitted in VIA C3 Nehemiah stepping ID 7 and below. The CPUID feature flag bit 11 will indicate if SYSENTER/SYSEXIT instructions are present. Page Attribute Table: PAT PAT function has been added to VIA C3 Nehemiah stepping ID 8 and above. The function is omitted in VIA C3 Nehemiah stepping ID 7 and below. The CPUID feature flag bit 16 will indicate if a Page At- tribute Table is present. Padlock The VIA Eden-N processor includes a suite of security technologies called Padlock. One Padlock feature is called the Advanced Cryptography Engine (ACE) and provides a high performance implementation of the Advanced Encryption Standard (AES), as specified by the US Government. VIA Eden-N processors also extend Padlock by including two separate Random Number Generators. Advanced Cryptography Engine: ACE Padlock's Advanced Cryptography Engine provides the world’s fastest AES encryption implementation. Wherever AES software encryption implementations are used today, it can be optimized for ACE with minimal effort. World class AES performance is a user-level instruction away as only one opcode handles encrypt and decrypt functions. See the Padlock ACE programming guide for further details. Random Number Generator: RNG VIA Eden-N processors incorporate two random number generators on the processors die for a fast source of entropy. See the Padlock RNG programming guide for further details. Section 2 Programming Interface 2-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 2.3 ACHINE-SPECIFIC FUNCTIONS 2.3.1 GENERAL All x86 processor implementations provide a variety of machine-specific functions. Examples are cache and TLB testing features and performance monitoring features that expose the internal implementation features. This section describes the VIA C3 Nehemiah processor machine-specific functions that are most likely used by software, and compares them to related processors where applicable. Appendix A documents the VIA C3 Nehemiah processor machine-specific registers (MSRs). This section covers those features of Intel Pentium-compatible processors that are used to commonly identify and control processor features. All Pentium-compatible processors have the same mechanisms, but the bit-specific data values often differ. 2.3.2 STANDARD CPUID INSTRUCTION FUNCTIONS The CPUID instruction is available on all contemporary x86 processors. The CPUID instruction has two standard functions requested via the EAX register. The first function returns a vendor identification string in registers EBX, ECX, and EDX. The second CPUID function returns an assortment of bits in EAX and EDX that identify the chip version and describe the specific features available. The EAX:EBX:ECX:EDX return values of the CPUID instruction executed with EAX == 0 are: Table 3-1. CPUID Return Values (EAX = 0) REGISTER[BITS] – MEANING VIA C3 NEHEMIAH EAX (highest EAX input 1 value understood by CPUID) EBX:EDX:ECX “Centaur (vendor ID string) Hauls” The EAX return values of the CPUID instruction executed with EAX == 1 are: Table 3-2. CPUID EAX Return Values (EAX = 1) EAX BITS – MEANING VIA C3 NEHEMIAH 3:0 - Stepping ID Same as the return value in EDX after Reset 7:4 - Model ID (see next section) 11:8 - Family ID 13:12 – Type ID 2-4 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet The EDX return values of the CPUID instruction with EAX == 1 are: Table 3-3 CPUID EDX Return Values (EAX = 1) VIA C3 VIA C3 EDX BITS – MEANING NEHEMIAH NEHEMIAH NOTES (Stepping 0-7) (Stepping 8-15) 0 – FPU present 1 1 1 - Virtual Mode Extension 0 1 2 - Debugging Extensions 1 1 3 - Page Size Extensions (4MB) 1 1 4 – Time Stamp Counter (TSC) supported 1 1 5 - Model Specific Registers present 1 1 6 - Physical Address Extension 0 0 7 - Machine Check Exception 0 0 8 - CMPXCHG8B instruction 1 1 1 9 – APIC supported 0 1 2 10- Reserved 11- Fast System Call 0 1 12- Memory Range Registers 1 1 13 - PTE Global Bit supported 1/0 1/0 3 14- Machine Check Architecture supported 0 0 15- Conditional Move supported 1 1 16- Page Attribute Table 0 1 17- 36-bit Page Size Extension 0 0 18- Processor serial number 0 0 19:22 - Reserved 23- MMX supported 1 1 24- FXSR 1 1 25- Streaming SIMD Extension supported 1 1 26:31 - Reserved Notes On CPUID Feature Flags: General: an “x/y” entry means that the default setting of this bit is x but the bit (and the underlying func- tion) can be set to y using the FCR MSR. 1. The CMPXCHG8B instruction is provided and always enabled, however, it can be disabled in the correspond- ing CPUID function bit 8 to avoid a bug in an early version of Windows NT. However, this default can be changed via bit 1 in the FCR MSR. 2. APIC will be available in future steppings. 3. The VIA C3 Nehemiah processor’s support for Page Global Enable can be enabled or disabled by a bit in the FCR. The CPUID bit reports the current setting of this enable control. Section 2 Programming Interface 2-5 VIA C3 Nehemiah Processor Datasheet September 29, 2004 2.3.3 EXTENDED CPUID INSTRUCTION FUNCTIONS The VIA C3 Nehemiah processor supports extended CPUID functions that provide additional information about the VIA C3 Nehemiah processor. Extended CPUID functions are requested by executing CPUID with EAX set to any value in the range 0x80000000 through 0x80000006. The following table summarizes the extended CPUID functions. Table 3-4. Extended CPUID Functions EAX TITLE OUTPUT 80000000 Largest Extended Function EAX=80000006 Input Value EBX,ECX,EDX=Reserved 80000001 Processor Signature and Fea- EAX=Processor Signature ture Flags EBX,ECX=Reserved EDX=Extended Feature Flags 80000002 Processor Name String EAX,EBX,ECX,EDX 80000003 Processor Name String EAX,EBX,ECX,EDX 80000004 Processor Name String EAX,EBX,ECX,EDX 80000005 TLB and L1 Cache Information EAX = Reserved EBX = TLB Information ECX = L1 Data Cache Information EDX = L1 Instruction Cache Information 80000006 L2 Cache Information EAX, EBX, EDX = Reserved ECX = L2 Cache Information Largest Extended Function Input Value (EAX==0x80000000) Returns 0x80000006 in EAX, the largest extended function input value. Processor Signature and Feature Flags (EAX==0x80000001) Returns processor version information in EAX. Processor Name String (EAX==0x80000002–0x80000004) Returns the name of the processor, suitable for BIOS to display on the screen (ASCII). The string can be up to 48 characters in length. If the string is shorter, the rightmost characters are padded with zero. The leftmost characters go in EAX, then EBX, ECX, and EDX. The leftmost character goes in least signifi- cant byte (little endian). 2-6 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet For example, the string “VIA C3 Nehemiah” would be returned by extended function EAX=0x80000002 as follows: EAX = 0x20414956 EBX = 0x6568654E ECX = 0x6861696D EDX = 0x00000000 Since the string is less than 17 bytes, the extended functions EAX=0x80000003 and EAX=0x80000004 return zero in EAX, EBX, ECX, and EDX. L1 Cache Information (EAX == 0x80000005) Returns information about the implementation of the TLBs and caches: Table 3-5. L1 Cache & TLB Configuration Encoding REGISTER DESCRIPTION VALUE EAX Reserved EBX TLB Information EBX[31:24] D-TLB associativity 8 EBX[23:16] D-TLB # entries 128 EBX[15: 8] I-TLB associativity 8 EBX[ 7: 0] I-TLB # entries 128 ECX L1 Data Cache Information ECX[31:24] Size (Kbytes) 64 ECX[23:16] Associativity 4/2 ECX[15: 8] Lines per Tag 1 ECX[ 7: 0] Line Size (bytes) 32 EDX L1 Instruction Cache Information EDX[31:24] Size (Kbytes) 64 EDX[23:16] Associativity 4/2 EDX[15: 8] Lines per Tag 1 EDX[ 7: 0] Line Size (bytes) 32 Notes On CPUID L1 Cache Associativity: Steppings 0 through 7 have a 4-way L1 Data and Instruction caches. Steppings 8 and higher have 2-way L1 Data and Instruction caches. Stepping 8 has an erratum that will inadvertently report 4-way L1 caches instead of the proper 2-way L1 caches. The erratum is fixed in future steppings. Section 2 Programming Interface 2-7 VIA C3 Nehemiah Processor Datasheet September 29, 2004 L2 Cache Information (EAX == 0x80000006) Returns information about the implementation of the L2 cache: Table 3-6. L2 Cache Configuration Encoding REGISTER DESCRIPTION VALUE EAX, EBX, EDX Reserved ECX L2 Data Cache Information ECX[31:16] Size (Kbytes) 64 ECX[15:12] Associativity 16 ECX[11: 8] Lines per Tag 1 ECX[ 7: 0] Line Size (bytes) 32 2-8 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 2.3.4 CENTAUR EXTENDED CPUID INSTRUCTION FUNCTIONS The VIA C3 Nehemiah processor supports special CPUID functions that provide additional information about the VIA C3 Nehemiah processor. Centaur CPUID functions are requested by executing CPUID with EAX set to 0xC0000000 or 0xC0000001. EAX INPUT TITLE OUTPUT Largest Centaur Extended Func- 0xC0000000 EAX=0xC0000001 tion Input Value EDX=Centaur Extended Feature Flags 0xC0000001 Centaur Extended Feature Flags EAX,EBX,ECX=Reserved EDX BIT VALUE EDX[0]=0 Alternate Instruction Set (AIS) not supported 0 EDX[0]=1 Alternate Instruction Set (AIS) supported EDX[1]=0 AIS Disabled 1 EDX[1]=1 AIS Enabled EDX[2]=0 Random Number Generator (RNG) Present 2 EDX[2]=1 Random Number Generator (RNG) Not Present EDX[3]=0 RNG Disabled 3 EDX[3]=1 RNG Enabled EDX[4]=0 Longhaul MSR 0x110A not available 4 EDX[4]=1 Longhaul MSR 0x110A available EDX[5]=0 FEMMS instruction (opcode 0x0F0E) Not Present 5 EDX[5]=1 FEMMS instruction (opcode 0x0F0E) Present EDX[6]=0 Advanced Cryptography Engine (ACE) Present 6 EDX[6]=1 Advanced Cryptography Engine (ACE) Not Present EDX[6]=0 ACE Disabled 7 EDX[6]=1 ACE Enabled 31:8 Reserved Section 2 Programming Interface 2-9 VIA C3 Nehemiah Processor Datasheet September 29, 2004 2.3.5 PROCESSOR IDENTIFICATION The VIA C3 Nehemiah processor provides several machine-specific features. These features are identified by the standard CPUID function EAX=1. Other machine-specific features are controlled by VIA C3 Ne- hemiah MSRs. Some of these features are not backward compatible with the predecessors in the VIA C3 family. System software must not assume that all future processors in the VIA processor family will implement all of the same machine-specific features, or even that these features will be implemented in a backward- compatible manner. In order to determine if the processor supports particular machine-specific features, system software should follow the following procedure. Identify the processor as a member of the VIA processor family by checking for a Vendor Identification String of “CentaurHauls” using CPUID with EAX=0. Once this has been verified, system software must determine the processor version in order to properly configure the machine-specific registers. In general, system software can determine the processor version by comparing the Family and Model Identification fields returned by the CPUID standard function EAX=1. If the processor version is not recognized then system software must not attempt to activate any machine- specific feature. 2.3.6 EDX VALUE AFTER RESET After reset the EDX register holds a component identification number as follows: 31:14 13:12 11:8 7:4 3:0 EDX Reserved Type ID Family ID Model ID Stepping ID 18 2 4 4 4 The specific values for the VIA C3 Nehemiah processor are listed in the chart. There are two stepping ID available for the Via C3 Nehemiah processor with different features available based on the stepping. The first stepping ID is 7 and below, while the second stepping ID is 8 and above. Differences in features are noted in the data sheet. PROCESSOR TYPE ID FAMILY ID MODEL ID STEPPING ID VIA C3 Nehemiah 0 6 9 Begins at 0 2-10 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 2.3.7 CONTROL REGISTER 4 (CR4) Control register 4 (CR4) controls some of the advanced features of the Celeron processor. The VIA C3 Nehemiah processor provides a CR4 with the following specifics: Table 3-7. CR4 Bits VIA C3 CELERON CELERON CR4 BITS - MEANING NOTES NEHEMIAH MODEL 6 MODEL 8 0: VME: Enables VME feature 0/1 0/1 0/1 1 1: PVI: Enables PVI feature 0/1 0/1 0/1 1 2: TSD: Makes RDTSC inst privileged 0/1 0/1 0/1 3: DE: Enables I/O breakpoints 0/1 0/1 0/1 4: PSE: Enables 4-MB pages 0/1 0/1 0/1 5: PAE: Enables address extensions r r r 6: MCE: Enables machine check exception 0/1 0/1 0/1 2 7: PGE: Enables global page feature 0/1 0/1 0/1 8: PCE: Enables RDPMC for all levels 0/1 0/1 0/1 9: OSFXSR: Enables FXSAVE//FXRSTOR Support 0/1 r 0/1 10: OSXMMEXCPT: O/S Unmasked Exception Support 0/1 r 0/1 31:11 – reserved r r r Notes On CR4 General: a “0/1” means that the default setting of this bit is 0 but the bit can be set to (1). A “0” means that the bit is always 0; it cannot be set. An “r” means that this bit is reserved. It appears as a 0 when read, and a GP exception is signaled if an attempt is made to write a 1 to this bit. 1. The VIA C3 Nehemiah processor stepping 7 and below do not provide this “Appendix H” function and this CR4 bit cannot be set. However, no GP exception occurs if an attempt is made to set this bit. The VIA C3 Ne- hemiah processor steppings 8 and above do provide function and the CR4 bit can be set. 2. The VIA C3 Nehemiah processor Machine Check has different specifics than the Machine Check function of compatible processors. 2.3.8 MACHINE-SPECIFIC REGISTERS The VIA C3 Nehemiah processor implements the concept of Machine Specific Registers (MSRs). RDMSR and WRMSR instructions are provided and the CPUID instruction identifies that the VIA C3 Nehemiah processor supports MSRs. In general, the MSRs have no usefulness to application or operating system software and are not used. (This is to be expected since the MSRs are different on each processor.) Appendix A contains a detailed description of the VIA C3 Nehemiah processor’s MSRs. Section 2 Programming Interface 2-11 VIA C3 Nehemiah Processor Datasheet September 29, 2004 2.4 OMITTED FUNCTIONS This section summarizes those functions that are not in the VIA C3 Nehemiah processor. A bit in the CPUID feature flags indicates whether these feature are present or not. Physical Address Extensions: PAE This function is omitted since the target market for the VIA C3 Nehemiah processor is portables and typi- cal desktop systems. These systems do not use 2 MB paging and have greater than 4 GB of system memory. Page Size Extensions: PSE-36 This function is omitted since the target operating systems for the VIA C3 Nehemiah do not require greater than 4 GB of system memory. Other Functions Model specific registers pertaining to Machine Check, and Debug, Performance Monitoring, and Trace features are not supported. 2-12 Programming Interface Section 2 September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION HARDWARE INTERFACE 3.1 BUS INTERFACE The VIA C3 Nehemiah processor bus interface is commonly referred to as the Socket 370 interface. The majority of the pins within the bus interface are involved with the physical memory and I/O interface. The remaining pins are power and ground pins, test and debug support pins, and various ancillary control functions. The pins and associated functions are listed and described in this section. Section 3 Hardware Interface 3-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 3.1.1 DIFFERENCES The areas where the VIA C3 Nehemiah processor differs from compatible processors should not cause operational compatibility issues. These differences are: � Bus-to-core Ratio Control � Bus Frequency Control � Probe Mode / JTAG / TAP Port (see Test and Debug Section) Bus-to-Core Frequency Ratio Control The VIA C3 Nehemiah processor supports both fused and software control of the bus-to-core frequency ratio. At reset, the factory-set, fused ratio is used. This ratio can then be adjusted via software. This ad- justment lasts until the next reset. Software can adjust the bus-to-core ratio using the VIA C3 Nehemiah processor’s LongHaul extensions. These are documented separately in the VIA C3 LongHaul Specification. Bus Frequency Selection The VIA C3 Nehemiah processor supports automated bus frequency selection through the BSEL pins. The BSEL pins are used as a mechanism whereby the processor and the system board can negotiate to support high frequency bus frequencies. The standard BSEL decoding is shown in Table 3-1. While the VIA C3 Nehemiah processor is designed to operate at bus frequencies of 66, 100, or 133 MHz, performance is improved by running at higher bus frequencies. Various speed bins preclude 133 MHz op- eration because the available bus-to-core ratios do not permit operation at the desired core MHz. Processors from these speed bins indicate this by shorting the BSEL[1] pin to ground internal to the pack- age. For these processors the BSEL[0] pin is left floating. Processors from speed bins which permit 133 MHz bus operation indicate this by allowing both BSEL[1] and BSEL[0] to float. It is anticipated that motherboards will pull up both BSEL pins. The resulting BSEL-indicated bus fre- quency will then be either 100 MHz or 133 MHz according to speed bin. Bus operation at 66MHz is not desirable. Table 3-1. BSEL Frequency Mapping BSEL[1] BSEL[0] BUS FREQUENCY 0 0 66 MHz 0 1 100 MHz 1 0 Reserved 1 1 133 MHz 3-2 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 3.1.2 CLARIFICATIONS Power Supply Voltage The VIA C3 Nehemiah processor automatically controls its core processor power supply voltage with the VID pins. The VID mapping for CPGA-packaged VIA C3 Nehemiah processors is in Table 3-2. This mapping cor- responds to the VRM8.5 specification. Section 3 Hardware Interface 3-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Table 3-2. Core Voltage Settings VID4 VID3 VID2 VID1 VID0 VCORE 0 0 1 0 0 1.050V 1 0 1 0 0 1.075V 0 0 0 1 1 1.100V 1 0 0 1 1 1.125 0 0 0 1 0 1.150V 1 0 0 1 0 1.175V 0 0 0 0 1 1.200V 1 0 0 0 1 1.225V 0 0 0 0 0 1.250V 1 0 0 0 0 1.275V 0 1 1 1 1 1.300V 1 1 1 1 1 1.325V 0 1 1 1 0 1.350V 1 1 1 1 0 1.375V 0 1 1 0 1 1.400V 1 1 1 0 1 1.425V 0 1 1 0 0 1.450V 1 1 1 0 0 1.475V 0 1 0 1 1 1.500V 1 1 0 1 1 1.525V 0 1 0 1 0 1.550V 1 1 0 1 0 1.575V 0 1 0 0 1 1.600V 1 1 0 0 1 1.625V 0 1 0 0 0 1.650V 1 1 0 0 0 1.675V 0 0 1 1 1 1.700V 1 0 1 1 1 1.725V 0 0 1 1 0 1.750V 1 0 1 1 0 1.775V 0 0 1 0 1 1.800V 1 0 1 0 1 1.825V NOTE: VID4 may be referred as VID25mV. 3-4 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet VCCCMOS The VIA C3 Nehemiah processor routes the VCC1.5 pin to the VCCCMOS pin via the package. This signal is not used by the processor, but is intended for the system as the power supply for CMOS level signals. VCCCMOS should not be expected to source more than 250mA. RESET# The VIA C3 Nehemiah processor is reset by the assertion of the RESET# pin. Current versions of the VIA C3 Nehemiah processor connect this pin to AH-4 in the Socket370 pinout. Board designers should always connect RESET# to both AH-4 and X-4 to ensure compatibility with all VIA processors. Thermal Monitoring The VIA C3 Nehemiah processor supports thermal monitoring via the THERMDN and THERMDP pins. However, it does not support the THERMTRIP# pin. The THERMTRIP# pin should be treated as re- served. Advanced Peripheral Interrupt Controller (APIC) The APIC is currently not supported by the VIA C3 Nehemiah processor. Future steppings of the VIA C3 Nehemiah will support the APIC. The APIC pins (PICCLK, PICD0, and PICD1) are specified as re- served, but should be connected on the motherboard for compatibility with future processors. Section 3 Hardware Interface 3-5 VIA C3 Nehemiah Processor Datasheet September 29, 2004 3.1.3 OMISSIONS VTT_PWRGD The VTT_PWRGD signal is not used. Care should be taken to prevent the VCC plane from powering up before the VTT plane. Breakpoint and Performance Monitoring Signals The VIA C3 Nehemiah processor internally supports instruction and data breakpoints. However, the VIA C3 Nehemiah processor does not support the external indication of breakpoint matches via the BP3-BP0 pins. Similarly, the VIA C3 Nehemiah processor contains performance monitoring hooks internally, but it does not support the indication of performance monitoring events on PM1-PM0. The associated pins are unconnected on the VIA C3 Nehemiah processor package. Error Checking The VIA C3 Nehemiah processor does not support error checking. The BERR#, BINIT#, AERR#, AP#[1:0], DEP#[7:0], IERR#, RP#, and RSP# pins do not exist and should be treated as reserved. V COREDET The VIA C3 Nehemiah processor does not connect to the VCOREDET pin. SLEWCTRL The VIA C3 Nehemiah processor does not connect to the SLEWCTRL pin. Future VIA processors may connect to the SLEWCTRL pin. 3-6 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 3.2 PIN DESCRIPTION Table 3-3. Pin Descriptions Pin Name Description I/O Clock A[31:3]# The address Bus provides addresses for physical memory and external I/O devices. I/O BCLK During cache inquiry cycles, A31#-A3# are used as inputs to perform snoop cycles. A20M# A20 Mask causes the CPU to make (force to 0) the A20 address bit when driving the I(1.5V) ASYNC external address bus or performing an internal cache access. A20M# is provided to emulate the 1 MByte address wrap-around that occurs on the 8086. Snoop addressing is not affected. ADS# Address Strobe begins a memory/I/O cycle and indicates the address bus (A31#-A3#) I/O BCLK and transaction request signals (REQ#) are valid. BCLK Bus Clock provides the fundamental timing for the VIA C3 Nehemiah CPU. The fre- I(2.5V) -- quency of the VIA C3 Nehemiah CPU input clock determines the operating frequency of the CPU’s bus. External timing is defined referenced to the rising edge of CLK. BNR# Block Next Request signals a bus stall by a bus agent unable to accept new transac- I/O BCLK tions. BPRI# Priority Agent Bus Request arbitrates for ownership of the system bus. I BCLK BSEL[1:0] Bus Selection Bus provides system bus frequency data to the CPU. O BCLK BR[1:0]# BR0# drives the BREQ[0]# signal in the system to request access to the system bus. I/O None BR1# drives the BREQ[1]# signal in the system to request access to the system bus. CPUPRES# CPU Present is grounded inside the processor to indicate to the system that a proces- O None sor is present. D[63:0]# Data Bus signals are bi-directional signals which provide the data path between the VIA I/O BCLK C3 Nehemiah CPU and external memory and I/O devices. The data bus must assert DRDY# to indicate valid data transfer. DBSY# Data Bus Busy is asserted by the data bus driver to indicate data bus is in use. I/O BCLK DEFER# Defer is asserted by target agent (e.g., north bridge) and indicates the transaction can- I BCLK not be guaranteed as an in-order completion. DRDY# Data Ready is asserted by data driver to indicate that a valid signal is on the data bus. I/O BCLK FERR# FPU Error Status indicates an unmasked floating-point error has occurred. FERR# is O(1.5V) ASYNC asserted during execution of the FPU instruction that caused the error. FLUSH# Flush Internal Caches writing back all data in the modified state. I(1.5V) ASYNC HIT# Snoop Hit indicates that the current cache inquiry address has been found in the cache I/O BCLK (exclusive or shared states). HITM# Snoop Hit Modified indicates that the current cache inquiry address has been found in I/O BCLK the cache and dirty data exists in the cache line (modified state). IGNNE# Ignore Numeric Error forces the VIA C3 Nehemiah CPU to ignore any pending un- I(1.5V) ASYNC masked FPU errors and allows continued execution of floating point instructions. INIT# Initialization resets integer registers and does not affect internal cache or floating point I(1.5V) ASYNC registers. INTR / LINT0 Maskable Interrupt / Signal become LINT0 when APIC is enabled I(1.5V) ASYNC NCHCTRL I ASYNC Control integrated I/O pull-ups. Connect this signal to VTT with a 14Ω resistor. NMI / LINT1 Non-Maskable Interrupt / Signal become LINT1 when APIC is enabled I(1.5V) ASYNC LOCK# Lock Status is used by the CPU to signal to the target that the operation is atomic. I/O BCLK PICCLK APIC clock for operation with the system I/O APIC I APIC Section 3 Hardware Interface 3-7 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Pin Name Description I/O Clock PICD[1:0] Bi-directional serial pins for communicating APIC messages to the system I/0 APIC PWRGD Indicates that the processor’s VCC is stable. I (1.5V) ASYNC REQ[4:0]# Request Command is asserted by bus driver to define current transaction type. I/O BCLK RESET# Resets the processor and invalidates internal cache without writing back. I BCLK RS[2:0]# Response Status signals the completion status of the current transaction when the I BCLK CPU is the response agent. RTTCTRL Control the output impedance on the on-die termination resistance. Connect this signal I ASYNC to VSS with a 56Ω resistor if relying upon on-die termination. Connect this signal to VSS with a 110Ω resistor if relying upon board termination. SLP# Sleep, when asserted in the stop grant state, causes the CPU to enter the sleep state. I(1.5V) ASYNC SMI# System Management (SMM) Interrupt forces the processor to save the CPU state to I(1.5V) ASYNC the top of SMM memory and to begin execution of the SMI services routine at the be- ginning of the defined SMM memory space. An SMI is a high-priority interrupt than NMI. STPCLK# Stop Clock causes the CPU to enter the stop grant state. I(1.5V) ASYNC TRDY# Target Ready indicates that the target is ready to receive a write or write-back transfer I BCLK from the CPU. VID[4:0] Voltage Identification Bus informs the regulatory system on the motherboard of the O(1.5V) ASYNC CPU Core voltage requirements. Table 3-4. BGA only Pin Descriptions Pin Name Description I/O Clock BR[4:0] Hardware strapping options for setting the processors internal clock multiplier. VIA C3 I Nehemiah processors do not have their clock multiplier set to a factory default value. Use jumpers or populate 0Ω resistors to select the rated multiplier. The BR[4:0] balls should be wired to VSS for a value of “0” or wired to OPEN for setting of “1.” See Table 3-5 for ratio values. 3-8 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Table 3-5. Clock Ratio BR[4] BR[3] BR[2] BR[1] BR[0] Bus Ratio 0 0 0 0 0 9.0X 0 0 0 0 1 3.0X 0 0 0 1 0 4.0X 0 0 0 1 1 10.0X 0 0 1 0 0 5.5X 0 0 1 0 1 3.5X 0 0 1 1 0 4.5X 0 0 1 1 1 9.5X 0 1 0 0 0 5.0X 0 1 0 0 1 7.0X 0 1 0 1 0 8.0X 0 1 0 1 1 6.0X 0 1 1 0 0 12.0X 0 1 1 0 1 7.5X 0 1 1 1 0 8.5X 0 1 1 1 1 6.5X 1 0 0 0 0 Reserved 1 0 0 0 1 11.0X 1 0 0 1 0 12.0X 1 0 0 1 1 Reserved 1 0 1 0 0 13.5X 1 0 1 0 1 11.5X 1 0 1 1 0 12.5X 1 0 1 1 1 10.5X 1 1 0 0 0 13.0X 1 1 0 0 1 15.0X 1 1 0 1 0 16.0X 1 1 0 1 1 14.0X 1 1 1 0 0 Reserved 1 1 1 0 1 15.5X 1 1 1 1 0 Reserved 1 1 1 1 1 14.5X Section 3 Hardware Interface 3-9 VIA C3 Nehemiah Processor Datasheet September 29, 2004 3.3 POWER MANAGEMENT The VIA C3 Nehemiah processor provides both static and dynamic power management. The VIA C3 Nehemiah processor supports five power management states: NORMAL, QUICKSTART, SLEEP, DEEP SLEEP and DEEPER SLEEP. The VIA C3 Nehemiah processor uses dynamic power management techniques to reduce power con- sumption in the NORMAL state. In NORMAL state, the on-chip arrays, selected datapaths and the associated control logic are powered down when not in use. Also, units that are in use attempt to mini- mize switching of inactive nodes. � NORMAL state is the normal operating state for the processor. � QUICKSTART state is the low power state where most of the processor clocks do not toggle. It is entered when the STPCLK# signal is asserted or when the processor executes the HALT instruc- tion. Snoop cycles are supported in this state. � SLEEP state is the low power state where only the processor's PLL (phase lock loop) toggles. It is entered from QUICKSTART state when the processor samples the SLP# signal asserted. Snoop cycles that occur while in SLEEP state or during a transition into or out of SLEEP state will cause unpredictable behavior. � DEEP SLEEP state is a very low power state. It is entered when the BCLK signal is stopped while the processor is in the SLEEP state. Snoop cycles are completely ignored in this state. � DEEPER SLEEP state is the lowest power state. It is entered when the processor core voltage is lowered while the processor is in the DEEP SLEEP state. Snoop cycles are completely ignored in this state. 3-10 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet BCLK stopped STPCLK# or BCLK on HLT instruction and !SLP# Normal Quick Start halt break or !STPCLK# SLP# BCLK stopped snoop snoop !SLP# serviced occurs Sleep Deep Sleep BCLK on and SLP# Core Voltage Snoop Lowered Core Voltage Raised Deeper Sleep Figure 3-1. Power Management State Diagram Section 3 Hardware Interface 3-11 VIA C3 Nehemiah Processor Datasheet September 29, 2004 3.4 TEST & DEBUG 3.4.1 BIST A Built-in Self-Test (BIST) can be requested as part of the VIA C3 Nehemiah processor reset sequence by holding INIT# asserted as RESET# is de-asserted. The VIA C3 Nehemiah processor BIST performs the following general functions: � A hardware-implemented exhaustive test of (1) all internal microcode ROM, and (2) the X86 in- struction decode, instruction generation, and entry point generation logic. � An extensive microcode test of all internal registers and datapaths. � An extensive microcode test of data and instruction caches, their tags, and associated TLBs. BIST requires about four million internal clocks. EAX Value After Reset The result of a BIST is indicated by a code in EAX. Normally EAX is zero after reset. If a BIST is re- quested as part of the Reset sequence, EAX contains the BIST results. A 0 in EAX after BIST Reset means that no failures were detected. Any value other than zero indicates an error has occurred during BIST. 3.4.2 JTAG The VIA C3 Nehemiah processor has a JTAG scan interface that is used for test functions and the pro- prietary Debug Port. However, the VIA C3 Nehemiah processor does not provide a fully compatible IEEE 1149.1 JTAG function. From a practical user viewpoint, JTAG does not exist and the associated pins (TCLK, and so forth) should not be used. 3.4.3 DEBUG PORT Certain processors have a proprietary Debug Port that uses the JTAG scan mechanism to control internal debug features (“probe mode”). These interfaces are not documented and are available (if at all) only un- der a non-disclosure agreement. The VIA C3 Nehemiah processor does not have a debug interface. 3-12 Hardware Interface Section 3 September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION ELECTRICAL SPECIFICATIONS 4.1 AC TIMING TABLES 1 Table 4-1: System Bus Clock AC Specifications (133 MHz) SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES System Bus Frequency 133 MHz T BCLK Period 7.5 7.65 ns Figure 4-1 (2) 1S T BCLK Period – Instantaneous Minimum 7.25 (2) 1Sabs T BCLK Period Stability +250 ps (2),(3),(4) 2S T BCLK High Time 1.4 ns Figure 4-1 at>2.0V 3S T BCLK Low Time 1.4 ns Figure 4-1 at<0.5V 4S T BCLK Rise Time 0.4 1.6 ns Figure 4-1 (5) 5S T BCLK Fall Time 0.4 1.6 ns Figure 4-1 (5) 6S Notes: 1. All AC timings for bus and CMOS signals are referenced to the BCLK rising edge at 1.25V. 2. Period, jitter, skew and offset measured at 1.25V. 3. Not 100% tested. Specified by design/characterization. 4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a compo- nent of BCLK skew between devices. 5. Measured between 0.5V and 2.0V. Section 4 Electrical Specifications 4-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 1 Table 4-2. System Bus Clock AC Specifications (100 MHz) SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES System Bus Frequency 100 MHz T BCLK Period 10 ns Figure 4-1 (2) 1S1 T BCLK Period – Instantaneous Minimum 9.75 ns (2) 1S1abs T BCLK Period Stability ps Figure 4-1 (2),(3),(4) 2S1 T BCLK High Time 2.70 ns Figure 4-1 At >2.0V 3S1 T BCLK Fall Time 2.45 ns Figure 4-1 At <0.5V 4S1 T BCLK Rise Time 0.4 ns Figure 4-1 (5) 5S1 T BCLK Fall Time 0.4 ns Figure 4-1 (5) 6S1 Notes: 1. All AC timings for bus and CMOS signals are referenced to the BCLK rising edge at 1.25V. 2. Period, jitter, skew and offset measured at 1.25V. 3. Not 100% tested. Specified by design/characterization 4. Measured on the rising edge of adjacent BCLKs at 1.25V. The jitter present must be accounted for as a compo- nent of BCLK skew between devices. 5. Measured between 0.5V and 2.0V. 1,8 Table 4-3. Bus Signal Groups AC Specifications SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES T Bus Output Valid Delay 0.40 3.25 ns Figure 4-2 7 T Bus Input Setup Time 0.95 ns Figure 4-3, (2),(3),(6) 8 1.30 Figure 4-4 (7) T Bus Input Hold Time 1 ns Figure 4-3, (4) 9 Figure 4-4 T RESET# Pulse Width 1 ms Figure 4-4 (5) 10 Notes: 1. All AC timings for bus and CMOS signals are referenced to the BCLK rising edge at 1.25V. All bus signals are referenced at VREF. Unless specified, all timings apply to both 100 MHz and 133 MHz bus frequencies. 2. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously. 3. Specification is for a minimum 0.4V swing from VREF-200 mV to VREF+200 mV. 4. Specification is for a maximum 0.8V swing from VTT-0.8V to VTT. 5. After VCC, VTT and BCLK become stable and PWRGOOD is asserted. 6. Applies to processors supporting 133 MHz bus clock frequency. 7. Applies to processors supporting 100 MHz bus clock frequency. 8. Rtt=56Ω internally terminated to VTT; VREF=2/3 VTT; Load = 50Ω 4-2 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 1,2 Table 4-4. CMOS and Open-drain Signal GROUPS AC Specifications SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES T 1.5V Input Pulse Width, except 2 BCLKs Figure 4-2 Active and 14 PWRGOOD and LINT[1:0] inactive states T LINT[1:0] Input Pulse Width 6 BCLKs Figure 4-2 (3) 14B T PWRGOOD Inactive Pulse Width 2 µs Figure 4-5 (4) 15 Notes: 1. All AC timings for CMOS and Open-drain signals are referenced to the rising edge of BCLK at 1.25V. All CMOS and Open-drain signals are referenced at 1.0V. 2. Minimum output pulse width on CMOS outputs is 2 BCLKs. 3. This specification only applies when the APIC is enabled and the LINT[1:0] signals are configured as edge trig- gered interrupts with fixed delivery, otherwise specification T14 applies. 4. When driven inactive, or after VCC, VTT and BCLK become stable. PWRGOOD must remain below VIL18,MAX until all the voltage planes meet the voltage tolerance specifications in Table 4-8 through Table 4-10 and BCLK have met the BCLK AC specifications in Table 4-1 and Table 4-2 for a least 2 µs. PWRGOOD must rise error-free and monotonically. Table 4-5. Reset Configuration AC Specifications and Power On/Power Down Timings SYMBOL PARAMETER MIN TYP MAX UNIT FIGURE NOTES T Reset Configuration Signals (A[15:5]#, 4 BCLKs Figure 4-4 Before deasser- 16 BREQ0#, FLUSH#, INIT#, PICD0) Setup Time tion of RESET# T Reset Configuration Signals (A[15:5]#, 2 20 BCLKs Figure 4-4 After clock that 17 BREQ0#, FLUSH#, INIT#, PICD0) Hold Time deasserts RESET# T RESET#/PWRGOOD Setup Time 1 ms Figure 4-5 Before deasser- 18 1 tion of RESET# T VCC to PWRGOOD Setup Time 10 ms Figure 4-5 18B T RESET# inactive to Valid Outputs 1 BCLK Figure 4-4 18D T RESET# inactive to Drive Signals 4 BCLKs Figure 4-4 18E T Time from VCC(nominal)-12% to PWRGOOD 0 ns Figure 4-6 VCC(nominal) is 19A low the VID voltage setting T All outputs valid after PWRGOOD low 0 ns Figure 4-6 19B T All inputs required valid after PWRGOOD low 0 ns Figure 4-6 19C T All outputs valid after VTT-12% 0 ns Figure 4-7 20B T All inputs required valid after VTT-12% 0 ns Figure 4-7 20C T VID, BSEL signals valid after VTT-12% 0 ns Figure 4-7 20D Notes: 1. At least 1 ms must pass after PWRGOOD rises above VIH18min and BCLK meet their AC timing specification until RESET# may be deasserted. Section 4 Electrical Specifications 4-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 1 Table 4-6. APIC Bus Signal AC Specifications SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES T PICCLK Frequency 2 33.3 MHz (2) 21 T PICCLK Period 30 500 ns Figure 4-1 22 T PICCLK High Time 10.5 ns Figure 4-1 at>1.6V 23 T PICCLK Low Time 10.5 ns Figure 4-1 at<0.4V 24 T PICCLK Rise Time 0.25 3.0 ns Figure 4-1 (0.4V-1.6V) 25 T PICCLK Fall Time 0.25 3.0 ns Figure 4-1 (1.6V-0.4V) 26 T PICD[1:0] Setup Time 8.0 ns Figure 4-3 (3) 27 T PICD[1:0] Hold Time 2.5 ns Figure 4-3 (3) 28 T PICD[1:0] Valid Delay (Rising Edge) 1.5 8.7 ns Figure 4-2 (3),(4) 29 PICD[1:0] Valid Delay (Falling Edge) 1.5 12.0 ns Notes: 1. All AC timing for APIC signals referenced to the PICCLK rising edge at 1.0V. All CMOS signals are refer- enced at 1.0V. 2. The minimum frequency is 2MHz when PICD0 is at 1.5V at reset referenced to PICCLK Rising Edge. 3. For open-drain signals, Valid Delay is synonymous with Float Delay. 4. Valid delay timings for these signals are specified into 150Ω to 1.5V and 0pF of external load. For real system timings, these specifications must be derated for external capacitance at 105ps/pF. 1, 3, 4 Table 4-7. StopGrant / Sleep / Deep Sleep AC Specifications SYMBOL PARAMETER MIN MAX UNIT FIGURE NOTES T Stop Grant Cycle Completion to SLP# assertion or 100 BCLKs Figure 4-8, 45 BCLK Stopped Figure 4-9 T Stop Grant Cycle Completion to Input Signals Stable 0 µs Figure 4-8, 46 Figure 4-9 T Sleep PLL Lock Latency 0 30 µs Figure 4-8, (2) 47 Figure 4-9 T STPCLK# Hold Time from PLL Lock 0 µs Figure 4-8, 48 Figure 4-9 T Input Signal Hold Time from STPCLK# Deassertion 8 BCLKs Figure 4-8, 49 Figure 4-9 T BCLK Settling Time 150 ns 60 Notes: 1. Input Signals other than RESET# and BPRI# must be held constant in the Stop Grant state. 2. The BCLK Settling Time specification (T60) applies to all sleep state exits under all conditions. 3. In Figure 4-8 after SLP# is asserted, BCLK can be stopped and the processor will enter the Deep Sleep state. To exit the Deep Sleep state all timings shown in Figure 4-9 will need to be observed. 4. Vcore must be at nominal stable voltage before Deep Sleep exit after a Deeper Sleep transition. 4-4 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet T h T r V H V TRIP V CLK L T f T l T p NOTES: T =T5S, T5S1, T25 (Rise Time) r T =T6S, T6S1, T26 (Fall Time) f T =T3S, T3S1, T23 (High Time) h T =T4S, T4S1, T24 (Low Time) l T =T1S, T1S1, T22 (Period) p V =1.25v for BCLK; 1.0V for PICCLK TRIP V =0.5v for BCLK; 0.4V for PICCLK L V =2.0v for BCLK; 1.6V for PICCLK H Figure 4-1. BCLK Generic Clock Timing Waveform V V C C CLK T T X X V Valid Valid T PW NOTES: T =T7, T29 (Valid Delay) X T =T14, T14B (Pulse Width) PW V=V for bus signal group; 1.0v for CMOS, Open-drain, and APIC signal groups REF V = 1.25v C Figure 4-2. Valid Delay Timings Section 4 Electrical Specifications 4-5 VIA C3 Nehemiah Processor Datasheet September 29, 2004 V C CLK T T S h V Valid Signal NOTES: T =T8,T27 (Setup Time) S T =T9, T28 (Hold Time) h V=V for bus signals; 1.0v for CMOS and APIC signals REF V = 1.25v C Figure 4-3. Setup and Hold Timings V C BCLK T u T t RESET# V T v T T x w Configuration (A[15:5], BREQ0#, Valid FLUSH#, INIT# T y Bus outputs Valid T z Non-configuration Active inputs NOTES: T =T9 (Bus Input Hold Time) t T =T8 (Bus Input Setup Time) u T =T10 (RESET# Pulse Width) v T =T16 (Reset Configuration Signals (A[15:5#, BREQ0#, FLUSH#, INIT#) Setup Time) w T =T17 (Reset Configuration Signals (A[15:5#, BREQ0#, FLUSH#, INIT#) Hold Time) x T =T18D (RESET# inactive to Valid Outputs) y T =T18E (RESET# inactive to Drive Signals) z V =1.25v C Figure 4-4. Cold/Warm Reset and Configuration Timings 4-6 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet BCLK VTT VID[4:0]/ Valid BSEL[1:0] VREF VCC T a T c V IH15,min PWRGOOD V IL15,max T b RESET# NOTES: T =T15 (PWRGOOD Inactive Pulse Width) a T =T18 (RESET#/PWRGOOD Setup Time) b T =T18B (Setup time from VCC valid until PWRGOOD assertion) c Figure 4-5. Power-on Sequence and Reset Timings Section 4 Electrical Specifications 4-7 VIA C3 Nehemiah Processor Datasheet September 29, 2004 VTT, VREF VID[4:0] BSEL[1:0] V -12% CC VCC BCLK Valid T a PWRGOOD V IL15 RESET# Bus Outputs Valid Other CMOS Outputs T b All Inputs Valid T c NOTES: T =T19A (Time from VCC(nominal)-12% to PWRGOOD low) a T =T19B (All outputs valid after PWRGOOD low) b T =T19C (All inputs required valid after PWRGOOD low) c Figure 4-6. Power Down Sequencing and Timings (VCC Leading) 4-8 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet VCC-12% VTT, VREF VID[4:0] Valid BSEL[1:0] VCC T T T a, b, c BCLK Valid PWRGOOD RESET# Bus Outputs Valid Other CMOS Outputs Valid All Inputs NOTES: T =T20B (All outputs valid after VTT - 12%) a T =T20C (All inputs required valid after VTT - 12%) b T =T20D (VID, BSEL signals valid after VTT - 12%) c Figure 4-7. Power Down Sequencing and Timings (VTT Leading) Section 4 Electrical Specifications 4-9 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Normal Stop Grant Sleep Stop Grant Normal BCLK T v STPCLK# T T x y CPU bus stpgnt SLP# T T w z Compatibility Changing Frozen Signals NOTES: T =T45 (Stop Grant Acknowledge Bus Cycle Completion to SLP# assertion) v T =T46 (Setup Time to Input Signal Hold Requirement) w T =T47 (Sleep PLL Lock Latency) x T =T48 (PLL lock to STPCLK# Hold Time) y T =T49 (Input Signal Hold Time) z Figure 4-8. Stop Grant/Sleep Timing (SLP# assertion method) 4-10 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Normal Quick Start Deep Sleep Quick Start Normal Stopped BCLK T v STPCLK# T T x y CPU bus stpgnt SLP# T T w z Compatibility Changing Frozen Signals NOTES: T =T45 (Stop Grant Acknowledge Bus Cycle Completion to Clock Shut Off Delay) v T =T46 (Setup Time to Input Signal Hold Requirement) w T =T47 (Sleep PLL Lock Latency) x T =T48 (PLL lock to STPCLK# Hold Time) y T =T49 (Input Signal Hold Time) z Figure 4-9. Stop Grant/Deep Sleep Timing (BCLK Stopping method) Section 4 Electrical Specifications 4-11 VIA C3 Nehemiah Processor Datasheet September 29, 2004 4.2 DC SPECIFICATIONS 4.2.1 RECOMMENDED OPERATING CONDITIONS Functional operation of the VIA C3 Nehemiah processor is guaranteed if the conditions in Table 4-8 are met. Sustained operation outside of the recommended operating conditions may damage the device. Table 4-8. Recommended Operating Conditions PARAMETER MIN NOM MAX UNITS NOTES Operating Case Temperature 0 70 CPGA °C Operating Case Temperature 0 85 °C EBGA V Voltage 1.40 V EBGA CORE V Voltage 1.45 V CPGA CORE V Static Tolerance V (1) CORE See Table 4-9 V Dynamic Tolerance V (2) CORE V Voltage 1.25 V 1.25V±3% (3) TT V Voltage 1.365 1.5 1.635 V (4) TT IV Termination Supply Current 800 mA (5) TT V -2% 2/3 V +2% V REF TT R 50 56 115 (6) TT Ω V – 1.5V Supply Voltage 1.365 1.635 V 1.5 Notes: 1. DC measurement 2. AC noise measured with bandwidth limited to 20MHz 3. Universal Socket370 boards must hold VTT to 1.25V ±9% while the bus is active and 1.25V ±3% when bus is idle. 4. Legacy Socket370 boards 5. DC measurement. Measured with 250 µs sampling rate. 6. RTT is controlled by RTTCTRL pin. RTTCTRL should be 56Ω when relying upon on-die bus termination. RTTCTRL should be 110Ω when relying upon board termination. 4-12 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Table 4-9. V Static and Transient Tolerance CC Voltage Deviation from VID Setting (mV) Icc (A) Static Tolerance Transient Tolerance Min Max Min Max 0 15 65 5 85 2 5 55 -5 74 4 -5 45 -15 62 6 -15 35 -25 51 8 -25 25 -35 40 10 -35 15 -45 28 12 -45 5 -55 17 14 -55 -5 -65 6 16 -65 -15 -76 -5 18 -75 -25 -87 -15 20 -85 -35 -98 -25 22 -95 -45 -110 -35 24 -105 -55 -121 -45 26 -115 -65 -132 -55 28 -125 -75 -144 -65 30 -135 -85 -155 -75 Section 4 Electrical Specifications 4-13 VIA C3 Nehemiah Processor Datasheet September 29, 2004 4.2.2 MAXIMUM RATINGS While functional operation is not guaranteed beyond the operating ranges listed in Table 4-8, the device may be subjected to the limits specified in Table 4-10 without causing long-term damage. These conditions must not be imposed on the device for a sustained period—any such sustained imposi- tion may damage the device. Likewise exposure to conditions in excess of the maximum ratings may damage the device. Table 4-10. Maximum Ratings PARAMETER MIN MAX UNITS NOTES Storage Temperature -65 150 °C Supply Voltage (V) -0.5 1.7 V CC CMOS I/O Voltage -0.5 V+0.5 V CMOS I/O Voltage -0.5 V+0.5 V TT 4-14 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 4.2.3 DC CHARACTERISTICS Table 4-11. DC Characteristics PARAMETER MINMAXUNITSNOTES I – Low level output current -9.0 mA @ V = V OL OL(max) V – High Level Output Voltage V V OH TT V – Low Level Output Voltage 0 0.4 V @ I = -8mA OL ol I – Input Leakage Current ± 15 µA L I – Input Leakage Current for inputs with pull-ups 200 µA LU I – Input Leakage Current for inputs with pull-downs -400 LD µA Table 4-12. CMOS DC Characteristics PARAMETER MIN MAX UNITS NOTES V -- Input Low Voltage -0.58 0.700 V IL V – Input High Voltage V + 0.2 V V (2) IH1.5 REF TT V – Input High Voltage 2.0 3.18 V (3) IH2.5 V – Low Level Output Voltage 0.40 V @ I OL OL V – High Level Output Voltage V V (1) OH CMOS I – Low Level Output Current 9 mA @ V OL OL I – Input Leakage Current ±100 µA (4) LI I – Output Leakage Current ±100 µA (4) LO Notes: 1. All CMOS signals are open drain. 2. Applies to all CMOS signals except BCLK. 3. Applies only to BCLK. 4. Leakage current is specified for the range between VSS and VCC. I/O’s are diode clamped to the VCC and VSS rails. BCLK has three series diodes between the input and VCC and a single diode between the input and VSS. All other signals have a single diode between the signal and VCC and another single diode between the signal and VSS. Section 4 Electrical Specifications 4-15 VIA C3 Nehemiah Processor Datasheet September 29, 2004 4.2.4 POWER DISSIPATION Table 4-13 gives the core power consumption for the VIA C3 Nehemiah processor at the various operat- ing frequencies and voltages. Note that this does not include the power consumed by the I/O pads. Table 4-13. Thermal Design Power Information 1,2 PARAMETER TDP MAX UNITS NOTES Normal Mode Nehemiah 1.00 GHz (CPGA) 1.45V 15.0 W Nehemiah 1.13 GHz (CPGA) 1.45V 15.0 W 70°C, 3, 5 Nehemiah 1.20 GHz (CPGA) 1.45V 19.0 W Notes: 1. Maximum power is generated from running publicly available application software that consumes the most power. Synthetic applications or “thermal virus” applications may consume more power. 2. TDP Max is average value of all processors while running the worst case instruction sequence. Not 100% guaranteed or tested. Consider these power numbers as an average of all parts and some deviation is ex- pected. 3. The above power consumption is preliminary and based on case temperature as noted. 4. All normal mode frequencies use 133MHz as the CPU clock frequency. 5. Conservative thermal solutions must be designed to account for worst-case core and I/O power consumption. Table 4-14. VTT-I/O Power Consumption PARAMETER TYPICAL MAX UNITS NOTES PTT-I/O – I/O Operating Power Consumption 0.3 1.2 W 4-16 Electrical Specifications Section 4 September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION MECHANICAL SPECIFICATIONS 5.1 CPGA PACKAGE The VIA C3 Nehemiah processor is available in a Ceramic Pin Grid Array (CPGA) package for Socket 370 motherboards. Section 5 Mechanical Specifications 5-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 AN AN RSV A12# A16# A6# VTT RSV VTT BPRI# DEFER# VTT RSV TRDY# DRDY# BR0# ADS# RSV RSV RSV AM AM RSV VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VID1 AL AL RSV VSS A15# A13# A9# RSV VTT A7# REQ4# REQ3# VTT HITM# HIT# DBSY# THRMDN THRMDP RSV VID0 VID2 AK AK VCC RSV A28# A3# A11# VREF6 A14# VTT REQ0# LOCK# VREF7 RSV PWRGOOD RS2# RSV RSV VCC VID4 AJ AJ A21# RSV VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC BSEL1 BSEL0 SMI# VID3 AH AH VSS RESET# A10# A5# A8# A4# BNR# REQ1# REQ2# VTT RS1# VCC RS0# RSV SLP# VCC VSS VCC AG AG RSV A19# VSS INIT# STPCLK# IGNNE# AF AF A25# VSS VCC RSV VCC VSS AE AE A17# A22# VCC A20M# RSV FLUSH# AD AD VSS A31# VREF5 VCC VSS V1.5 AC AC RSV A20# VSS VSS FERR# RSV AB AB A23# VSS VCC A24# VCC VCMOS AA AA A27# A30# VCC VTT VTT RSV Z Z VSS A29# A18# VCC VSS V2.5 Y Y RSV A26# VSS RSV VCC VSS X X BR1# RESET2# RSV VSS RSV VSS W W D0# RSV VCC PLL1 RSV BCLK V VIA Nehemiah V VSS RSV VSS VCC VREF4 VCC U U D4# D15# VSS PLL2 VTT VTT CPGA T T VCC D1# D6# VSS VCC VSS S S (PIN SIDE VIEW) D8# D5# VCC VTT RTTCTRL VTT R R RSV D17# VREF3 VCC VSS VCC Q Q D12# D10# VSS RSV RSV RSV P P D9# VSS VCC D18# VCC VSS N N D2# D14# VCC RSV RSV NCHCTRL M M VSS D11# D3# VCC VSS INTR L L D13# D20# VSS RSV PICD1 NMI K K VCC VREF2 D24# VCC VCC VSS J J D7# D30# PICCLK PICD0 RSV VCC H H D19# VCC VSS D16# VSS VCC G G D21# D23# VSS RSV VTT RSV F F VCC VCC D32# D22# RSV D27# VCC D63# VREF1 VSS VCC VSS VCC VSS VCC VSS VCC VSS E E D26# D25# VCC VSS VCC VSS VCC VSS VCC VSS RSV VTT D62# RSV RSV RSV VREF0 RSV RSV D D VSS VSS VCC D38# D39# D42# D41# D52# VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS C C D33# VCC D31# D34# D36# D45# D49# D40# D59# D55# D54# D58# D50# D56# RSV RSV RSV RSV CPUPRES# B B D35# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC RSV A A D29# D28# D43# D37# D44# D51# D47# D48# D57# D46# D53# D60# D61# RSV RSV RSV RSV VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Figure 5-1. CPGA Pinout (Pinside View) 5-2 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Table 5-1. CPGA Pin Cross Reference Address Data Control Power/other VCCVTT VSS Reserved Name Ball Name Ball Name Ball Name Ball Ball Ball Ball Ball AA-5 AH-20 AM-22 AK-24 A3# AK-8 D0# W-1 A20M# AE-33 CPUPRES# C-37 AB-2 AK-16 AM-26 AL-11 A4# AH-12 D1# T-4 ADS# AN-31 PLL1 W-33 AB-34 AL-13 AM-30 AN-13 A5# AH-8 D2# N-1 BCLK W-37 PLL2 U-33 AD-32 AL-21 AM-34 V-4 A6# AN-9 D3# M-6 BNR# AH-14 V AD-36 1.5 AE-5 AN-11 AM-6 B-36 A7# AL-15 D4# U-1 BPRI# AN-17 V Z-36 2.5 E-5 AN-15 B-12 G-33 A8# AH-10 D5# S-3 BR0# AN-29 V AB-36 CMOS A9# AL-9 D6# T-6 BR1# X-2 VID0 AL-35 E-9 G-35 B-16 E-37 A10# AH-6 D7# J-1 BSEL0 AJ-33 VID1 AM-36 F-14 AA-33 B-20 C-35 A11# AK-10 D8# S-1 BSEL1 AJ-31 VID2 AL-37 F-2 AA-35 B-24 E-35 A12# AN-5 D9# P-6 DBSY# AL-27 VID3 AJ-37 F-22 AN-21 B-28 C-33 F-26 E-23 B-32 C-31 A13# AL-7 D10# Q-3 DEFER# AN-19 VID4 AK-36 F-30 S-33 B-4 A-33 A14# AK-14 D11# M-4 DRDY# AN-27 V E-33 REF0 F-34 S-37 B-8 A-31 A15# AL-5 D12# Q-1 FERR# AC-35 V F-18 REF1 F-4 U-35 D-18 E-31 A16# AN-7 D13# L-1 FLUSH# AE-37 V K-4 REF2 H-32 U-37 D-2 C-29 A17# AE-1 D14# N-3 HIT# AL-25 V R-6 REF3 H-36 D-22 E-29 A18# Z-6 D15# U-3 HITM# AL-23 V V-6 REF4 J-5 D-26 A-29 A19# AG-3 D16# H-4 IGNNE# AG-37 V AD-6 REF5 K-2 D-30 A-35 A20# AC-3 D17# R-4 INIT# AG-33 V AK-12 REF6 K-32 D-34 G-37 A21# AJ-1 D18# P-4 INTR M-36 V AK-22 REF7 K-34 D-4 L-33 A22# AE-3 D19# H-6 NMI L-37 THERMDN AL-29 M-32 Z-34 N-33 A23# AB-6 D20# L-3 LOCK# AK-20 THERMDP AL-31 N-5 E-11 N-35 A24# AB-4 D21# G-1 PWRGOOD AK-26 P-2 E-15 Q-33 A25# AF-6 D22# F-8 REQ0# AK-18 P-34 E-19 Q-35 A26# Y-3 D23# G-3 REQ1# AH-16 R-32 E-7 Q-37 A27# AA-1 D24# K-6 REQ2# AH-18 R-36 F-20 R-2 A28# AK-6 D25# E-3 REQ3# AL-19 S-5 F-24 W-35 A29# Z-4 D26# E-1 REQ4# AL-17 T-2 F-28 Y-1 A30# AA-3 D27# F-12 RESET# AH-4 T-34 F-32 AK-30 A31# AD-4 D28# A-5 RESET2# X-4 V-32 F-36 AM-2 D29# A-3 RS0# AH-26 V-36 G-5 F-10 D30# J-3 RS1# AH-22 D31# C-5 RS2# AK-28 W-5 H-2 AN-23 D32# F-6 SLP# AH-30 Y-35 H-34 AC-37 D33# C-1 SMI# AJ-35 Z-32 K-36 AL-33 D34# C-7 STPCLK# AG-35 AF-2 L-5 AN-35 AH-24 M-2 AN-37 D35# B-2 TRDY# AN-25 Section 5 Mechanical Specifications 5-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Address Data Control Power/other VCCVTT VSS Reserved Name Ball Name Ball Name Ball Name Ball Ball Ball Ball Ball AH-32 M-34 AH-28 D36# C-9 RTTCTRL S-35 AH-36 P-32 AK-32 D37# A-9 NCHCTRLN-37 P-36 AN-33 D38# D-8 PICCLK J-33 AJ-13 AJ-17 A-37 E-27 D39# D-10 PICD0 J-35 AJ-21 AB-32 AG-1 D40# C-15 PICD1 L-35 AJ-25 AC-33 E-21 D41# D-14 AJ-29 AC-5 AC-1 D42# D-12 AJ-5 AD-2 W-3 D43# A-7 AK-2 AD-34 AF-4 D44# A-11 D45# C-11 AK-34 AF-32 X-6 D46# A-21 AM-12 AF-36 Y-33 D47# A-15 AM-16 AG-5 J-37 D48# A-17 AM-20 AH-2 AE-35 AM-24 AH-34 AA-37 D49# C-13 AM-28 AJ-11 AJ-3 D50# C-25 AM-32 AJ-15 AK-4 D51# A-13 AM-4 AJ-19 AL-1 D52# D-16 AM-8 AJ-23 X-34 D53# A-23 B-10 AJ-27 AN-3 D54# C-21 B-14 AJ-7 D55# C-19 B-18 AL-3 D56# C-27 B-22 AM-10 D57# A-19 B-26 AM-14 D58# C-23 B-30 AM-18 D59# C-17 B-34 Q-5 D60# A-25 B-6 R-34 D61# A-27 C-3 T-32 D62# E-25 D-20 T-36 D63# F-16 D-24 U-5 D-32 V-2 D-36 V-34 D-6 X-32 E-13 X-36 E-17 Y-37 AJ-9 Y-5 D-28 Z-2 AF-34 5-4 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Figure 5-2. CPGA with Heat Slug Dimensions Table 5-2. CPGA Package Dimensions Millimeters Inches Symbol Typical Min Max Notes Typical Min Max Notes A 1.96 1.76 2.16 0.077 0.069 0.085 A1 1.00 typical 0.039 typical A2 2.96 2.72 3.33 0.116 0.107 0.131 φB 0.046 0.41 0.51 0.018 0.016 0.020 D 49.53 49.28 49.83 1.950 1.940 1.962 D1 45.72 45.47 45.97 1.8 1.790 1.810 D2 25.4 25.02 25.78 1.00 0.985 1.015 e1 2.54 2.41 2.67 0.100 0.095 0.105 L 3.18 2.98 3.38 0.125 0.117 0.133 N 370 Lead 370 Lead count count S1 1.905 1.65 2.16 0.075 0.065 0.085 Section 5 Mechanical Specifications 5-5 VIA C3 Nehemiah Processor Datasheet September 29, 2004 A B C D E F G H I J K L M N O 18.40 9.18 3.24 0.81 7.74 0.50 1.15 1.75 1.28 0.65 0.78 0.22 1.54 0.96 19.70 Dimension Units: MM Speed Code: Core Speed and FSB Speed AAA BBB CC.C Description 1.4 100 14.0 1.4AGHz 1.4 133 10.5 1.4AGHz 1.3 133 10.0 1.3AGHz 1.3 100 13.0 1.3AGHz 1.2 100 12.0 1.2AGHz 1.2 133 9.0 1.2AGHz 1.1 100 11.0 1.1AGHz 1.0 100 10.0 1.0AGHz 1.0 133 7.5 1.0AGHz Figure 5-3. CPGA Top Marking Design 5-6 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 5.2 EBGA PACKAGE The VIA C3 Nehemiah in EBGA is packaged in a unique enhanced ball grid array that facilitates compact and economical surface mounting. The VIA C3 Nehemiah in EBGA bus is functionally similar to Socket 370 used by conventional CPGA VIA C3 Nehemiah’s but is obviously not mechanically compatible. Section 5 Mechanical Specifications 5-7 VIA C3 Nehemiah Processor Datasheet September 29, 2004 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 1 VSS D19# VCC D24# VCC D13# VSS VCC D9# D10# VSS VCC D1# D4# VSS VCC A29# A27# VSS VSS A31# A22# A21# BRB1 VSS VSS 2 D23# VSS D30# VCC VSS D3# VTT D14# D18# D12# VCC D5# D6# D15# VCC A26# A18# A30# VCC A23# A17# VSS VCC VCC VSS A28# 3 D21# VCC VSS D7# D20# VCC D11# D2# VSS VCC D17# D8# VSS VTT D0# RESET# VTT VCC A24# A20# VTT A19# A25# VSS A10# VCC 4 VCC D26# D16# VCC VSS VCC VREF2 VSS VSS VCC VREF3 VSS VSS VCC VREF4 VSS VSS VCC VSS VSS VREF5 VCC VCC A12# VCC A15# 5 D32# VSS D25# VCC VSS VTT VSS VCC VTT VSS VSS A5# VSS A13# 6 D31# D35 D33# VSS VCC A3# A16# A9# 7 VCC D28# D29# VSS VSS A6# VCC VSS 8 VSS D43# D34# VCC VCC VSS VSS VTT A8# VCC 9 D38# D22# VCC VCC VTT VTT VREF6 A4# A11# BNR# 10 D37# D36# VTT VSS VCC VCC A14# A7# 11 VCC D45# D39# VSS VCC REQ1# REQ4# VSS 12 VSS D27# D44# VCC VSS BPRI# REQ2# VCC 13 D49# D42# VTT VCC VCC VSS VSS VTT REQ0#DEFER# Bottom View 14 D41# D51# VSS VSS VSS VCC VCC VCC REQ3# LOCK# 15 VCC D47# D40# VSS VREF7 RS1# VTT VSS 16 VSS VCC D63# VREF1 VSS HITM# TRDY# VCC 17 D59# D52# VCC VCC VSS VSS HIT# PWRGD 18 D55# D48# VTT VSS VTT VTT VCC VCC RS0# DRDY# 19 VCC D54# D57# VSS VSS VCC VCC DBSY# RS2# VSS 20 VSS D46# PICCLK VCC VSS BREQ# ADS# VCC 21 THRM THRM D53# D58# VTT VCC VSS SLP# DN DP 22 D50# VSS D62# VSS VCC VTT VCC VSS VTT VSS RSV VTT VCC BSEL1 23 RTT D56# VCC D60# VREF0 VCC VSS VSS VCC PICD0 VSS BCLK RSV VSS PLL2 PLL1 VCC VSS VSS VCC VCC VSS VCC RSV RSV VSS CTRL 24 NCH STP VCC D61# RSV VCC VTT VCC VSS NMI VCC RSV PICD1 VCC VSS RSV FERR# VCC VSS A20M# VID3 VID2 VID0 VSS VCC BSEL0 CTRL CLK# 25 VCC VSS VCC VSS VSS VSS VTT INTR VSS VCC RSV RSV VSS VSS VCC VTT FLUSH# RSV VCC IGNNE# SMI# VSS VCC RSV VSS RSV 26 VSS VSS VSS RSV BR4 RSV RSV VSS VCC VCC VSS BR3 BR2 BR1 BR0 VSS RSV VTT VTT VSS INIT# VID4 VID1 VCC VSS VSS Figure 5-4. EBGA Ball Diagram (Bottom View) 5-8 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Table 5-3. EBGA Ball Cross Reference Address Data Control Power/other VCC VTT VSS Reserved Name Ball Name Ball Name Ball Name Ball Ball Ball Ball Ball 1 A3# AD-6 D0# R-3 A20M# W-24 PLL1 T-23 A-11 A-1 R-24 AA-3 1 A4# AD-9 D1# N-1 ADS# AE-20 PLL2 R-23 A-15 A-12 AC-22 AD-13 1 THERMDN A5# AD-5 D2# H-3 BCLK M-23 AE-21 A-19 AD-22 A-16 AE-23 1 A6# AD-7 D3# F-2 BNR# AF-9 THERMDPAF-21 A-24 A-20 AD-25 AD-8 1 A7# AF-10 D4# P-1 BPRI# AD-12 VID0 AC-24 A-25 A-26 AD-23 AE-15 1 BREQ# A8# AE-8 D5# M-2 AD-20 VID1 AC-26 A-4 A-8 AF-25 C-10 1 BSEL0 A9# AF-6 D6# N-2 AF-24 VID2 AB-24 A-7 C-13 AB-13 G-26 1 A10# AE-3 D7# D-3 BSEL1 AF-22 VID3 AA-24 AA-23 AB-2 D-26 C-18 1 A11# AE-9 D8# M-3 DBSY# AD-19 VID4 AB-26 AB-19 AB-23 F-26 C-21 1 DEFER# A12# AD-4 D9# J-1 AF-13 VREF0 D-23 AB-4 E-24 AB-25 L-25 1 A13# AF-5 D10# K-1 DRDY# AF-18 VREF1 D-16 AB-14 G-2 AB-8 M-25 1 A14# AE-10 D11# G-3 FERR# T-24 VREF2 G-4 AC-10 AC-12 V-25 G-25 1 A15# AF-4 D12# K-2 FLUSH# U-25 VREF3 L-4 AC-11 AC-13 U-26 P-3 1 A16# AE-6 D13# F-1 HIT# AE-17 VREF4 R-4 AC-14 T-25 AC-16 C-24 1 A17# AA-2 D14# H-2 HITM# AD-16 VREF5 AA-4 AC-18 AC-17 L-24 U-3 1 A18# U-2 D15# P-2 IGNNE# Y-25 VREF6 AC-9 AC-19 AC-20 N-23 W-26 1 A19# AB-3 D16# C-4 INIT# AA-26 VREF7 AC-15 AC-2 AC-21 V-26 A20# Y-3 D17# L-3 INTR H-25 AC-23 AB-9 AC-5 A21# AC-1 D18# J-2 LOCK# AF-14 AC-25 AB-18 AC-7 A22# AB-1 D19# B-1 NMI H-24 AC-4 V-5 AC-8 A23# Y-2 D20# E-3 PWRGD AF-17 AC-6 V-22 AD-17 REQ0# A24# W-3 D21# A-3 AE-13 AD-10 J-5 AD-24 A25# AC-3 D22# B-9 REQ1# AD-11 AD-14 J-22 AD-3 A26# T-2 D23# A-2 REQ2# AE-12 AD-18 E-9 AE-1 A27# V-1 D24# D-1 REQ3# AE-14 AD-26 E-18 AE-2 REQ4# A28# AF-2 D25# C-5 AE-11 AD-2 AE-25 A29# U-1 D26# B-4 RESET# T-3 AE-22 AE-26 A30# V-2 D27# B-12 RS0# AE-18 AE-24 AE-5 A31# AA-1 D28# B-7 RS1# AD-15 AE-4 AF-1 Section 5 Mechanical Specifications 5-9 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Address Data Control Power/other VCC VTT VSS Reserved D29# C-7 RS2# AE-19 AF-20 AF-23 D30# C-2 SMI# AA-25 AF-3 AF-26 A-6 D31# STPCLK# Y-24 AF-8 AF-7 D32# A-5 TRDY# AE-16 B-16 B-2 D33# C-6 BR0 R-26 B-23 B-22 D34# C-8 BR1 P-26 B-3 B-25 D35# B-6 BR2 N-26 C-1 B-26 D36# B-10 BR3 M-26 C-17 B-5 D37# A-10 BR4 E-26 C-25 C-14 NCHCTRL D38# A-9 K-24 C-9 C-3 D39# C-11 PICCLK C-20 D-12 C-26 K-23 D40# C-15 PICD0 D-13 D-10 D41# A-14 PICD1 M-24 D-17 D-11 D42# B-13 BRB1 AD-1 D-2 D-14 D43# B-8 D-20 D-15 D44# C-12 D-21 D-18 D45# B-11 D-24 D-19 D46# B-20 D-4 D-22 D47# B-15 D-5 D25 D48# B-18 D-8 D-6 D49# A-13 D-9 D-7 D50# A-22 E-1 E-14 D51# B-14 E-13 E-19 D52# B-17 E-23 E-2 D53# A-21 E-8 E-25 D54# B-19 F-24 E-4 D55# A-18 F-3 F-23 D56# A-23 F-4 F-25 D57# C-19 H-1 G-1 D58# B-21 H-22 G-23 D59# A-17 H-23 G-24 D60# C-23 J-24 H-26 5-10 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Address Data Control Power/other VCC VTT VSS Reserved D61# B-24 J-26 H-4 D62# C-22 K-25 H-5 D63# C-16 K-26 J-25 K-3 J-3 K-4 J-4 L-2 L-1 M-1 L-23 N-22 L-26 N-24 M-4 P-4 N-25 P-5 N-3 R-2 N-4 R-25 N-5 T-1 P-22 U-23 P-23 U-24 P-24 V-3 P-25 V-4 R-1 W-2 T-26 W-25 T-4 Y-23 U-4 AE-7 V-23 AF-12 V-24 AF-16 W-1 AF-20 W-4 W-5 W-22 W-23 Y-1 Y-4 Y-26 Section 5 Mechanical Specifications 5-11 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Address Data Control Power/other VCC VTT VSS Reserved AF-11 AF-15 AF-19 5-12 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet Allowable Pressure on the top of the package is 800 kPa (116 Psi) Figure 5-5. EBGA Mechanical Specification Section 5 Mechanical Specifications 5-13 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Remark: 1. The “S” means the clock ratio can be adjusted by M/B jumper. 2. The “E” means the temperature of case will not be higher than 85℃. 3. The “T” means termination on die. A B C D E F G H I J K L M N O P 18.40 9.18 3.24 0.81 7.74 0.50 1.15 1.75 1.28 0.65 0.78 0.22 1.54 0.96 1.30 19.70 Dimension Units: MM Speed Code: Core Speed and FSB Speed AAA BBB CC.C Description 1.4 100 14.0 1.4AGHz 1.4 133 10.5 1.4AGHz 1.3 133 10.0 1.3AGHz 1.3 100 13.0 1.3AGHz 1.2 100 12.0 1.2AGHz 1.2 133 9.0 1.2AGHz 1.1 100 11.0 1.1AGHz 1.0 100 10.0 1.0AGHz 1.0 133 7.5 1.0AGHz Figure 5-6. EBGA Top Marking Design 5-14 Mechanical Specifications Section 5 September 29, 2004 VIA C3 Nehemiah Processor Datasheet This page is intentionally left blank. Section 5 Mechanical Specifications 5-15 September 29, 2004 VIA C3 Nehemiah Processor Datasheet SECTION THERMAL SPECIFICATIONS 6.1 INTRODUCTION The VIA C3 Nehemiah is specified for operation with device case temperatures in the range of 0°C to 70°C (85°C for EBGA). Operation outside of this range will result in functional failures and may poten- tially damage the device. Care must be taken to ensure that the case temperature remains within the specified range at all times dur- ing operation. An effective heat sink with adequate airflow is therefore a requirement during operation. 6.2 TYPICAL ENVIRONMENTS Typical thermal solutions involve three components: a heat sink, an interface material between the heat sink and the package, and a source of airflow. The best thermal solutions rely on the use of all three com- ponents. To the extent that any of these components are not used, the other components must be improved to compensate for such omission. In particular, the use of interface material such as thermal grease, silicone paste, or graphite paper can make a 40°C difference in the case temperature. Likewise, the imposition of airflow is realistically a requirement. Section 6 Thermal Specifications 6-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 6.3 MEASURING T C The case temperature (T ) should be measured by attaching a thermocouple to the center of the VIA C3 C Nehemiah package. The heat produced by the processor is very localized so measuring the case tempera- ture anywhere else will underestimate the case temperature. The presence of a thermocouple is inherently invasive; effort must be taken to minimize the effect of the measurement. The thermocouple should be attached to the processor through a small hole drilled in the heat sink. Thermal grease should be used to ensure that the thermocouple makes good contact with the package, but the thermocouple should not come in direct contact with the heat sink. Physical Test Conditions Case temperature measurements should be made in the worst case operating environments. Ideally, sys- tems should be maximally configured, and tested at the worst-case ambient temperature. Test Patterns During normal operation the processor attempts to minimize power consumption. Consequently, normal power consumption is much lower than the maximum power consumption. Thermal testing should be done while running software which causes the processor to operate at its thermal limits. 6.4 MEASURING T J The junction temperature of the die can be measured by using the processor’s on-chip diode. 6-2 Thermal Specifications Section 6 September 29, 2004 VIA C3 Nehemiah Processor Datasheet 6.5 ESTIMATING T C The VIA C3 Nehemiah processor’s case temperature can be estimated based on the general characteristics of the thermal environment. This estimate is not intended as a replacement for actual measurement. Case temperature can be estimated where, T ≡ Ambient Temperature A T ≡ Case Temperature C θ ≡ case-to-ambient thermal resistance CA θ ≡ junction-to-ambient thermal resistance JA θ ≡ junction-to-case thermal resistance JC P ≡ power consumption (Watts) and, T = T + (P * θ ) J C JC T = T – (P * θ ) A J JA T = T – (P * θ ) A C CA θ = θ – θ CA JA JC Section 6 Thermal Specifications 6-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 This page is intentionally left blank. 6-4 Thermal Specifications Section 6 September 29, 2004 VIA C3 Nehemiah Processor Datasheet APPENDIX MACHINE SPECIFIC REGISTERS A.1 GENERAL Tables A-1 and A-2 summarize the VIA C3 Nehemiah processor machine-specific registers (MSRs). Fur- ther description of each MSR follows the table. MSRs are read using the RDMSR instruction and written using the WRMSR instruction. There are four basic groups of MSRs (not necessarily with contiguous addresses). Other than as defined below, a reference to an undefined MSR causes a General Protection exception. 1. Generally these registers can have some utility to low-level programs (like BIOS). Note that some of the MSRs (address 0 to 0x4FF) have no function in the VIA C3 Nehemiah proc- essor. These MSRs do not cause a GP when used on the VIA C3 Nehemiah processor; instead, reads to these MSRs return zero, and writes are ignored. Some of these undocumented MSRs may have ill side effects when written to indiscriminately. Do not write to undocumented MSRs. 2. There are some undocumented internal-use MSRs used for low-level hardware testing purposes. At- tempts to read or write these undocumented MSRs cause unpredictable and disastrous results; so don’t use MSRs that are not documented in this datasheet! 3. MSRs used for cache and TLB testing. These use MSR addresses that are not used on compatible processor. These test functions are very low-level and complicated to use. They are not documented in this datasheet but the information will be provided to customers given an appropriate justification MSRs are not reinitialized by the bus INIT interrupt; the setting of MSRs is preserved across INIT. Appendix A Machine Specific Registers A-1 VIA C3 Nehemiah Processor Datasheet September 29, 2004 Table A-1. Category 1 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES TSC Time Stamp Counter 10h TSC[63:32] TSC[31:0] RW EBL_CR_POWERON EBL_CR_POWERON 2Ah n/a Control bits RW PERFCTR0 Performance counter 0 C1h TSC[39:32] TSC[31:0] RW 1 PERFCTR1 Performance counter 1 C2h 0 Count[31:0] RW BBL_CR_CTL3 L2 Hardware Disabled 11Eh n/a 00800000h RO EVNTSEL0 Event counter 0 select 186h n/a 00470079h RO 1 EVNTSEL1 Event counter 1 select 187h n/a Control bits RW MTRR MTRRphysBase0 200h Control bits Control bits RW MTRR MTRRphysMask0 201h Control bits Control bits RW MTRR MTRRphysBase1 202h Control bits Control bits RW MTRR MTRRphysMask1 203h Control bits Control bits RW MTRR MTRRphysBase2 204h Control bits Control bits RW MTRR MTRRphysMask2 205h Control bits Control bits RW MTRR MTRRphysBase3 206h Control bits Control bits RW MTRR MTRRphysMask3 207h Control bits Control bits RW MTRR MTRRphysBase4 208h Control bits Control bits RW MTRR MTRRphysMask4 209h Control bits Control bits RW MTRR MTRRphysBase5 20Ah Control bits Control bits RW MTRR MTRRphysMask5 20Bh Control bits Control bits RW MTRR MTRRphysBase6 20Ch Control bits Control bits RW MTRR MTRRphysMask6 20Dh Control bits Control bits RW MTRR MTRRphysBase7 20Eh Control bits Control bits RW MTRR MTRRphysMask7 20Fh Control bits Control bits RW MTRR MTRRfix64K_00000 250h Control bits Control bits RW MTRR MTRRfix16K_80000 258h Control bits Control bits RW MTRR MTRRfix16K_A0000 259h Control bits Control bits RW MTRR MTRRfix4K_C0000 268h Control bits Control bits RW MTRR MTRRfix4K_C8000 269h Control bits Control bits RW MTRR MTRRfix4K_D0000 26Ah Control bits Control bits RW MTRR MTRRfix4K_D8000 26Bh Control bits Control bits RW MTRR MTRRfix4K_E0000 26Ch Control bits Control bits RW MTRR MTRRfix4K_E8000 26Dh Control bits Control bits RW MTRR MTRRfix4K_F0000 26Eh Control bits Control bits RW MTRR MTRRfix4K_F8000 26Fh Control bits Control bits RW MTRR MTRRdefType 2FFh Control bits Control bits RW A-2 Machine Specific Registers Appendix A September 29, 2004 VIA C3 Nehemiah Processor Datasheet Notes: 1. PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR that reflects this limitation. Table A-2. Category 2 MSRs MSR MSR NAME ECX EDX EAX TYPE NOTES FCR Feature Control Reg 1107h n/a FCR value RW FCR2 Feature Control Reg 2 1108h FCR2_Hi FCR2 value RW 1 FCR3 Feature Control Reg 3 1109h FCR3_Hi FCR3 value WO 1 Notes: 1. FCR2 and FCR3 provide system software with the ability to specify the Vendor ID string returned by the CPUID instruction. Appendix A Machine Specific Registers A-3 VIA C3 Nehemiah Processor Datasheet September 29, 2004 A.2 CATEGORY 1 MSRS 10H: TSC (TIME STAMP COUNTER) VIA C3 Nehemiah processor has a 64-bit MSR that materializes the Time Stamp Counter (TSC). System increments the TSC once per processor clock. The TSC is incremented even during AutoHalt or Stop- Clock. A WRMSR to the TSC will clear the upper 32 bits of the TSC. 2AH: EBL_CR_POWERON 31:27 27 26 25:22 21:2019:1817:15 14 13 12:0 Res BF4 Low- BF[3:0] Res BSEL Res 1MPOV IOQDepth Reserved '11000 PowerEn (Ignored on write; ' returns 0 on '1' read) 5 1 1 4 2 2 3 1 1 13 IOQDepth: 0 = In Order Queue Depth with up to 8 transactions 1 = 1 transaction 1MPOV: 0 = Power on Reset Vector at 0xFFFFFFF0 (4Gbytes) 1 = Power on Reset Vector at 0x000FFFF0 (1 Mbyte) BSEL: 01 = 133 MHz Bus 10 = 100 MHz Bus A-4 Machine Specific Registers Appendix A September 29, 2004 VIA C3 Nehemiah Processor Datasheet BF[4:0]: Bus Clock Frequency Ratio Nehemiah MSR 0x2A [27] MSR 0x2A [25:22] 5.0 0 0000b 16.0 0 0001b Reserved 0 0010b 10.0 0 0011b 5.5 0 0100b Reserved 0 0101b Reserved 0 0110b 9.5 0 0111b 9.0 0 1000b 7.0 0 1001b 1010b 8.0 0 1011b 6.0 0 1100b 12.0 0 1101b 7.5 0 1110b 8.5 0 1111b 6.5 0 0000b 9.0 1 0001b Reserved in Steppings 0 &1 1 11.0 otherwise 0010b 12.0 1 0011b 10.0 1 0100b 13.5 1 0101b 11.5 1 0110b 12.5 1 0111b 10.5 1 1000b 13.0 1 1001b 15.0 1 1010b 16.0 1 1011b 14.0 1 1100b 12.0 1 1101b 15.5 1 1110b Reserved 1 1111b 14.5 1 Appendix A Machine Specific Registers A-5 VIA C3 Nehemiah Processor Datasheet September 29, 2004 LowPowerEn: This bit always set to '1' C1H-C2H: PERFCTR0 & PERFCTR1 These are events counters 0 and 1. VIA C3 Nehemiah processor’s PERFCTR0 is an alias for the lower 40 bits of the TSC. 11EH: BBL_CR_CTL3 31:24 23 22:0 Reserved L2_Hdw_Disable Reserved (Ignored on write; ‘1’ returns 0 on read) 8 1 23 The VIA C3 Nehemiah processor does contain an L2 cache. For compatibility, this read-only MSR indi- cates to the BIOS or system software that the L2 is disabled even if the L2 is enabled. L2_Hdw_Disable: This bit always set to '1' A-6 Machine Specific Registers Appendix A September 29, 2004 VIA C3 Nehemiah Processor Datasheet 186H: EVNTSEL0 (EVENT COUNTER 0 SELECT) 31:24 23:16 15:9 8:0 Reserved Reserved Reserved CTR0 Event Select = 79h 8 8 7 9 PERFCTR0 is an alias for the lower 40 bits of the Time Stamp Counter. EVNTSEL0 is a read only MSR which reflects this limitation. The CTR0_Event Select field always returns 0x0079, which corresponds to counting of processor clocks. 187H: EVNTSEL1 (EVENT COUNTER 1 SELECT) 31:24 23:16 15:9 8:0 Reserved Reserved Reserved CTR1 Event Select 8 8 7 9 VIA C3 Nehemiah processor have two MSRs that contain bits defining the behavior of the two hardware event counters: PERFCTR0 and PERFCTR1. The CTR1_Event_Select control field defines which of several possible events is counted. The possible Event Select values for PERFCTR1 are listed in the table below. Note that CTR1_Event_Select is a 9-bit field. The EVNTSEL1 register should be written before PERFCTR1 is written to initialize the counter. The counts are not necessarily perfectly exact; the counters are intended for use over a large number of events and may differ by one or two counts from what might be expected. Most counter events are internal implementation-dependent debug functions, having no meaning to soft- ware. The counters that can have end-user utility are: EVENT DESCRIPTION C0h Instructions executed 1C0h Instructions executed and string iterations 79h Internal clocks (default event for CTR0) Appendix A Machine Specific Registers A-7 VIA C3 Nehemiah Processor Datasheet September 29, 2004 A.3 CATEGORY 2 MSRs 1107H: FCR (FEATURE CONTROL REGISTER) The FCR controls the major optional feature capabilities of the VIA C3 Nehemiah processor. Table A-3 contains the bit values for the FCR. The default settings shown for the FCR bits are not necessarily exact. The actual settings can be changed as part of the manufacturing process and thus a particular VIA C3 Ne- hemiah processor version can have slightly different default settings than shown here. All reserved bit values of the FCR must be preserved by using a read-modify-write sequence to update the FCR. Table A-3. FCR Bit Assignments BIT NAME DESCRIPTION DEFAULT 0 ALTINST 0 Reserved for test & special uses 1 ECX8 Enables CPUID reporting CX8 1 2 Reserved 1 3 Reserved 0 4 Reserved 0 5 DSTPCLK Disables supporting STPCLK 0 6 Reserved 0 7 EPGE Enables CR4.PGE and CPUID.PGE (Page Global Enable) 1 8 DL2 Disables L2 Cache 0 9 Reserved 1 10 Reserved 0 11 Reserved 0 12 EBRPRED Enables Branch Prediction 1 13 DIC Disables I-Cache 0 14 DDC Disables D-Cache 0 31:15 Reserved 0/1 A-8 Machine Specific Registers Appendix A September 29, 2004 VIA C3 Nehemiah Processor Datasheet ALTINST: 0 = Normal x86 instruction execution. 1 = Alternate instruction set execution is enabled (see details below) ECX8: 0 = The CPUID instruction does not report the presence of the CMPXCHG8B instruction (CX8 = 0). The instruction actually exists and operates correctly, however. 1 = The CPUID instruction reports that the CMPXCHG8B instruction is supported (CX8 = 1). DSTPCLK: 0 = STPCLK interrupt properly supported. 1 = Ignores SPCLK interrupt. EPGE: 0 = The processor does not support Page Global Enable and therefore CPUID Feature Flags reports EDX[13]=0; attempts to set CR4.PGE are ignored. 1 = The processor supports Page Global Enable and therefore CPUID Feature Flags re- ports EDX[13]=1; CR4.PGE can be set to 1. DL2: 0 = L2 Cache enabled. 1 = L2 Cache disabled. EBRPRED: 0 = Disables branch prediction function. 1 = Enables branch prediction function. DIC: 0 = Enables use of I-Cache. 1 = Disables use of I-Cache: cache misses are performed as single transfer bus cycles, PCD is de-asserted. This overrides any setting of CR0.CD and CR0.NW. DDC: 0 = Enables use of D-Cache. 1 = Disables use of D-Cache: same semantics as for DIC except for D-Cache. Appendix A Machine Specific Registers A-9 VIA C3 Nehemiah Processor Datasheet September 29, 2004 ALTERNATE INSTRUCTION EXECUTION When set to 1, the ALTINST bit in the FCR enables execution of an alternate (not x86) instruction set. While setting this FCR bit is a privileged operation, executing the alternate instructions can be done from any protection level. This alternate instruction set includes an extended set of integer, MMX, floating-point, and 3DNow! in- structions along with additional registers and some more powerful instruction forms over the x86 instruction architecture. For example, in the alternate instruction set, privileged functions can be used from any protection level, memory descriptor checking can be bypassed, and many x86 exceptions such as alignment check can be bypassed. This alternate instruction set is intended for testing, debug, and special application usage. Accordingly, it is not documented for general usage. If you have a justified need for access to these instructions, contact your VIA representative. The mechanism for initiating execution of this alternate set of instructions is as follows: 1. Set the FCR ALTINST bit to 1 using WRMSR instruction (this is a privileged instruction). This should be done using a read-modify-write sequence to preserve the values of other FCR bits. 2. The ALTINST bit enables execution of a new x86 jump instruction that starts execution of alter- nate instructions. This new jump instruction can be executed from any privilege level at any time that ALTINST is 1. The new jump instruction is a two-byte instruction: 0x0F3F. If ALTINST is 0, the execution of 0x0F3F causes an Invalid Instruction exception. 3. When executed, the new 0x0F3F x86 instruction causes a near branch to CS:EAX. That is, the branch function is the same as the existing x86 instruction � jmp [eax] � In addition to the branch, the 0x0F3F instruction sets the processor into an internal mode where the target bytes are not interpreted as x86 instructions but rather as alternate instruction set instructions. 4. The alternate instructions fetched following the 0x0F3F branch should be of the form � 0x8D8400XXXXXXXX where 0xXXXXXXXX is the 32-bit alternate instruction � That is, the alternate instructions are presented as the 32-bit displacement of a � LEA [EAX+EAX+disp] � instruction. This example assumes that the current code segment size is 32-bits, if it is 16-bits, then an address size prefix (0x67) must be placed in front of the LEA opcode. 5. Upon fetching, the LEA “wrapper” is stripped off and the 32-bit alternate instruction contained in the displacement field is executed. 6. The alternate instruction set contains a special branch instruction that returns control to x86 fetch and execute mode. The x86 state upon return is not necessarily what it was when alternate instruc- tion execution is entered since the alternate instructions can completely modify the x86 state. While all VIA C3 processor processors contain this alternate instruction feature, the invocation details (e.g., the 0x8D8400 “prefix”) may be different between processors. Check the appropriate processor data- sheet for details. A-10 Machine Specific Registers Appendix A September 29, 2004 VIA C3 Nehemiah Processor Datasheet 1108H: FCR2 (FEATURE CONTROL REGISTER 2) This MSR contains more feature control bits — many of which are undefined. It is important that all re- served bits are preserved by using a read-modify-write sequence to update the MSR. 63:32 Last 4 characters of Alternate Vendor ID string 31:15 14 13:12 11:8 7:4 3:0 Reserved AVS Res Family ID Model ID Res 17 1 2 4 4 4 AVS: 0 = The CPUID instruction vendor ID is “CentaurHauls” 1 = The CPUID instruction returns the alternate Vendor ID. The first 8 characters of the alternate Vendor ID are stored in FCR3 and the last 4 characters in FCR2[63:32]. These 12 characters are undefined after RESET and may be loaded by system software using WRMSR. Family ID: This field will be returned as the family ID field by subsequent uses of the CPUID in- struction Model ID: This field will be returned as the model ID field by subsequent uses of the CPUID in- struction 1109H: FCR (FEATURE CONTROL REGISTER 3) This MSR contains the first 8 characters of the alternate Vendor ID. The alternate Vendor ID is returned by the CPUID instruction when FCR2[AVS] is set to ‘1’. FCR3 is a write-only MSR. 63:32 First 4 characters of Alternate Vendor ID string 31:0 Middle 4 characters of Alternate Vendor ID string Appendix A Machine Specific Registers A-11