GE INTELLIGENT PLATFORMS VMIVME-7700RC
Specifications
Form Factor
VME
Ethernet Chipset
Intel 82571EB
Datasheet
Extracted Text
VMIVME-7700
® ®
A GE Fanuc Company Ultra Low Voltage Intel Celeron VMEbus
® ®
• Intel ’s Ultra Low Voltage Celeron 400 MHz/650 MHz processor
• Special features for embedded applications include:
— Up to 1 GB bootable Flash on secondary IDE (optional)
— Two 16-bit and two 32-bit programmable timers
— 32 KB of nonvolatile SRAM
— Software-selectable Watchdog timer with reset
— Remote Ethernet booting
— One PMC expansion site (IEEE-1386.1 PCI mezzanine card standard,
5 V)
— VME64 modes supported: A32/A24/D32/D16/D08(EO)/MBLT64/BLT32
— VMEbus interrupt handler, interrupter, and system controller
PHOTO NOT AVAILABLE
— Includes real-time endian conversion hardware for little-endian and
big-endian data interfacing (patent no. 6,032,212)
— Enhanced bus error handling
— Passive heat sink
— Real-time clock and miniature speaker included
— Dual front panel universal serial bus (USB) connections
• Standard features include:
— Up to 512 MB PC100 SDRAM
— 100 MHz system bus via Intel 815E chipset
— Dual Ethernet controllers supporting 10BaseT and 100BaseTX
interfaces
— Ultra DMA/100 hard drive and floppy drive controllers (uses VMEbus P2
for connection to IDE/floppy)
are provided on the front panel with two network status
— Two high performance 16550-compatible serial ports
indicators.
— PS/2-style keyboard and mouse ports on front panel
— VMEbus backplane interface
REMOTE ETHERNET BOOTING — The
— User programmable Watchdog timer
— Passive processor heat sink
VMIVME-7700 utilizes an Expansion ROM BIOS which
enables processor booting from a network server. The facility
MICROPROCESSOR — The VMIVME-7700 is
supports PXE and a variety of network boot protocols
based on the Intel Ultra Low Voltage Celeron processor.
including BOOTP and DHCP (TCP/IP).
The enhanced Celeron processor has 256 KB of on-die L2
cache. The µFCBGA package processors offer thermal
UNIVERSAL SERIAL BUS (USB) — The
characteristics that are well suited for embedded systems
VMIVME-7700 provides front panel dual connection hub
operating over a wide range of temperatures.
host controllers for the USB. Supported USB features
include: isochronous data transfers, asynchronous
DRAM MEMORY — The VMIVME-7700 accepts
messaging, self-identification and configuration of
one 144-pin SODIMM PC100 module for a maximum
peripherals, and dynamic (hot) attachment.
memory configuration of 512 MB.
SERIAL PORTS — The VMIVME-7700 provides two
16550-compatible serial ports. Each serial port has an
BIOS — The VMIVME-7700 System BIOS and video
independent 16-byte FIFO supporting baud rates up to
BIOS are provided in reprogrammable memory.
115 kbaud. Connection for both serial ports is provided by
VIDEO GRAPHIC CONTROLLER — High
resolution graphics and multimedia-quality video are
supported on the VMIVME-7700 by an internal 815E AGP
Ordering Options
graphics controller. A fully functional, integrated 2D/3D
May 02, 2003 800-007700-000 A A B C – D E F
graphics accelerator provides pixel processing and
rendering, with display resolutions of up to 1600 x 1200 VMIVME-7700 – –
supported. The video output is provided through the front
A = Processor
panel. 0 = 400 MHz Ultra Low Voltage Celeron Processor
1 = 650 MHz Ultra Low Voltage Celeron Processor
B = SDRAM Memory
CompactFlash — The VMIVME-7700 includes a
1 = 128 MB
CompactFlash socket on the assembly. The CompactFlash
2 = 512 MB
may be configured as the boot device through the BIOS boot C = CompactFlash
0 = No CompactFlash
device set up. The CompactFlash, as an ordering option, is
1 = 128 MB CompactFlash
available up to 1 GB of storage space.
2 = 256 MB CompactFlash
3 = 512 MB CompactFlash
IDE Interface — The VMIVME-7700 provides an 4 = 1 GB CompactFlash
D/E = Reserved
IDE interface for hard disk drive support. The IDE interface
allows support of several types of data transfers: Connector Adapter
Programmed I/O(PIO), 8237 style DMA, Ultra ATA/33,
VMIC Part Number 360-010050-01. The connector adapter is a 9-pin Micro-D to
Ultra ATA/66 and Ultra ATA/100. standard D serial adapter. The 360-010050-001 connector adapter is sold separately.
For Ordering Information, Call:
ETHERNET CONTROLLER — The 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859
E-mail: info@vmic.com Web Address: www.vmic.com
VMIVME-7700 provides two front panel connections to
Copyright © May 2003 by VMIC
either 10BaseT or 100BaseTX LAN using two Intel
Specifications subject to change without notice.
82551ER Ethernet controllers. Standard RJ45 connectors
VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1
VMIVME-7700
A GE Fanuc Company
two micro DB-9 connectors located on the front panel. The Round Robin (RRS)
micro DB-9 connectors require two micro DB-9 to standard
Single Level (SGL)
DB-9 adapters, VMIC P/N 360-010050-001.
Priority (PRI)
PMC EXPANSION SITE — The VMIVME-7700 The system controller provides a SYSCLK driver,
provides one IEEE 1386.1, 5 V PCI mezzanine card (PMC) IACK* daisy-chain driver, and a VMEbus access timeout
expansion site. This expansion capability allows the timer. The system controller also provides an arbitration
addition of peripherals offered for PMC applications. The timeout if BBSY* is not seen within a specified period after
PMC site provides for standard I/O out the VMEbus front a BGOUT* signal is issued. This period is programmable
panel. An optional I/O connection to the VMEbus P2 for 16 or 256 µs.
connection can be provided.
VMEbus REQUESTER — The microprocessor can
KEYBOARD and MOUSE PORTS — The request and gain control of the bus using any of the VMEbus
VMIVME-7700 supports a PS/2 keyboard and mouse request lines (BR3* to BR0*) under software control. The
through the front panel. requester can be programmed to operate in any of the
following modes:
HARDWARE RESET — A hardware reset switch is
Release-On-Request (ROR)
accessible from the front panel.
Release-When-Done (RWD)
PROGRAMMABLE TIMER — The VMIVME-7700 VMEbus Capture and Hold (VCAP)
provides the user with two 16-bit timers and two 32-bit
timers. These timers are mapped in PCI memory space, are
MAILBOXES — The VMEbus interface provides four
completely software programmable and can generate PCI
32-bit mailboxes, which are accessible from both the
bus interrupts.
microprocessor and the VMEbus providing interprocessor
communication. The mailboxes have the ability to interrupt
WATCHDOG TIMER — The VMIVME-7700
the microprocessor when accessed by theVMEbus.
provides a software-programmable Watchdog timer. The
Watchdog timer is enabled under software control. Once the
INTERRUPT HANDLER — The interrupt handler
timer is enabled, software must access the timer within the
monitors, and can be programmed to respond to any or all
specified time period, or the output of the Watchdog timer
VMEbus IRQ* lines. All normal-process VMEbus-related
will reset the unit.
interrupts can be mapped to PCI INTA# or SERR#
interrupts. These include:
NONVOLATILE SRAM — The VMIVME-7700
Mailbox interrupts
provides 32 KB of nonvolatile SRAM. The contents of the
VMEbus interrupts
SRAM are preserved when +5 V power is interrupted or
removed from the unit.
VMEbus interrupter IACK cycle (acknowledgment
of VMIVME-7700 VMEbus-issued interrupts)
CMOS BATTERY — The VMIVME-7700 uses a
All error processing VMEbus-related interrupts can be
holder that permits field replacement of the CMOS battery.
mapped to PCI INTA# or SERR#. Note: PCI SERR#
A header and jumper allows the battery to be disconnected
initiates an SBC NMI. These include:
from the circuitry for long-term storage.
ACFAIL* interrupt
ANNUNCIATORS — Indicators for the board status,
BERR* interrupt
+5 V power good, are provided on the front panel. In
SYSFAIL* interrupt
addition, two indicators for the Ethernet adapter activity are
located on each RJ45 network connector.
The interrupt handler has a corresponding STATUS/ID
register for each IRQ* interrupt. Once the handler receives
THERMAL MANAGEMENT — The VMIVME-7700
an IRQ*, it requests the VMEbus and, once granted, it
utilizes a passive heat sink that relies on forced air cooling
performs an IACK cycle for that level. Once the IACK cycle
within the equipment rack at the specified flow rate. Please
is complete and the STATUS/ID is stored in the
refer to the environmental specifications for more
corresponding ID register, an appropriate interrupt status bit
information.
is set in an internal status register, and a PCI interrupt is
generated. The PCI interrupt can be mapped to PCI INTA#
VMEbus INTERFACE — The VMIVME-7700
or SERR#.
VMEbus interface is based on the Universe IID high
performance PCI-to-VMEbus interface from
INTERRUPTER — Interrupts can be issued under
Newbridge/Tundra.
software control on any or all of the seven VMEbus interrupt
lines (IRQ7* to IRQ1*). A common ID register is associated
SYSTEM CONTROLLER — The VMEbus system
with all interrupt lines. During the interrupt acknowledge
controller capabilities allow the board to operate as a slot 1
cycle, the interrupter issues the ID to the interrupt handler.
controller, or it can be disabled when another board is acting
The interrupter can be programmed to generate a PCI INTA#
as the system controller. The system controller may be
or SERR# interrupt when a VMEbus interrupt handler
programmed to provide the following modes of arbitration:
acknowledges a software-generated VMEbus interrupt.
2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859
VMIVME-7700
A GE Fanuc Company
BYTE SWAPPING — The Intel 80x86 family of BACK PANEL CONFIGURATION — The
processors uses little-endian format. To accommodate VMIVME-7700 provides support for external IDE disk drive
VMEbus modules that transfer data in big-endian format, and floppy drive through the VMEbus P2 backplane
such as the 680x0 processor family, the VMIVME-7700 connector and the VMIACC-0562 backplane adapter.
incorporates byte-swapping hardware. This provides
independent byte swapping for both the master and slave OPERATING SYSTEM AND SOFTWARE
interfaces. Both master and slave interface byte swapping are SUPPORT — The VMIVME-7700 provides embedded
under software control. The VMIVME-7700 supports high features beyond PC/AT functionality. These features are
throughput DMA transfers of bytes, words and longwords in supported by VMIC software products aimed at developers
both Master and Slave configurations. If endian conversion who are incorporating VMIC SBCs, I/O boards and
is not needed, we offer a special “bypass” mode that can be workstations into systems. The VMIVME-7700 supports a
®
used to further enhance throughput. (Not available for byte variety of operating systems including Microsoft Windows
® ® ®
transfers.) NT , Windows 2000, Windows XP, QNX, Linux and
®
VxWorks .
MASTER INTERFACE — MA32: MBLT32:
MBLT64 (A32:A24:A16:D32:D16:D8 (EO):BLT32) SPECIFICATIONS
The VMEbus master interface provides nine separate
memory windows into VMEbus resources. Each window
Single Slot 6U (4HP) Eurocard Form Factor:
has separate configuration registers for mapping PCI bus
Height 9.2 in. (233.4 mm)
transfers to the VMEbus (that is, PCI bus base address,
window size, VMEbus base address, VMEbus access type,
Depth 6.3 in. (160 mm)
VMEbus address/data size, etc.). The maximum/minimum
Thickness 0.8 in. (20.3 mm)
window sizes for the nine windows are as follows:
Window Minimum Size Maximum Size
0,4 4 KB 4 GB
Power Requirements:
1 to 3, 5 to 7 64 KB 4 GB
+5 VDC (±5 percent),
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