INTEL GD82551QM

82551QM Fast Ethernet Multifunction PCI/CardBus Controller Networking Silicon - 82551QM Datasheet Product Features  Enhanced IP Protocol Support — Improved dynamic transmit chaining with multiple priorities transmit queues — TCP, UDP, IPv4 Checksum Offload — Full pin compatibility with the 82559 and — Received Checksum Verification 82550 controllers  Quality of Service (QoS) — Backward compatible software to the 8255x — Multiple Priority Transmit Queues controller family (IPSec not supported)  Optimum Integration for Lowest Cost Solution — Full Duplex support at 10 and 100 Mbps — Integrated IEEE 802.3 10BASE-T and — IEEE 802.3u Auto-Negotiation support 100BASE-TX compatible PHY — 3 KB transmit and receive FIFOs — 32-bit PCI/CardBus master interface — Fast back-to-back transmission support with — Modem interface for combination solutions minimum interframe spacing — Integrated power management functions — IEEE 802.3x 100BASE-TX Flow Control 2 — Thin BGA 15mm package support  PHY detects polarity, MDI-X, and cable lengths. — Adaptive Technology Auto MDI/MDI-X crossover at all speeds  Low Power Features  XOR tree mode support — Advanced Power Management capabilities  Wired for Reduced Total Cost of Ownership — Low power 3.3 V device (TCO) — Efficient dynamic standby mode — Wired for Management support — Deep power down support — Integrated Alert Standard Format — Clock Run protocol support — ACPI and PCI Power Management standards  82551QM Enhancements compliance — Improved Bit Error Rate performance — Wake on “interesting” packets and link status change support — Integrated UNDI ROM support — Magic Packet* support — HWI support — Remote power up support — Deep power-down state power reduction 1  High Performance Networking Functions  Lead-free 196-pin Ball Grid Array (BGA). Devices that are lead-free are marked with a — Early release circled “e1” and have the product code: — 8255x controller family chained memory LUXXXXX. structure 1 This device is lead-free. That is, lead has not been intentionally added, but lead may still exist as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-banned materials, is available at: ftp://download.intel.com/design/packtech/ material_content_IC_Package.pdf#pagemode=bookmarks In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales Rerepresentative. 317803-004 Revision 4.0 Revision History Revision Revision Description Date Oct 2001 0.6 • Removed references to IPSec support and changed description of FLA1/AUXPWR to use a pull-up resistor if auxiliary power is present, else leave it disconnected. • Changed description of VCCR to show connecting it directly to main 3.3V supply and reduced text describing bus operations. • Reduced PHY functional description to overview level and reorganized manageability section, adding ASF text. Added 0Fh as Revision ID and added targeted Icc specs. Dec 2001 1.0 • Added description for No Connect pins and corrected typographical errors. Apr 2002 2.0 Changed document status to Intel Confidential. Mar 2003 2.1 • Removed document status and removed references to MDI/MDI-X feature, which is not sup- ported by the 82551QM Jun 2003 3.0 • Added information for the 82551IT. Oct 2003 3.1 • Corrected operating temperature range in specifications to 0° to 70° C. Mar 2004 3.11 • Added operating temperature reference to Section 1.1 Oct 2004 3.2 • Removed operating temperature reference to Section 1.1. • Added references to MDI/MDI-X feature, which is now supported by the 82551QM and removed information for the 82551IT. Nov 2004 3.3 • Updated the section describing “Multiple Priority Transmit Queues”. • Added information about migrating from a 2-layer 0.36 mm wide-trace substrate to a 2-layer 0.32 mm wide-trace substrate. Refer to the section on Package and Pinout Information. • Added statement that no changes to existing soldering processes are needed for the 2-layer 0.32 mm wide-trace substrate change in the section describing “Package Information”. Jan 2005 3.4 • Added a note for PHY signals RBIAS100 and RBIAS10 to Table 9. Apr 2006 3.5 • Changed case temperature specification to “0° C to 85° C”. Oct 2006 3.6 • Added Figure 31 “196 PBGA Package Pad Detail”. The figure shows solder resist opening and metal diameter dimensions. July 2007 3.7 • Added Section 15 “Reference Schematics”, updated Section 12.1 (changed Tcase to ambient) and added ordering information to Section 1.4. Sept 2007 3.8 • Updated Figures 34 and 35. Added Digital I/O and Crystal Input One (X1) Characteristics (Tables 70 and 71). Updated Section 5.8.4. Mar 2008 3.9 • Updated Figure 35: changed TEST pull down resistor value (62 K to 1 K). Nov 2008 4.0 • Updated Table 9 (X1 and X2 pin descriptions). • Updated Tables 70 and 71 (Digital I/O and crystal input one (X1) characteristics). Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 82551QM may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call in North America 1-800-548-4725, Europe 44-0-1793-431-155, France 44-0-1793-421-777, Germany 44-0-1793-421-333, other Countries 708- 296-9333 ® Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. Copyright © 2008, Intel Corporation. * Other product and corporate names may be trademarks of other companies and are used only for explanation and to the owners’ benefit, without intent to infringe. ii Datasheet Networking Silicon — 82551QM Contents 1.0 Introduction.........................................................................................................................1 1.1 Overview ...............................................................................................................1 1.2 Byte Ordering ........................................................................................................1 1.3 References............................................................................................................1 1.4 Product Ordering Codes........................................................................................2 2.0 Architectural Overview .......................................................................................................3 2.1 Parallel Subsystem Overview................................................................................3 2.2 FIFO Subsystem Overview ...................................................................................4 2.3 Manageability Subsystem Overview .....................................................................4 2.4 10/100 Mbps Serial CSMA/CD Unit Overview ......................................................4 2.5 10/100 Mbps Physical Layer Unit..........................................................................4 3.0 Performance Enhancements..............................................................................................5 3.1 Multiple Priority Transmit Queues .........................................................................5 3.2 Early Release........................................................................................................5 3.3 Hardware Integrity Support ...................................................................................6 3.4 Management Data Interface MDI/MDI-X Feature..................................................6 4.0 Signal Descriptions.............................................................................................................7 4.1 Signal Type Definitions .........................................................................................7 4.2 PCI Bus and CardBus Interface Signals ...............................................................8 4.2.1 Address and Data Signals .......................................................................8 4.2.2 Interface Control Signals .........................................................................8 4.2.3 System and Power Management Signals ...............................................9 4.3 Local Memory Interface Signals..........................................................................10 4.4 System Management Bus (SMB) Interface Signals ...........................................12 4.5 Test Port Signals ................................................................................................13 4.6 PHY Signals .......................................................................................................13 4.7 Power and Ground Signals .................................................................................14 5.0 Media Access Control Functional Description..................................................................15 5.1 Device Initialization..............................................................................................15 5.1.1 Initialization Effects.................................................................................15 5.1.2 Initialization Effects on TCO Functionality..............................................16 5.2 PCI and CardBus Interface .................................................................................16 5.2.1 Bus Operations.......................................................................................16 5.2.2 Clock Run Signal....................................................................................25 5.2.3 Power Management Event and Card Status Change Signals................25 5.3 PCI Power Management .....................................................................................26 5.3.1 Power States ..........................................................................................26 5.3.2 Wake-up Events .....................................................................................30 5.4 CardBus Power Management .............................................................................31 5.5 Wake on LAN (Preboot Wake-up).......................................................................31 5.6 Parallel Flash/Modem Interface...........................................................................32 5.7 Serial EEPROM Interface....................................................................................33 5.8 10/100 Mbps CSMA/CD Unit...............................................................................35 Datasheet iii 82551QM — Networking Silicon 5.8.1 Full Duplex .............................................................................................35 5.8.2 Flow Control ...........................................................................................36 5.8.3 Address Filtering Modifications ..............................................................36 5.8.4 VLAN Support ........................................................................................36 5.9 Media Independent Interface (MII) Management Interface .................................36 6.0 Physical Layer Functional Description .............................................................................37 6.1 100BASE-TX PHY Unit .......................................................................................37 6.1.1 100BASE-TX Transmit Clock Generation ..............................................37 6.1.2 100BASE-TX Transmit Blocks ...............................................................37 6.1.3 100BASE-TX Receive Blocks ................................................................37 6.1.4 100BASE-TX Link Integrity Auto-Negotiation.........................................38 6.2 10BASE-T PHY Functions ..................................................................................38 6.2.1 10BASE-T Transmit Clock Generation...................................................38 6.2.2 10BASE-T Transmit Blocks....................................................................38 6.2.3 10BASE-T Receive Blocks.....................................................................38 6.2.4 10BASE-T Link Integrity and Full Duplex...............................................39 6.3 Auto-Negotiation .................................................................................................39 6.3.1 Description .............................................................................................39 6.3.2 Parallel Detect and Auto-Negotiation .....................................................39 6.4 LED Description ..................................................................................................40 7.0 Modem Functionality ........................................................................................................43 7.1 PCI Address Mapping to the Modem ..................................................................43 7.2 Modem Read and Write Cycles ..........................................................................43 7.3 Modem and Preboot eXtension Environment Coexistence.................................43 7.3.1 Programming Details..............................................................................44 7.3.2 Support Circuitry ....................................................................................44 8.0 Manageability Functionality..............................................................................................45 8.1 Alert Standard Format.........................................................................................45 8.2 Heartbeat ............................................................................................................46 8.3 Ping/Pong............................................................................................................46 8.4 Watchdog ............................................................................................................47 8.5 Advanced Power Management Modes ...............................................................47 8.6 Polling .................................................................................................................47 8.7 Link Loss .............................................................................................................47 8.8 Acknowledge.......................................................................................................47 9.0 Configuration Registers....................................................................................................49 9.1 Function 0: LAN (Ethernet) PCI Configuration Space.........................................49 9.1.1 PCI Vendor ID and Device ID Registers ................................................49 9.1.2 PCI Command Register .........................................................................50 9.1.3 PCI Status Register................................................................................51 9.1.4 PCI Revision ID Register........................................................................52 9.1.5 PCI Class Code Register .......................................................................52 9.1.6 PCI Cache Line Size Register................................................................53 9.1.7 PCI Latency Timer .................................................................................53 9.1.8 PCI Header Type ...................................................................................53 9.1.9 PCI Base Address Registers..................................................................53 9.1.10 Base Address Registry Summary ..........................................................56 iv Datasheet Networking Silicon — 82551QM 9.1.11 CardBus Card Information Structure (CIS) Pointer ................................56 9.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers.......................56 9.1.13 Capability Pointer ...................................................................................57 9.1.14 Interrupt Line Register............................................................................57 9.1.15 Interrupt Pin Register .............................................................................57 9.1.16 Minimum Grant Register ........................................................................58 9.1.17 Maximum Latency Register....................................................................58 9.1.18 Capability ID Register.............................................................................58 9.1.19 Next Item Pointer....................................................................................58 9.1.20 Power Management Capabilities Register .............................................58 9.1.21 Power Management Control/Status Register (PMCSR).........................59 9.1.22 Data Register .........................................................................................60 9.2 Function 1: Modem PCI Configuration Space.....................................................60 9.2.1 Modem Configuration ID Register ..........................................................61 9.2.2 Modem Command Register ...................................................................61 9.2.3 Modem Status Register..........................................................................62 9.2.4 Modem Revision ID Register..................................................................62 9.2.5 Modem Header Type Register ...............................................................62 9.2.6 Modem I/O Base Address Register........................................................62 9.2.7 Modem Memory Base Address Register................................................63 9.2.8 Modem CardBus CIS Pointer .................................................................63 9.2.9 Modem Subsystem Vendor ID Register .................................................63 9.2.10 Modem Subsystem ID Register..............................................................63 9.2.11 Modem Capabilities Pointer ...................................................................63 9.2.12 Modem Interrupt Register.......................................................................63 9.2.13 Modem Power Management Capabilities Register ................................63 9.2.14 Modem Power Management Control/Status Register ............................64 9.2.15 Modem Data Register ............................................................................64 9.2.16 Modem Support in PCI Mode .................................................................64 10.0 Control/Status Registers ..................................................................................................65 10.1 LAN (Ethernet) Control/Status Registers ............................................................65 10.1.1 System Control Block Status Word ........................................................66 10.1.2 System Control Block Command Word..................................................67 10.1.3 System Control Block General Pointer...................................................67 10.1.4 PORT .....................................................................................................67 10.1.5 Flash Control Register............................................................................67 10.1.6 EEPROM Control Register.....................................................................68 10.1.7 Management Data Interface Control Register........................................68 10.1.8 Receive Direct Memory Access Byte Count...........................................68 10.1.9 Flow Control Register.............................................................................68 10.1.10 Power Management Driver Register ......................................................69 10.1.11 General Control Register........................................................................70 10.1.12 General Status Register .........................................................................70 10.1.13 Ethernet Card Status Change Registers ................................................70 10.2 Statistical Counters .............................................................................................73 10.3 Modem Control/Status Registers ........................................................................75 10.3.1 Modem Base Memory Addressing .........................................................76 10.3.2 Modem Base I/O Addressing .................................................................76 10.3.3 Modem CardBus CSTCHG Registers ....................................................76 Datasheet v 82551QM — Networking Silicon 11.0 PHY Unit Registers ..........................................................................................................79 11.1 MDI Registers 0 - 7 .............................................................................................79 11.1.1 Register 0: Control Register ..................................................................79 11.1.2 Register 1: Status Register ...................................................................80 11.1.3 Register 2: PHY Identifier Register .......................................................81 11.1.4 Register 3: PHY Identifier Register .......................................................81 11.1.5 Register 4: Auto-Negotiation Advertisement Register ...........................81 11.1.6 Register 5: Auto-Negotiation Link Partner Ability Register ....................82 11.1.7 Register 6: Auto-Negotiation Expansion Register .................................82 11.2 MDI Registers 8 - 15 ...........................................................................................82 11.3 MDI Register 16 - 31 ...........................................................................................83 11.3.1 Register 16: PHY Unit Status and Control Register ..............................83 11.3.2 Register 17: PHY Unit Special Control Register ...................................83 11.3.3 Register 18: PHY Address Register.......................................................84 11.3.4 Register 19: 100BASE-TX Receive False Carrier Counter ...................84 11.3.5 Register 20: 100BASE-TX Receive Disconnect Counter ......................85 11.3.6 Register 21: 100BASE-TX Receive Error Frame Counter ....................85 11.3.7 Register 22: Receive Symbol Error Counter .........................................85 11.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Coun- ter 85 11.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter .............85 11.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter .....................86 11.3.11 Register 26: Equalizer Control and Status Register ..............................86 11.3.12 Register 27: PHY Unit Special Control Register ...................................86 11.3.13 Register 28: MDI/MDI-X Control Register ..............................................87 11.3.14 Register 29: Hardware Integrity Control Register ..................................87 12.0 Electrical and Timing Specifications.................................................................................89 12.1 Absolute Maximum Ratings ................................................................................89 12.2 DC Specifications ...............................................................................................90 12.3 AC Specifications ................................................................................................93 12.4 Timing Specifications ..........................................................................................94 12.4.1 Clocks Specifications .............................................................................94 12.4.2 Timing Parameters.................................................................................95 13.0 82551QM Test Port Functionality...................................................................................103 13.1 Introduction .......................................................................................................103 13.2 Test Function Description .................................................................................103 13.2.1 Tristate .................................................................................................103 13.2.2 XOR Tree .............................................................................................104 14.0 Package and Pinout Information ....................................................................................107 14.1 Package Information .........................................................................................107 14.2 Pinout Information .............................................................................................109 14.2.1 Pin Assignments .................................................................................109 14.2.2 Ball Grid Array Diagram .......................................................................111 15.0 Reference Schematics...................................................................................................112 vi Datasheet Networking Silicon — 82551QM 1.0 Introduction ® This datasheet is applicable to the Intel 82551QM Fast Ethernet Multifunction PCI/CardBus Controller, a member of the 8255x Fast Ethernet Controller family. 1.1 Overview The 82551QM is an evolutionary addition to Intel’s family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load for operations such as Large Send. Its optimized 32-bit interface and efficient scatter-gather bus mastering capabilities enable the 82551QM to perform high speed data transfers over the PCI bus or CardBus. This capability accelerates the processing of high level commands and operations, which lowers CPU utilization. Its architecture enables data to flow efficiently from the bus interface unit to the 3 KB Transmit and Receive FIFOs, providing the perfect balance between the wire and system bus. In addition, multiple priority queues are provided to prevent data underruns and overruns. The 82551QM also integrates advanced manageability features into one component. It includes support for the Alerting Standards Forum (ASF) alert standard format bi-directional alerting and provides a Total Cost of Ownership (TCO) interface that can be used with bus management controllers. ASF sensor polling is supported, as well as remote control capabilities. The 82551QM embeds UNDI (Universal NIC Driver Interface) code, allowing it to support Preboot eXecutable Environment (PXE) without the use of additional external ROM. The 82551QM includes both a MAC and PHY. In also has a simple interface to the analog front end, which allows cost effective designs requiring minimal board real estate. The 82551QM is pin compatible with the 82550 and 82559 family of controllers and is offered with software that provides backwards compatibility with previous 8255x controllers. 1.2 Byte Ordering TCP and IP Internet Engineering Task Force (IETF) Request for Comments (RFCs) and literature use big endian (BE) byte ordering. This document uses big endian ordering for all IP and TCP frame formats. However, little endian byte ordering is used for referencing 82551QM memory resident structures and internal structures. 1.3 References The following documents may provide further information on topics discussed in this document. • 10/100 Mbit Ethernet Controller Family Software Developer’s Manual. Intel Corporation. • Advanced Configuration and Power Interface Specification, Revision 1.0. Intel Corporation, Microsoft Corporation, and Toshiba. • IEEE 802.3x and 802.1y Standards. Datasheet 1 82551QM — Networking Silicon • Network Device Class Power Management Reference Specification, Revision 1.0a. AMD, Inc. and Microsoft Corporation. • System Management Bus (SMB) Specification. Smart Battery System Special Interest Group (SIG). • 82551QM/ER/IT EEPROM Map and Programming Information. Intel Corporation • 82562EZ(EX)/82551QM & 82540EM Combined Footprint LOM Design Guide. Intel Corporation 1.4 Product Ordering Codes The product ordering code for the 82551QM is: • GD82551QM (Leaded) • LU82551QM (Lead Free) Device Stepping MM Number Specification Notes LU82551QM A0 860610 S L7G5 Production (Tape and Reel) LU82551QM A0 860611 Production (Tray) GD82551QM A0 844662 Production (Tray) GD82551QM A0 844663 S L66W Production (Tape and Reel) GRP1LINE1 GRP1LINE2 GRP1LINE3 GRP1LINE4 BSMC PIN 1 BSMC = Bottom-Side Mark Code Figure 1. 82551QM Component Markings Legend: GRP1LINE1 - 82551QM GRP1LINE2 - (FPO) GRP1LINE3 - Blank GRP1LINE4 - (M) (C) ‘01 (leaded); (M) (C) ‘01 (e1) (lead free) 2 Datasheet Networking Silicon — 82551QM 2.0 Architectural Overview ® The Intel 82551QM is divided into five main subsystems: a parallel subsystem, a FIFO subsystem, the manageability subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/100 Mbps physical layer (PHY) unit. 2.1 Parallel Subsystem Overview The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ Flash/EEPROM/Modem interface. The parallel subsystem also interfaces to the FIFO subsystem, passing data (such as transmit, receive, and configuration data) and command and status parameters between these two blocks. The dual function modem and PCI bus master interface provides a complete glueless interface to a PCI bus and is compliant with the PCI Bus Specification, Revision 2.2. The 82551QM provides 32 bits of addressing and data, as well as the PCI control interface. As a PCI target, it conforms to the PCI configuration scheme, which allows all accesses to the 82551QM to be automatically mapped into free memory and I/O space upon initialization of a PCI system. When transmit and receive data is processed, the 82551QM operates as a master on the PCI bus, initiating zero wait state transfers. The 82551QM Control/Status Register Block is part of the PCI target element. The Control/Status Register block consists of the following 82551QM internal control registers: System Control Block (SCB), PORT, Flash Control, EEPROM Control, Modem Control and Management Data Interface (MDI) Control. An embedded micromachine consisting of independent transmit and receive processing units allow the 82551QM to execute commands and receive incoming frames with no real time CPU intervention. The 82551QM contains a multiplexed interface to connect an external serial EEPROM and Flash memory and modem. The Flash interface, which can also be used to connect to any standard 8-bit device, provides up to 128 KB of addressing to the Flash. Both read and write accesses are supported. The Flash can be used for remote boot functions, network statistical and diagnostics functions, and management functions. The Flash is mapped into host system memory (anywhere within the 32-bit memory address space) for software accesses. It is also mapped into an available boot expansion ROM location during boot time of the system. More information on the Flash interface is detailed in Section 5.6, “Parallel Flash/Modem Interface”. The serial EEPROM is used to store relevant information for a LAN connection such as node address, as well as board manufacturing and configuration information. Both read and write accesses to the EEPROM are supported by the 82551QM. Information on the EEPROM interface is detailed in Section 5.7, “Serial EEPROM Interface”. The modem interface uses an ISA-like signal and is described in more detail in Section 7.0, “Modem Functionality”. Datasheet 3 82551QM — Networking Silicon 2.2 FIFO Subsystem Overview The 82551QM FIFO subsystem consists of independent 3 KB transmit and receive FIFOs. Each FIFO provides a temporary buffer for frames as they are transmitted or received. Transmit frames queued within the transmit FIFO allow back-to-back transmission within the minimum Interframe Spacing (IFS). The FIFOs allow the 82551QM to withstand long PCI bus latencies without losing incoming data. Additional attributes of the FIFOs that enhance performance and functionality are: • Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits are being performed. • Extended PCI zero wait state burst accesses to and from the 82551QM for both transmit and receive FIFOs • Efficient re-transmission of data directly from the transmit FIFO when physical or data link errors (collision detection or data underrun) are encountered, increasing performance by eliminating the need to re-access the data from host memory • Automatic discard of incoming runt receive frames 2.3 Manageability Subsystem Overview The 82551QM’s Manageability subsystem supports bi-directional ASF, version 1.0. In addition, it provides a Total Cost of Ownership (TCO) interface that enables connection with alerting and management controllers such as the Intelligent Platform Management Interface (IPMI) solutions and Baseboard Management Controllers (BMCs). 2.4 10/100 Mbps Serial CSMA/CD Unit Overview The 82551QM’s CSMA/CD unit allows it to be connected to a 10 or 100 Mbps Ethernet network at half or full duplex. The CSMA/CD unit performs all of the functions of the 802.3 protocol such as frame formatting, frame stripping, collision handling, deferral to link traffic, etc. 2.5 10/100 Mbps Physical Layer Unit The integrated Physical Layer (PHY) unit of the 82551QM allows connection to either a 10 or 100 Mbps Ethernet network. The PHY supports Auto-Negotiation for 100BASE-TX Full Duplex, 100BASE-TX Half Duplex, 10BASE-T Full Duplex, and 10BASE-T Half Duplex. Three LED pins indicate link status, network activity, and speed. 4 Datasheet Networking Silicon — 82551QM 3.0 Performance Enhancements All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551QM has been designed to provide improved networking throughput. Performance is limited to the system’s ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. System bottlenecks prevent optimal performance in typical operating conditions. Thus, to help alleviate these issues, Network Operating System (NOS) vendors are establishing normalized off- load specifications. These specifications define the types of off-load support required by the OS and interface between the network drivers. The 82551QM provides support for these initiatives and enables an improvement in platform network efficiency. With the pervasiveness of Internet Protocols, the off-load capabilities have focused on improving IP efficiency. As part of this effort, the 82551QM includes support for Multiple Priority Transmit Queues. 3.1 Multiple Priority Transmit Queues The 82551QM supports two queues: High Priority Queue (HPQ) and Low Priority Queue (LPQ). The 82551QM provides a method for the driver to modify the HPQ while processing data. A new read only register is defined in the Control/Status Register (CSR) that enables the driver to change the transmit priority of elements within the HPQ. When software reads this register, the address of the next Command Block to be processed by the 82551QM on the HPQ is returned. After reading this register, software can freely modify the next Command Block (for example, overwrite it with a different Command Block) and any subsequent Command Block, without any conflict with the 82551QM. Note: The 82551QM Windows* driver supports the Command Block Pointer register (in the CSR). 3.2 Early Release Like the 82558, 82559 and 82550, the 82551QM supports a 3 KB transmit FIFO. The 82551QM provides a transmit FIFO enhancement called “early release” that effectively increases the amount of free capacity in the transmit FIFO. The enabling of early release is controlled through configuration space and occurs when the following conditions are met: 1. The transmitted frame is the oldest one in the queue (in other words, it is located at the head of the queue). 2. The transmitted frame has been completely transferred to the XMT-SRAM and processed (for example, XSUM). Large frames (greater than 3 KB) are never candidates for an early release. 3. When the preemptive queue mechanism is on, a frame which satisfies condition 2 may not satisfy condition 1 and therefore will not benefit from an early release. 4. More than 128 bytes have already been transferred to the XMT-SYNC-FIFO. This condition guarantees that at least one slot time elapsed (collision window). Datasheet 5 82551QM — Networking Silicon 3.3 Hardware Integrity Support Cabling problems are a common cause for network downtime situations. Hardware Integrity (HWI) can help reduce this by locating cabling problems, which reduces Total Cost of Ownership (TCO). It uses transmission line theory to measure the arrival time and electrical characteristics of the wave reflected from an incident test wave launched on the media. With these measurements, opens, shorts, and degraded cable quality can be located along the wire. HWI is controlled and activated by software. The Hardware Integrity Control, register 29 of the MDI Registers, is used for activating HWI (Section 11.3.14, “Register 29: Hardware Integrity Control Register”). 3.4 Management Data Interface MDI/MDI-X Feature The 82551QM controller MDI/MDI-X feature provides the ability to automatically detect the required cable connection type and configure the controller-side MAU to the cable type. This feature effectively allows all properly wired Ethernet cables usable with any Ethernet device to be connected to the 82551QM without any additional external logic. This advanced feature enables auto-correction of incorrect cabling with respect to cross-over versus straight-through cables. The 82551QM can identify the cable connection type and adjust its MDI port to the cable by switching between the TD and RD pairs. The auto-switching is done prior to the start of the hardware auto negotiation algorithm. In a standard straight-through RJ-45 port configuration, the transmit pair is on contacts 1 and 2, and the receive pair on contacts 3 and 6. These are defined by Clause 23.7.1 of the IEEE 802.3u standard. Table 1 lists the connections for both straight-through and cross-over RJ-45 ports for comparison. Table 1. RJ-45 Connections RJ-45 Straight-Through Cross-Over MDIX a b Contact MDI Signal Signal 1 TD+ RD+ 2 TD- RD- 3RD+ TD+ 4 Not Used Not Used 5 Not Used Not Used 6RD- TD- 7 Not Used Not Used 8 Not Used Not Used a. Straight-through connections used on DTE applications. b. Cross-over connections used on Hub and Switch applications. 6 Datasheet Networking Silicon — 82551QM 4.0 Signal Descriptions 4.1 Signal Type Definitions Table 2. Signal Type Descriptions Type Name Description IN Input The input pin is a standard input only signal. The output pin is a Totem Pole Output pin and is a standard OUT Output active driver. TS Tri-State The tri-state pin is a bidirectional, input/output pin. The sustained tri-state pin is an active low tri-state signal owned and driven by one agent at a time. The agent asserting the STS STS Sustained Tri-State pin low must drive it high at least one clock cycle before floating the pin. A new agent can only assert an STS signal low one clock cycle after it has been tri-stated by the previous owner. The open drain pin allows multiple devices to share this signal OD Open Drain as a wired-OR. AI Analog Input The analog input pin is used for analog input signals. AO Analog Output The analog output pin is used for analog output signals. B Bias The bias pin is an input bias. Digital Power DPS Digital power or ground for the device. Supply Analog Power APS Analog power or ground for the device. Supply Datasheet 7 82551QM — Networking Silicon 4.2 PCI Bus and CardBus Interface Signals 4.2.1 Address and Data Signals Table 3. Address and Data Signals Symbol Type Name and Function Address and Data. The address and data lines are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. During the address phase, the address and data lines contain the 32-bit physical address. For I/O, AD[31:0] TS this is a byte address; for configuration and memory, it is a Dword address. The 82551QM uses little-endian byte ordering (in other words, AD[31:24] contain the most significant byte and AD[7:0] contain the least significant byte). During the data phases, the address and data lines contain data. Command and Byte Enable. The bus command and byte enable signals are multiplexed on the same PCI pins. During the address phase, the C/BE# lines define the bus command. During the data C/BE#[3:0] TS phase, the C/BE# lines are used as Byte Enables. The Byte Enables are valid for the entire data phase and determine which byte lanes carry meaningful data. Parity. Parity is even across AD[31:0] and C/BE#[3:0] lines. It is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write PAR TS transaction or TRDY# is asserted on a read transaction.Once PAR is valid, it remains valid until one clock after the completion of the current data phase. The master drives PAR for address and write data phases; and the target, for read data phases. 4.2.2 Interface Control Signals Table 4. Interface Control Signals Symbol Type Name and Function Cycle Frame. The cycle frame signal is driven by the current master to indicate the beginning and duration of a transaction. FRAME# is FRAME# STS asserted to indicate the start of a transaction and de-asserted during the final data phase. Initiator Ready. The initiator ready signal indicates the bus master’s ability to complete the current data phase and is used in conjunction IRDY# STS with the target ready (TRDY#) signal. A data phase is completed on any clock cycle where both IRDY# and TRDY# are sampled asserted (low) simultaneously. Target Ready. The target ready signal indicates the selected device’s ability to complete the current data phase and is used in conjunction TRDY# STS with the initiator ready (IRDY#) signal. A data phase is completed on any clock cycle where both IRDY# and TRDY# are sampled asserted (low) simultaneously. Stop. The stop signal is driven by the target to indicate to the initiator that it wishes to stop the current transaction. As a bus slave, STOP# is STOP# STS driven by the 82551QM to inform the bus master to stop the current transaction. As a bus master, STOP# is received by the 82551QM to stop the current transaction. 8 Datasheet Networking Silicon — 82551QM Table 4. Interface Control Signals Symbol Type Name and Function Initialization Device Select. The initialization device select signal is used by the 82551QM as a chip select during PCI configuration read IDSEL IN and write transactions. This signal is provided by the host in PCI systems. In a CardBus system, this pin should not be connected. Device Select. The device select signal is asserted by the target once it has detected its address. As a bus master, the DEVSEL# is an input signal to the 82551QM indicating whether any device on the bus has DEVSEL# STS been selected. As a bus slave, the 82551QM asserts DEVSEL# to indicate that it has decoded its address as the target of the current transaction. Request. The request signal indicates to the bus arbiter that the REQ# TS 82551QM desires use of the bus. This is a point-to-point signal and every bus master has its own REQ#. Grant. The grant signal is asserted by the bus arbiter and indicates to GNT# IN the 82551QM that access to the bus has been granted. This is a point- to-point signal and every master has its own GNT#. Interrupt A. The interrupt A signal is used to request an interrupt by INTA# OD the 82551QM. This is an active low, level-triggered interrupt signal. System Error. The system error signal is used to report address SERR# OD parity errors. When an error is detected, SERR# is driven low for a single PCI clock. Parity Error. The parity error signal is used to report data parity errors during all PCI transactions except a Special Cycle. The parity error pin is asserted two clock cycles after the error was detected by the device PERR# STS receiving data. The minimum duration of PERR# is one clock for each data phase where an error is detected. A device cannot report a parity error until it has claimed the access by asserting DEVSEL# and completed a data phase. 4.2.3 System and Power Management Signals Table 5. System and Power Management Signals Symbol Type Name and Function Clock. The Clock signal provides the timing for all PCI transactions and is an input signal to every PCI device. The 82551QM requires a CLK IN PCI Clock signal (frequency greater than or equal to 16 MHz) for nominal operation. The 82551QM supports Clock signal suspension using the Clock Run protocol. Clock Run. The Clock Run signal is used by the system to pause or slow down the PCI Clock signal. It is used by the 82551QM to enable IN/OUT CLK_RUN# or disable suspension of the PCI Clock signal or restart of the PCI OD clock. When the Clock Run signal is not used, this pin should be connected to an external pull-down resistor. Reset. The PCI Reset pin is used to place PCI registers, sequencers, and signals into a consistent state. When RST# is asserted, the RST# IN 82551QM ignores other PCI signals and all PCI output signals will be tristated. The PCI Reset pin should be pulled high to the main digital power supply. Power Management Event. The Power Management Event signal PME# OD indicates that a power management event has occurred in a PCI bus system. Datasheet 9 82551QM — Networking Silicon Table 5. System and Power Management Signals Symbol Type Name and Function Card Status Change/Wake on LAN*. This pin is multiplexed to provide Card Status Change or Wake on LAN signals. In a CardBus system, it is used as the Card Status Change output signal and is an CSTSCHG/ OUT asynchronous signal to the Clock signal. It indicates that a power WOL management event has occurred in a CardBus system. In a PCI system, it is used as the WOL pin and provides a positive pulse of approximately 52 ms upon detection of an incoming Magic Packet*. Isolate. The Isolate pin is used to isolate the 82551QM from the PCI bus. It also provides PCI Reset pin functionality. When Isolate is active ISOLATE# IN (low), the 82551QM does not drive its PCI outputs (except PME# and CSTSCHG) or sample its PCI inputs (including CLK and RST#). The ISOLATE# pin should be driven by the PCI Reset signal. Alternate Reset. The Alternate Reset pin is used to reset the ALTRST# IN 82551QM on power-up. The Alternate Reset signal should be pulled high to the main digital power supply. Voltage Input/Output. The VIO pin is the voltage bias pin and should B be connected to a 5 V supply in a 5 V PCI signaling environment and a VIO 3.3 V supply in 3.3 V signaling environment. For CardBus systems, it IN should be connected to the main digital power supply. 4.3 Local Memory Interface Signals Note: All unused Flash Address and Data pins MUST be left floating. Some of these pins have undocumented test functionality and can cause unpredictable behavior if they are unnecessarily connected to a pull-up or pull-down resistor. Table 6. Local Memory Interface Signals Symbol Type Name and Function Flash/Modem Data Input/Output. These pins are used for Flash/ FLD7:0 IN/OUT Modem data interface. These pins should be left floating if the Flash and modem are not used. Flash Address 16/25 MHz Clock. This multiplexed pin is controlled by the status of the Flash Address 7 (FLA7) pin. If FLA7 is left floating, FLA16/ IN/OUT this pin is used as FLA16; otherwise, if FLA7 is connected to a pull-up CLK25 resistor, this pin is used as a 25 MHz clock output. This pin should be left floating if the Flash and the CLK25 functionality are not used. Flash Address 15/EEPROM Data Output. During Flash accesses, this multiplexed pin acts as the Flash Address 15 output signal. During FLA15/EESK OUT EEPROM accesses, it acts as the serial shift clock output to the EEPROM. Flash Address 14/EEPROM Data Output. During Flash accesses, FLA14/ this multiplexed pin acts as the Flash Address 14 output signal. During IN/OUT EEDO EEPROM accesses, this pin accepts serial input data from the EEPROM Data Output pin. Flash Address 13/EEPROM Data Input. During Flash accesses, this multiplexed pin acts as the Flash Address 13 output signal. During FLA13/EEDI OUT EEPROM accesses, this pin provides serial output data to the EEPROM Data Input pin. 10 Datasheet Networking Silicon — 82551QM Table 6. Local Memory Interface Signals Symbol Type Name and Function Flash Address 12/Modem Central Site Mode. This multiplexed pin acts as the Flash Address 12 output signal in a non-modem card. If FLA12/ modem is enabled, it is used as an output signal to the modem. It is IN/OUT MCNTSM# either floated by default or driven low by the Modem System Control Registers. This pin should be left floating if Flash and modem functionality are not used. Flash Address 11/Modem Interrupt. This multiplexed pin acts as the Flash Address 11 output signal in a non-modem card. If modem is FLA11/MINT IN/OUT enabled, it is used as the Modem Interrupt input signal. This pin should be left floating if Flash and modem functionality are not used. Flash Address 10/Modem Ring. This multiplexed pin acts as the FLA10/ Flash Address 10 output signal in a non-modem card. If modem is IN/OUT MRING# enabled, it is used as the Modem Ring input signal. This pin should be left floating if Flash and modem functionality are not used. Flash Address 9/Modem Reset. This multiplexed pin acts as the Flash Address 9 output signal in a non-modem card. If modem is FLA9/MRST IN/OUT enabled, it acts as the Modem Reset signal with an active high output. This pin should be left floating if Flash and modem functionality are not used. Flash Address 8/ISA Input/Output Channel Ready. This multiplexed pin acts as the Flash Address 8 output signal in a non- FLA8/ IN/OUT modem card. If modem is enabled, it is used as the ISA IOCHRDY IOCHRDY input signal. This pin should be left floating if Flash and modem functionality are not used. Flash Address 7/Clock Enable. This multiplexed pin acts as the Flash Address 7 output signal during nominal operation. When the power-on reset of the 82551QM is active, this pin acts as input control FLA7/ over the FLA 16/CLK25 output signal. If the FLA 7/CLKEN pin is IN/OUT CLKEN connected to a pull-up resistor (3.3 K ), a 25 MHz clock signal is provided on the FLA16/CLK25 output; otherwise, it is used as FLA16 output. For systems that do not use the 25 MHz clock output or Flash, this pin should be left floating. Flash Address 6:2. These pins are used as Flash address outputs. If the modem is enabled, these pins carry modem address bits 6:2. FLA6:2 OUT These pins should be left floating if the Flash and modem are not used. Flash Address 1/Auxiliary Power. This multiplexed pin acts as the Flash Address 1 output signal during nominal operation. If the modem is enabled, this pin carries modem address bit 1. When the power-on FLA1/ TS reset of the 82551QM is active (low), it acts as the power supply AUXPWR indicator. If the 82551QM is fed by auxiliary power, it should be connected to VCC through a pull-up resistor (3.3 K ). Otherwise, this pin should be left floating. Flash Address 0/PCI Mode. This multiplexed pin acts as the Flash Address[0] output signal during nominal operation. If the modem is enabled, this pin carries modem address bit 0. When power-on reset FLA0/ of the 82551QM is active (low), it acts as the input system type. If the TS PCIMODE# 82551QM is used in a CardBus system, this pin should be connected to a pull-up resistor (3.3 K ); otherwise, the 82551QM considers the host as a PCI system. For PCI systems that do not use Flash or modem, this pin should be left floating. EEPROM Chip Select. The EEPROM Chip Select signal is used to EECS OUT assert chip select to the serial EEPROM. Datasheet 11 82551QM — Networking Silicon Table 6. Local Memory Interface Signals Symbol Type Name and Function Flash Chip Select. The Flash Chip Select pin provides an active low Flash or modem chip select signal. This signal in combination with the FLCS# OUT Modem Chip Select (MDMCS#) signal determines which device, Flash or modem, is being used. This pin should be left floating if Flash and modem functionality are not used. Flash Output Enable. This pin provides an active low output enable control (read) to the Flash memory. If the modem is enabled, this is an FLOE# OUT active low output enable (read) of the modem. This pin should be left floating if Flash and modem functionality are not used. Flash Write Enable. This pin provides an active low write enable control to the Flash memory. If the modem is enabled, this is an active FLWE# OUT low write enable to the modem. This pin should be left floating if Flash and modem functionality are not used. Modem Chip Select. This pin provides an active low modem chip select. When it is set to 0b, the Flash port is used as a modem port; MDMCS# OUT when 1b, a Flash port. This pin should be left floating if Flash and modem are not used. 4.4 System Management Bus (SMB) Interface Signals Table 7. System Management Bus (SMB) Interface Signals Symbol Type Name and Function IN Alert Bus Data. This signal is stable when the Alert Bus Clock signal is high. SMBDATA This open drain signal should be pulled high to V in all cases. OD CC Alert Bus Clock. This pin is used for the Alert Bus Clock signal. One clock IN SMBCLK pulse is generated for each data bit transferred. It is an open drain signal and OD should be pulled high to V in all cases. CC Bus Alert/Main Power Good. This is a multiplexed pin used as the Bus Alert pin and Main Power Good pin. As the Bus Alert pin, it is used as an SMB_ALERT#/ OD interrupt signal for a slave device on the Alert Bus. As the Main Power Good LAN_PWR_GOOD pin it indicates that the main power supply is stable. This pin must be pulled high to V if it is not connected. CC 12 Datasheet Networking Silicon — 82551QM 4.5 Test Port Signals Table 8. Test Port Signals Symbol Type Name and Function Test Port. If this input pin is high, the 82551QM enables the test port. TEST IN During nominal operation this pin should be connected to a pull-down resistor. TCK IN Test Port Clock. This pin is used for the Test Port Clock signal. Test Port Data Input. This pin is used for the Test Port Data Input TI IN signal. Test Port Execute Enable. This pin is used for the Test Port Execute TEXEC IN Enable signal. Test Port Data Output. This pin is used for the Test Port Data Output TO OUT signal. Note: These test port signals are not JTAG compatible. As a result, a BSDL file is not required. 4.6 PHY Signals Table 9. PHY Signals Symbol Type Name and Function Crystal Input One. X1 and X2 can be driven by an external 25 MHz X1 AI crystal. Otherwise, X1 may be driven by an external 3.3 V metal-oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. Crystal Input Two. X1 and X2 can be driven by an external 25 MHz X2 AO crystal. Otherwise, X1 may be driven by an external 3.3 V MOS level 25 MHz oscillator when X2 is left floating. Analog Twisted Pair Ethernet Transmit Differential Pair. These pins transmit the serial bit stream for transmission on the Unshielded TDP Twisted Pair (UTP) cable. The current-driven differential driver can be AO two-level (10BASE-T) or three-level (100BASE-TX) signals depending TDN on the mode of operation. These signals interface directly with an isolation transformer. Analog Twisted Pair Ethernet Receive Differential Pair. These pins RDP receive the serial bit stream from the isolation transformer. The bit AI stream can be two-level (10BASE-T) or three-level (100BASE-TX) RDN signals depending on the mode of operation. Activity LED. The Activity LED pin indicates either transmit or receive activity. When activity is present, the activity LED is on (ACTLED# active low); when no activity is present, the activity LED is off. ACTLED# OUT In Wake on LAN mode, the ACTLED# signal is used to indicate that the received frame passed MAC address filtering. Link Integrity LED. The Link Integrity LED pin indicates link integrity. LILED# OUT If the link is valid in either 10 or 100 Mbps, the LED is on (LILED# active low); if link is invalid, the LED is off. Speed LED. The Speed LED pin indicates the speed. The speed LED SPDLED# OUT will be on at 100 Mbps (SPDLED# active low) and off at 10 Mbps. Datasheet 13 82551QM — Networking Silicon Table 9. PHY Signals Symbol Type Name and Function Reference Bias Resistor (100 Mbps). This pin should be connected RBIAS100 B a to a pull-down resistor. Reference Bias Resistor (10 Mbps). This pin should be connected RBIAS10 B a to a pull-down resistor. Voltage Reference. This pin is connected to a 1.25 V ± 1% external voltage reference generator. To use the internal voltage reference VREF B source, this pin should be left floating. Under normal circumstances, the internal voltage reference should be used and this pin would be left open. a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to com- pensate for high/low MDI transmit amplitude. See the 82562EZ(EX)/82551QM & 82540EM Combined Foot- print LOM Design Guide for more information. 4.7 Power and Ground Signals Table 10. Power and Ground Signals Symbol Type Name and Function Digital 3.3 V Power. The VCC pins should be connected to the main digital power supply. This is 3.3 V in systems with an auxiliary AUX VCC DPS power supply and PCI power in systems without an auxiliary power supply. The power source is configured through the FLA1/AUXPWR pin. VCCR APS Analog Power. These pins should be connected directly to VCC. VSSPL, Digital Ground. These pins should be connected to the main digital VSSPP, DPS ground plane. VSSPT, VSS No Connect. These pins should not be connected to any circuit. Pull- NC DPS up or pull-down resistors should not be used. 14 Datasheet Networking Silicon — 82551QM 5.0 Media Access Control Functional Description 5.1 Device Initialization The 82551QM has six sources for initialization. They are listed according to their precedence: 1. Internal Power-on Reset (POR) 2. ALTRST# pin 3. RST# pin 4. ISOLATE# pin 5. Software Reset (Software Command) 6. Selective Reset (Software Command) 5.1.1 Initialization Effects The following table lists the effect of each of the different initialization sources on major portions of the 82551QM. The initialization sources are listed in order of precedence. For example, any resource that is initialized by the software reset is also initialized by the D3 to D0 transition and ALTRST# and RST# but not necessarily by the selective reset. Table 11. Initialization Effects Internal D3 to D0 Software Selective ALTRST# RST# ISOLATE# POR Transition Reset Reset EEPROM read ?? ?? -- -- -- and initialization Loadable microcode ?? ?? ?? -- decoded/reset MAC configuration ?? ?? ?? -- reset and multicast hash Memory pointers and ?? ?? ??? mircomachine state reset PCI Configuration ?? ?? ? -- -- register reset PHY configuration ?? ? -- -- -- -- reset Datasheet 15 82551QM — Networking Silicon Table 11. Initialization Effects Internal D3 to D0 Software Selective ALTRST# RST# ISOLATE# POR Transition Reset Reset Clear only Clear only Power if no if no management ?? auxiliary auxiliary -- -- -- event reset power power present present Statistic ??? ?? ? -- counters reset Sampling of configuration ??? -- -- -- -- input pins 5.1.2 Initialization Effects on TCO Functionality The 82551QM has the ability to be controlled by two masters, the host CPU on the PCI bus and the TCO controller on the SMB. The 82551QM may be initialized by the PCI bus during SMB operation. The table below lists the effect of those sources: Table 12. Initialization Effects on TCO Status and Receive Initialization Source SMB Behavior Enable ALTRST#, RST#, or b The SMB is terminated instantaneously. Initialized to inactive a ISOLATE# The SMB cycle is aborted. During SMB read commands, the 82551QM transfers zeros until the end of the cycle. An SMB write cycle has no effect on the 82551QM. The 82551QM asserts the D3 to D0 transition Initialized to inactive SMB_ALERT# after a D3 to D0 transition. The 82551QM indicates its initialization status to the TCO controller via an active initialization bit in the Status Word. The SMB cycle is aborted. During SMB read commands, the 82551QM transfers zeros until the Software Reset, end of the cycle. An SMB write cycle has no effect on Selective Reset, or D3 to Unaffected the 82551QM. After a software reset, the 82551QM D0 transition reports its initialization in the same manner as in a D3 to D0 transition. a. ISOLATE# acts as reset on its trailing edge. While the 82551QM is in the D3 power state, the RST# initializes the 82551QM on the trailing edge. b. SMB commands in process will be terminated immediately. 5.2 PCI and CardBus Interface 5.2.1 Bus Operations After configuration, the 82551QM is ready for its normal operation. As a Fast Ethernet Controller, the role of the 82551QM is to access transmitted data or deposit received data. In both cases the 82551QM, as a bus master device, will initiate memory cycles by way of the PCI bus. 16 Datasheet Networking Silicon — 82551QM To perform these actions, the 82551QM is controlled and examined by the CPU through its control and status structures and registers. Some of these structures reside in the 82551QM and some reside in system memory. For access to the 82551QM’s Control/Status Registers (CSR), the 82551QM acts as a slave device. The 82551QM serves as a slave also while the CPU accesses its 128 KB Flash buffer or its EEPROM. When the 82551QM is in modem mode, it also acts as a slave. Details regarding modem interface are described in Section 5.6, “Parallel Flash/Modem Interface”. Section 5.2.1.1 describes the 82551QM slave operation. It is followed by a description of the 82551QM operation as a bus master (initiator) in Section 5.2.1.2. 5.2.1.1 Bus Slave Operation The 82551QM serves as a target device in the following cases: • CPU accesses to the 82551QM System Control Block (SCB) Control/Status Registers (CSR) • CPU accesses to the EEPROM through its CSR • CPU accesses to the 82551QM PORT address through the CSR • CPU accesses to the MDI control register in the CSR • CPU accesses to the Flash control register in the CSR • CPU accesses to the 128 KB Flash The CSR and the 1 MB Flash buffer are considered by the 82551QM as totally separated memory spaces. The 82551QM provides separate Base Address Registers (BARs) in the configuration space to distinguish between them. The size of the CSR memory space is 4 KB in the memory space and 64 bytes in the I/O space. The 82551QM treats accesses to these memory spaces differently. 5.2.1.1.1 Control/Status Register (CSR) Accesses The 82551QM supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request 4 KB of memory space and 64 bytes of I/O space to accomplish these accesses. The 82551QM provides 4 valid KB of CSR space, which include the following elements: • System Control Block (SCB) registers • PORT register • Flash control register • EEPROM control register • MDI control register • Flow control registers • CardBus registers The following figures show CSR zero wait state I/O read and write cycles. In the case of accessing the Control/Status Registers, the CPU is the initiator and the 82551QM is the target of the transaction. Datasheet 17 82551QM — Networking Silicon Figure 2. CSR I/O Read Cycle CLK 1 2 34 5 67 89 FRAME# ADDR DATA AD I/O RD BE# C/BE# IRDY# TRDY# DEVSEL# STOP# Read Accesses: The CPU, as the initiator, drives address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. As a slave, the 82551QM controls the TRDY# signal and provides valid data on each data access. The 82551QM allows the CPU to issue only one read cycle when it accesses the Control/Status Registers, generating a disconnect by asserting the STOP# signal. The CPU can insert wait states by de-asserting IRDY# when it is not ready. Figure 3. CSR I/O Write Cycle CLK 1 2 34 5 67 89 FRAME# ADDR DATA AD I/O WR BE# C/BE# IRDY# TRDY# DEVSEL# STOP# 18 Datasheet 82551QM SYSTEM 82551QM SYSTEM Networking Silicon — 82551QM Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551QM with valid data on each data access immediately after asserting IRDY#. The 82551QM controls the TRDY# signal and asserts it from the data access. The 82551QM allows the CPU to issue only one I/O write cycle to the Control/Status Registers, generating a disconnect by asserting the STOP# signal. This is true for both memory mapped and I/O mapped accesses. 5.2.1.1.2 Flash Buffer Accesses The CPU accesses to the Flash buffer are very slow and the 82551QM issues a target-disconnect at the first data access. The 82551QM asserts the STOP# signal to indicate a target-disconnect. The figures below illustrate memory CPU read and write accesses to the 128 KB Flash buffer. The longest burst cycle to the Flash buffer contains one data access only. Figure 4. Flash Buffer Read Cycle CLK FRAME# ADDR DATA AD MEM RD BE# C/BE# IRDY# TRDY# DEVSEL# STOP# Read Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM controls the TRDY# signal and de-asserts it for a certain number of clocks until valid data can be read from the Flash buffer. When TRDY# is asserted, the 82551QM drives valid data on the AD[31:0] lines. The CPU can also insert wait states by de-asserting IRDY# until it is ready. Flash buffer read accesses can be byte or word length. Datasheet 19 82551QM SYSTEM 82551QM — Networking Silicon Figure 5. Flash Buffer Write Cycle CLK FRAME# ADDR DATA AD MEM WR BE# C/BE# IRDY# TRDY# DEVSEL# STOP# Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. It also provides the 82551QM with valid data immediately after asserting IRDY#. The 82551QM controls the TRDY# signal and de-asserts it for a certain number of clocks until valid data is written to the Flash buffer. By asserting TRDY#, the 82551QM signals the CPU that the current data access has completed. Flash buffer write accesses can be byte length only. 20 Datasheet 82551QM SYSTEM Networking Silicon — 82551QM 5.2.1.1.3 Retry Premature Accesses The 82551QM responds with a Retry to any configuration cycle accessing the 82551QM before the completion of the automatic read of the EEPROM. The 82551QM may continue to Retry any configuration accesses until the EEPROM read is complete. The 82551QMdoes not enforce the rule that the retry master must attempt to access the same address again to complete any delayed transaction. Any master access to the 82551QM after the completion of the EEPROM read will be honored. Figure 6 below depicts how a Retry looks when it occurs. Figure 6. PCI Retry Cycle CLK FRAME# IRDY# TRDY# DEVSEL# STOP# Note: The 82551QM is considered the target in the above diagram; thus, TRDY# is not asserted. A Retry may also occur in the following two scenarios: • Card Information Structure (CIS) in memory is accessed in CardBus mode. • External modem registers are accessed and the modem does not assert IOCHRDY within 7 PCI clocks from the assertion of MDMCS#. 5.2.1.1.4 Error Handling Data Parity Errors: The 82551QM checks for data parity errors while it is the target of the transaction. If an error was detected, the 82551QM always sets the Detected Parity Error bit in the PCI Configuration Status register, bit 15. The 82551QM also asserts PERR#, if the Parity Error Response bit is set (PCI Configuration Command register, bit 6). The 82551QM does not attempt to terminate a cycle in which a parity error was detected. This gives the initiator the option of recovery. Target-Disconnect: The 82551QM prematurely terminates a cycle in the following cases: • After accesses to the Flash buffer • After accesses to its CSR • After accesses to the configuration space Datasheet 21 82551QM SYSTEM 82551QM — Networking Silicon System Error: The 82551QM reports parity error during the address phase using the SERR# pin. If the SERR# Enable bit in the PCI Configuration Command register or the Parity Error Response bit is not set, the 82551QM only sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). If SERR# Enable and Parity Error Response bits are both set, the 82551QM sets the Signaled System Error bit (PCI Configuration Status register, bit 14) as well as the Detected Parity Error bit and asserts SERR# for one clock. Note: The 82551QM detects a system error for any parity error during an address phase, whether or not it is involved in the current transaction. 5.2.1.2 Bus Master Operation As a PCI Bus Master, the 82551QM initiates memory cycles to fetch data for transmission or deposit received data and to access the memory resident control structures. The 82551QM performs zero wait state burst read and write cycles to the host main memory. Figure 7 and Figure 8 depict memory read and write burst cycles. For bus master cycles, the 82551QM is the initiator and the host main memory (or the PCI host bridge, depending on the configuration of the system) is the target. Figure 7. Memory Read Burst Cycle CLK 1 2 34 5 678 910 FRAME# ADDR DATA DATA DATA DATA DATA AD MR BE# BE# C/BE# IRDY# TRDY# DEVSEL# 22 Datasheet SYSTEM 82551QM Networking Silicon — 82551QM Figure 8. Memory Write Burst Cycle CLK 1 2 34 567 89 10 FRAME# ADDR DATA DATA DATA DATA DATA AD MW BE# BE# C/BE# IRDY# TRDY# DEVSEL# The CPU provides the 82551QM with action commands and pointers to the data buffers that reside in host main memory. The 82551QM independently manages these structures and initiates burst memory cycles to transfer data to and from them. The 82551QM uses the Memory Read Multiple (MR Multiple) command for burst accesses to data buffers and the Memory Read Line (MR Line) command for burst accesses to control structures. For all write accesses to the control structure, the 82551QM uses the Memory Write (MW) command. For write accesses to data structure, the 82551QM may use either the Memory Write or Memory Write and Invalidate (MWI) commands. Read Accesses: The 82551QM performs block transfers from host system memory to perform frame transmission on the serial link. In this case, the 82551QM initiates zero wait state memory read burst cycles for these accesses. The length of a burst is bounded by the system and the 82551QM’s internal FIFO. The length of a read burst may also be bounded by the value of the Transmit DMA Maximum Byte Count in the Configure command. The Transmit DMA Maximum Byte Count value indicates the maximum number of transmit DMA PCI cycles that will be completed after an 82551QM internal arbitration. The 82551QM, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM asserts IRDY# to support zero wait state burst cycles. The target signals the 82551QM that valid data is ready to be read by asserting the TRDY# signal. Write Accesses: The 82551QM performs block transfers to host system memory during frame reception. In this case, the 82551QM initiates memory write burst cycles to deposit the data, usually without wait states. The length of a burst is bounded by the system and the 82551QM’s internal FIFO threshold. The length of a write burst may also be bounded by the value of the Receive DMA Maximum Byte Count in the Configure command. The Receive DMA Maximum Byte Count value indicates the maximum number of receive DMA PCI transfers that will be completed before the 82551QM internal arbitration. The 82551QM, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control lines IRDY# and FRAME#. The 82551QM asserts IRDY# to support zero wait state burst cycles. The 82551QM also drives valid data on AD[31:0] lines during each data phase (from the first clock and on). The target controls the length and signals completion of a data phase by de-assertion and assertion of TRDY#. Datasheet 23 SYSTEM 82551QM 82551QM — Networking Silicon 5.2.1.2.1 Memory Write and Invalidate The 82551QM has four Direct Memory Access (DMA) channels. Of these four channels, the Receive DMA is used to deposit the large number of data bytes received from the link into system memory. The Receive DMA uses both the Memory Write (MW) and the Memory Write and Invalidate (MWI) commands. To use MWI, the 82551QM must guarantee the following: 1. Minimum transfer of one cache line 2. Active byte enable bits (or BE[3:0]# are all low) during MWI access 3. The 82551QM may cross the cache line boundary only if it intends to transfer the next cache line too. To ensure the above conditions, the 82551QM may use the MWI command only if the following conditions are true: 1. The Cache Line Size (CLS) written in the CLS register during PCI configuration is 8 or 16 Dwords. 2. The accessed address is cache line aligned. 3. The 82551QM has at least 8 or 16 Dwords of data in its receive FIFO. 4. There are at least 8 or 16 Dwords of data space left in the system memory buffer. 5. The MWI Enable bit in the PCI Configuration Command register, bit 4, must be set to 1b. 6. The MWI Enable bit in the 82551QM Configure command must be set to 1b. If any one of the above conditions is not true, the 82551QM uses the MW command. If an MWI cycle has started and one of the conditions is no longer valid (for example, the data space in the memory buffer is now less than CLS), then the 82551QM terminates the MWI cycle at the end of the cache line. The next cycle is either an MW or MWI cycle depending on the conditions listed above. If the 82551QM started a MW cycle and reached a cache line boundary, it either continues or terminates the cycle depending on the Terminate Write on Cache Line configuration bit of the 82551QM Configure command (byte 3, bit 3). If this bit is set, the 82551QM terminates the MW cycle and attempts to start a new cycle. The new cycle is an MWI cycle if this bit is set and all of the above conditions are met. If the bit is not set, the 82551QM continues the MW cycle across the cache line boundary if required. 5.2.1.2.2 Read Align The Read Align feature enhances the 82551QM’s performance in cache line oriented systems. In these particular systems, starting a PCI transaction on a non-cache line aligned address may cause low performance. To resolve this performance anomaly, the 82551QM attempts to terminate transmit DMA cycles on a cache line boundary and start the next transaction on a cache line aligned address. This feature is enabled when the Read Align Enable bit is set in the 82551QM Configure command (byte 3, bit 2). If this bit is set, the 82551QM operates as follows: • When the 82551QM is almost out of resources on the transmit DMA (that is, the transmit FIFO is almost full), it attempts to terminate the read transaction on the nearest cache line boundary. 24 Datasheet Networking Silicon — 82551QM • When the arbitration counter’s feature is enabled (in other words, the Transmit DMA Maximum Byte Count value is set in the Configure command), the 82551QM switches to other pending DMAs on cache line boundary only. This feature is not recommended for use in non-cache line oriented systems since it may cause shorter bursts and lower performance. If this feature is used, it is recommended that the CLS register in PCI Configuration space is set to 8 or 16. 5.2.1.2.3 Error Handling Data Parity Errors: As an initiator, the 82551QM checks and detects data parity errors that occur during a transaction. If the Parity Error Response bit is set (PCI Configuration Command register, bit 6), the 82551QM also asserts PERR# and sets the Data Parity Detected bit (PCI Configuration Status register, bit 8). In addition, if the error was detected by the 82551QM during read cycles, it sets the Detected Parity Error bit (PCI Configuration Status register, bit 15). 5.2.2 Clock Run Signal The CLK_RUN# signal is used to control the PCI clock as defined in the CardBus specification and PCI Mobile design guide and is compliant with both the CardBus specification and PCI Mobile design guide. This signal is active in both the CardBus and PCI bus operating modes. The Clock Run signal is an open drain I/O signal. It is used as a bidirectional channel between the host and the devices. • The host de-asserts the CLK_RUN# signal to indicate that the clock is about to be stopped or slowed down to a non-operational frequency. • The host asserts the CLK_RUN# signal when the clock is either running at a normal operating frequency or about to be started. • The 82551QM asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the host from stopping or to request that the host restore the clock if it was previously stopped. Proper operation requires that the system latency from the nominal PCI CLK to CLK_RUN# assertion should be less than 0.5 µs. If the system latency is longer than 0.5 µs, there is an increase in receive overruns. In these types of systems, the Clock Run functionality should be disabled. In this case, the 82551QM claims the PCI clock even during idle time. If the CLK_RUN# signal is not used, it must be connected to a pull-down resistor. 5.2.3 Power Management Event and Card Status Change Signals The 82551QM supports power management indications in the PCI and CardBus mode. In CardBus systems, the CSTSCHG pin is used for power management event indication. The PME# output pin provides an indication of a power management event in PCI systems. The CSTSCHG pin is supported by four registers located in the Control/Status Register (Section 10.0, “Control/Status Registers” describes these registers in more detail). Datasheet 25 82551QM — Networking Silicon 5.3 PCI Power Management The 82551QM supports a larger set of wake-up packets and the capability to wake the system on a link status change from a low power state. These added power management enhancements enable the 82551QM to adhere to emerging standards. The 82551QM enables the host system to be in a sleep state and remain virtually connected to the network. After a power management event or link status change is detected, the 82551QM wakes the host system. The sections below describe these events, the 82551QM power states, and estimated power consumption at each power state. 5.3.1 Power States The 82551QM contains two sets of power management registers, one for PCI and one for CardBus, The has one set of PCI power management registers and implements all four power states as defined in the Power Management Network Device Class Reference Specification, Revision 1.0. The four device power states, D0 through D3, vary from maximum power consumption at D0 to the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except for host accesses to the 82551QM’s PCI configuration registers. The D1 and D2 power management states enable intermediate power savings while providing the system wake-up capabilities. In the D3 cold state, the 82551QM can provide wake-up capabilities only if auxiliary power is supplied. Wake-up indications from the 82551QM are provided by the Power Management Event (PME#) signal in PCI implementations and the Card Status Change (CSTSCHG) signal in CardBus designs. In addition to providing a host interface through the PCI bus, the 82551QM provides TCO controller access through a dedicated System Management Bus (SMB). Additional information on the supported TCO functionality at all power states is described in Section 8.0, “Manageability Functionality”. 5.3.1.1 D0 Power State As defined in the Network Device Class Reference Specification, the device is fully functional in the D0 power state. In this state, the 82551QM receives full power and should be providing full functionality. In the 82551QM the D0 state is partitioned into two substates, D0 Uninitialized (D0u) and D0 Active (D0a). D0u is the 82551QM’s initial power state following a Power-on Reset (POR) event and before the Base Address Registers (BARs) are accessed. While in the D0u state, the 82551QM has PCI slave functionality to support its initialization by the host and supports Wake on LAN mode. Initialization of the CSR, Memory, or I/O Base Address Registers in the PCI Configuration space switches the 82551QM from the D0u state to the D0a state. In the D0a state, the 82551QM provides its full functionality and consumes nominal power. In addition, the 82551QM supports wake on link status change (Section 5.3.2, “Wake-up Events”). While it is active, the 82551QM requires a nominal PCI clock signal (in other words, a clock frequency greater than 16 MHz) for proper operation. During idle time, the 82551QM supports a PCI clock signal suspension using the Clock Run signal mechanism. The 82551QM supports a dynamic standby mode. In this mode, the 82551QM is able to save almost as much power as it does in the static power-down states. The transition to or from standby is done dynamically by the 82551QM and is transparent to the software. 26 Datasheet Networking Silicon — 82551QM 5.3.1.2 D1 Power State For a device to meet the D1 power state requirements, as specified in the Advanced Configuration and Power Interface (ACPI) Specification, Revision 1.0, it must not allow bus transmission or interrupts; however, bus reception is allowed. Therefore, device context may be lost and the 82551QM does not initiate any PCI activity. In this state, the 82551QM responds only to PCI accesses to its configuration space and system wake-up events. The 82551QM retains link integrity and monitors the link for any wake-up events such as wake-up packets or link status change. Following a wake-up event, the 82551QM asserts the PME# signal to alert the PCI system or the CSTSCHG signal for a CardBus system. 5.3.1.3 D2 Power State The ACPI D2 power state is similar in functionality to the D1 power state. If the bus is in the B2 bus power state, the 82551QM will consume less current than it does in the D1 state. In addition to D1 functionality, the 82551QM can provide a lower power mode with wake-on-link status change capability. The 82551QM may enter this mode if the link is down while the 82551QM is in the D2 state. In this state, the 82551QM monitors the link for a transition from an invalid link to a valid link. The 82551QM will not attempt to keep the link alive by transmitting idle symbols or link 1 integrity pulses. The sub-10 mA state due to an invalid link can be enabled or disabled by a configuration bit in the Power Management Driver Register (PMDR). 5.3.1.4 D3 Power State In the D3 power state, the 82551QM has the same capabilities and consumes the same amount of power as it does in the D2 state. However, it enables the PCI system to be in the Bus Power 3 (B3) state. If the PCI system is in the B3 state (in other words, no PCI power is present), the 82551QM provides wake-up capabilities if it is connected to an auxiliary power source in the system. If PME is disabled, the 82551QM does not provide wake-up capability or maintain link integrity. In this mode, the 82551QM consumes minimal power. The 82551QM enables a system to be in a sub-5 watt state (low power state) and still be virtually connected. More specifically, the 82551QM supports full wake-up capabilities while it is in the D3 cold state. The 82551QM can be connected to an auxiliary power source (V ), which enables it AUX to provide wake-up functionality while the PCI power is off. The typical current consumption of the 82551QM is 125 mA at 3.3 V and a dual power plane is not required. If connected to an auxiliary power source, the 82551QM receives all of its power from the auxiliary source in all power states. When connected to an auxiliary power supply, the 82551QM must have a status indicator of whether the power supply is valid (in other words, auxiliary power is stable). The indication is received at the AUXPWR pin, as described next. 1. For a topology of two 82551QM devices connected by a crossed twisted-pair Ethernet cable, the deep power-down mode should be disabled. If it is enabled, the two devices may not detect each other if the operating system places them into a low power state before both nodes become active. Datasheet 27 82551QM — Networking Silicon 5.3.1.4.1 Auxiliary Power Signal The 82551QM senses whether it is connected to the PCI power supply or to an auxiliary power supply (V ) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed AUX with FLA1) is sampled when the 82551QM power-on reset is active. An external pull-up resistor should be connected to the 82551QM if it is fed by V ; otherwise, the FLA1/AUXPWR pin AUX should be left floating. The presence of AUXPWR affects the value reported in the Power Management Capability Register (PCI Configuration Space, offset DEh). The Power Management Capability Register is described in more detail in Section 9.1.20, “Power Management Capabilities Register”. 5.3.1.4.2 Alternate Reset Signal The 82551QM’s ALTRST# input pin functions as a power-on reset input. Following ALTRST# being driven low, the 82551QM is initialized to a known state. While this function is required, this pin is not needed for it. Since this functionality is provided by the 82551QM’s internal power-on reset signal, this pin should be pulled high to the main digital power supply. Note: A separate internal power-on reset signal is generated when power is applied to the device. This signal is active while it provides the 82551QM power-on reset function and is also used for sampling configuration inputs. 5.3.1.4.3 Isolate Signal When the 82551QM is connected to V , it can be powered on while the PCI bus is powered off. AUX In this case, the 82551QM isolates itself from the PCI bus. The 82551QM has a dedicated ISOLATE# pin that must be connected to the PCI Reset signal. Whenever the PCI Bus is in the B3 state, the PCI Reset signal becomes active and the 82551QM isolates itself from the PCI bus. During this state, the 82551QM ignores all PCI signals including the RST# and CLK input signals. It also tristates all PCI outputs, except the PME# signal. In the transition to an active PCI power state (in other words, from B3 bus power state to B0 bus power state), the PCI Reset signal shifts high. This generates an internal hardware reset, which initializes the device (described in Section 5.1.1, “Initialization Effects”). Some designs in existence may implement the previous recommendations for the RST#, ISOLATE# and ALTRST# input pins. In these cases, the PCI Reset signal is connected to the RST# pin, the PCI power source’s stable power (power good) to the ISOLATE# pin, and the auxiliary power source’s stable power (auxiliary power good) to the ALTRST# pin. It is not necessary for existing working designs to make changes for these signals; however, it is recommended that the changes contained in this document should be included when possible. New designs should implement the recommendations contained in this document. 5.3.1.4.4 Reset Signal The RST# signal can be activated in one of the following cases: • Power-up • Warm boot • Wake-up (B3 to B0 transition) • Set to power-down (B0 to B3 transition) 28 Datasheet Networking Silicon — 82551QM If PME is enabled (in the PCI power management registers), the RST# signal does not affect any PME related circuits (in other words, the CSTSCHG registers (CardBus only), PCI power management registers, and the wake-up packet would not be affected). Note: The PCI Specification, Revision 2.2, states that the RST# signal should be active low in the B3 state. (In PCI Specification, Revision 2.1, the RST# signal is undefined during the B3 state.) The transition from the B3 bus power state to the B0 bus power state occurs on the trailing edge of the RST# signal. The initialization signal is generated internally in the following cases: • Active RST# signal while the 82551QM is the D0, D1, or D2 power state • RST# trailing edge while the 82551QM is in the D3 power state • ISOLATE# trailing edge The internal initialization signal resets the PCI Configuration Space, MAC configuration, and memory structure. The behavior of the RST# and ISOLATE# pins and the internal 82551QM initialization signal are shown in the following figure. Figure 9. Initialization upon RST# and ISOLATE# D0 - D2 power state RST# Internal hardware reset D3 power state RST# Internal hardware 640 ns reset Internal reset due to ISOLATE# ISOLATE# Internal hardware 640 ns reset Datasheet 29 82551QM — Networking Silicon The following tables list the functionality at the different power states for the 82551QM. Table 13. Functionality at the Different Power States Power State Link Functionality • Power-up state D0u Don’t care • PCI slave access Full functionality at full power and wake on an Valid invalid link D0a Full functionality at full power and wake on a valid Invalid link • Wake-up on “interesting” packets and link invalid Valid • PCI configuration access D1 • Wake on link valid Invalid • PCI configuration access Valid Same functionality as D1 (link valid) D2 Invalid Detection for valid link and no link integrity Valid Same functionality as D1 (link valid) D3 (with power) Invalid Detection for valid link and no link integrity No wake-up functionality Dx (x>0 without Note: If the TCO bit is set in the EEPROM, the Don’t care PME#) 82551QM will not disable the link function and will consume power as in the D2 state. 5.3.2 Wake-up Events There are two types of wake-up events: “Interesting” Packets and Link Status Change. These two events are detailed below. Note: The wake-up event is supported only if the PME Enable bit in the Power Management Control/ Status (PMCSR) register is set. The PMCSR is described in Section 9.1.21, “Power Management Control/Status Register (PMCSR)”. 5.3.2.1 “Interesting” Packet Event In the power-down state, the 82551QM is capable of recognizing “interesting” packets. The 82551QM supports pre-defined and programmable packets that can be defined as any of the following: • Address Resolution Protocol (ARP) Packets (with Multiple IP addresses) • Direct Packets (with or without type qualification) • Magic Packet* • Neighbor Discovery Multicast Address Packet (“ARP” in IPv6 environment) • NetBIOS over TCP/IP (NBT) Query Packet (under IPv4) • Internetwork Package Exchange* (IPX*) Diagnostic Packet • TCO Packet 30 Datasheet Networking Silicon — 82551QM This allows the 82551QM to handle various packet types. In general, the 82551QM supports programmable filtering of any packet in the first 128 bytes. When the 82551QM is in one of the low power states, it searches for a predefined pattern in the first 128 bytes of the incoming packets. The only exception is the Magic Packet, which is scanned for the entire frame. The 82551QM classifies the incoming packets into one of the following categories: • No Match. The 82551QM discards the packet and continues to process the incoming packets. • TCO Packet. The 82551QM implements perfect filtering of TCO packets. After a TCO packet is processed, the 82551QM is ready for the next incoming packet. There are two possible system environments: — TCO controller on the SMB. The entire TCO packet is transferred to the TCO controller. — System without TCO controller. TCO packets are treated as any other wake-up packets and may assert the PME# signal if configured to do so. • Wake-up Packet. The 82551QM is capable of recognizing and storing the first 128 bytes of a wake-up packet. If a wake-up packet is larger than 128 bytes, its tail is discarded by the 82551QM. After the system is fully powered-up, software has the ability to determine the cause of the wake-up event through the PMDR and dump the stored data to the host memory. Magic Packets are an exception. The Magic Packets may cause a power management event and set an indication bit in the PMDR; however, it is not stored by the 82551QM for use by the system when it wakes up. 5.3.2.2 Link Status Change Event The 82551QM link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82551QM reports a PME link status event in all power states. The PME# signal is gated by the PME Enable bit in the PMCSR and the CSMA Configure command. 5.4 CardBus Power Management The CardBus Power Management Proposal differs from the PCI Power Management Specification in the following manner: • The PME# signal is replaced by CSTSCHG which is an active high output signal. • An auxiliary power source, V , is supplied on the same V pins. AUX cc • An auxiliary power source bit in the PMC register must be set. • The PCI clock signal and the PCI reset signal are guaranteed to be kept low in the B3 state. In addition, the 82551QM also meets the CardBus requirement for current consumption less than 70 mA in the D0u state. 5.5 Wake on LAN (Preboot Wake-up) When the 82551QM is drawing power from an auxiliary power source (V ), it can support the AUX same preboot Wake on LAN (WOL) capabilities as the 82559 device. The 82551QM enters WOL mode after the following events occur: Datasheet 31 82551QM — Networking Silicon • An ALTRST# is completed. • The 82551QM reads the EEPROM and the WOL bit is set. When the 82551QM is in WOL mode: • The 82551QM scans incoming packets for a Magic Packet. When it receives a Magic Packet, the 82551QM asserts the PME# signal (until cleared) and the CSTSCHG signal for 52 ms. • The Activity LED changes its functionality to indicate that the received frame passed Individual Address (IA) filtering or broadcast filtering. • The PCI Configuration registers are accessible to the host. • Software must not attempt to access the Flash. The 82551QM switches from WOL mode to the D0a power state following a setup of the Memory or I/O Base Address Registers in the PCI Configuration space. If the 82551QM receives a Magic Packet while the it is in the D0u, D1, D2, or D3 power state, it issues a positive pulse on the CSTSCHG pin. This pulse is cleared by a later non-Wake on LAN message. For PCI systems and in designs that support the 3-pin header standard, the CSTSCHG pin acts as the WOL signal. 5.6 Parallel Flash/Modem Interface The 82551QM’s parallel interface is used for Flash interface only or modem interface only. The 82551QM supports a glueless interface to an 8-bit wide, 128 KB, parallel memory device. The parallel local port is multiplexed with a modem interface in a LAN/modem combination card. The Flash (or boot PROM) is read from or written to whenever the host CPU performs a read or a write operation to a memory location that is within the Flash mapping window. All accesses to the Flash, except read accesses, require the appropriate command sequence for the device used. (Refer to the specific Flash data sheet for more details on reading from or writing to the Flash device.) The accesses to the Flash are based on a direct decode of CPU accesses to a memory window defined in either the 82551QM Flash Base Address Register (PCI Configuration space at offset 18h) or the Expansion ROM Base Address Register (PCI Configuration space at offset 30h). The 82551QM asserts control to the Flash when it decodes a valid access. The 82551QM supports an external Flash memory (or boot PROM) of up to 128 KB. The Expansion ROM address can be separately disabled by setting the corresponding bit in the EEPROM, word Ah. 32 Datasheet Networking Silicon — 82551QM Note: Flash accesses must always be assembled or disassembled by the 82551QM whenever the access is greater than a byte-wide access. Due to slow access times to a typical Flash and to avoid violating PCI bus holding specifications (no more than 16 wait states inserted for any cycles that are not system initiation cycles), the maximum data size is either one word or one byte for a read operation and one byte only for a write operation. Note: In mobile applications, the MDMCS# pin enables the modem controller or Flash device. 5.7 Serial EEPROM Interface The serial EEPROM stores configuration data for the 82551QM and is a serial in/serial out device. The 82551QM supports either a 64-register or 256-register size EEPROM and automatically detects the EEPROM’s size. A 256-word EEPROM device is required for a Cardbus system and contains the CIS information. A 256-word EEPROM device is also required for a TCO enabled system to hold the heartbeat packet. The EEPROM should operate at a frequency of at least 1 MHz. All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The end of the address field is indicated by a dummy zero bit from the EEPROM, which indicates the entire address field has been transferred to the device. An EEPROM read instruction waveform is shown in the figure below. Figure 10. 64-Word EEPROM Read Instruction Waveform EESK EECS A A A A A A A A 5 4 3 2 1 10 0 EEDI READ OP code D D 15 0 EEDO The 82551QM can also use the EEPROM for heartbeat packet transmission (systems without a TCO controller are also supported). In these designs, the EEPROM is accessed through time windows autonomously by the 82551QM hardware. During these time windows, the 82551QM will respond with a PCI Retry to both EEPROM and Flash accesses. The 82551QM performs an automatic read of five words (0h, 1h, 2h, Ah, and Dh) of the EEPROM after the de-assertion of Reset. It may read six more words (Bh, Ch, FBh, FCh, FDh, and FEh) if the modem bit is set in the EEPROM (word Ah, bit 0). Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details. Datasheet 33 82551QM — Networking Silicon The 82551QM EEPROM format is shown below in Table 14. Table 14. EEPROM Address Map Word High Byte (Bits 15 – 8) Low Byte (Bits 7 – 0) 00h Ethernet Individual Address Byte 2 Ethernet Individual Address Byte 1 01h Ethernet Individual Address Byte 4 Ethernet Individual Address Byte 3 02h Ethernet Individual Address Byte 6 Ethernet Individual Address Byte 5 03h Compatibility Byte 1 Compatibility Byte 0 04h Reserved 05h Controller Type Connectors 06h Primary PHY Record (high byte) Primary PHY Record (low byte) 07h Secondary PHY Record (high byte) Secondary PHY Record (low byte) 08h PWA Byte 1 PWA Byte 2 09h PWA Byte 3 PWA Byte 4 0Ah EEPROM_ID (high byte) EEPROM_ID (low byte) 0Bh Subsystem_ID (high byte) Subsystem_ID (low byte) 0Ch Subsystem_Vendor (high byte) Subsystem_Vendor (low byte) SMB Address and Card Information 0Dh Configuration and Heartbeat Pointer Structure Pointer 0Eh Reserved 0Fh Reserved 10h Alerting APM Register Alerting Mask Register 11h Alerting Watchdog Data Alerting Watchdog 1 Data 12h Alerting Heartbeat Value Alerting Watchdog Value 13h Alerting RPC Value Alerting RTM Value 14h Alerting Enable Register Alerting Control Register 15h Alerting Poll 1 Register Alerting Poll 1 Address 16h Alerting Poll 1 Event Code Alerting Poll 1 Data Mask 17h Alerting Poll 2 Register Alerting Poll 2 Address 18h Alerting Poll 2 Event Code Alerting Poll 2 Data Mask 19h Alerting Poll 3 Register Alerting Poll 3 Address 1Ah Alerting Poll 3 Event Code Alerting Poll 3 Data Mask 1Bh Alerting Poll 4 Register Alerting 2 Poll 4 Address 1Ch Alerting Poll 4 Event Code Alerting Poll 4 Data Mask 1Dh Alerting Reset/Power Descriptor Register Alerting Reset/Power Descriptor Address 1Eh Alerting Reset Descriptors Alerting Reset Descriptors 1Fh ARP Enable IP Address Pointer 20h:22h Reserved 23h Device ID (high byte) Device ID (low byte) 24h – 2Fh Reserved 30h:33h Intel Boot Agent Configuration 34 Datasheet Networking Silicon — 82551QM Table 14. EEPROM Address Map (Continued) Word High Byte (Bits 15 – 8) Low Byte (Bits 7 – 0) 32h – 3Eh Reserved 3Fh 64-word EEPROM Checksum (high byte) 64-word EEPROM Checksum (low byte) 40h:F7h Controlled by the ASF Agent F8h:FEh Reserved for Software FFh 256-word EEPROM Checksum, high byte 256-word EEPROM Checksum, low byte Note: Refer to the 82551QM/ER/IT EEPROM Map and Programming Information for more details. 5.8 10/100 Mbps CSMA/CD Unit The 82551QM CSMA/CD unit implements both the IEEE 802.3 Ethernet 10 Mbps and IEEE 802.3u Fast Ethernet 100 Mbps standards. It performs all the CSMA/CD protocol functions such as transmission, reception, collision handling, etc. The 82551QM CSMA/CD unit communicates with the internal PHY unit through a standard Media Independent Interface (MII), as specified by IEEE 802.3, Chapter 22. This is a 10/100 Mbps mode in which the data stream is nibble-wide and the serial clocks run at either 25 or 2.5 MHz. 5.8.1 Full Duplex When operating in full duplex mode the 82551QM can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the receive differential pair of the PHY. The 82551QM operates in either half duplex mode or full duplex mode. For proper operation, both the 82551QM CSMA/CD module and the PHY unit must be set to the same duplex mode. The CSMA duplex mode is set by the 82551QM Configure command or forced by the settings in the PHY unit’s registers. The PHY duplex mode is set either by Auto-Negotiation or, if Auto-Negotiation is disabled, by setting the full duplex bit in the Management Data Interface (MDI) Register 0, bit 8. By default, the internal PHY unit advertises full duplex ability in the Auto-Negotiation process regardless of the duplex setting of the CSMA unit. The CSMA configuration should match the result of the Auto- Negotiation. The selection of duplex operation (full or half) and flow control is done in two levels: MAC and PHY. The MAC duplex selection is done only through the CSMA configuration mechanism (in other words, the Configure command in software). Datasheet 35 82551QM — Networking Silicon 5.8.2 Flow Control The 82551QM supports IEEE 802.3x frame-based flow control frames in both full duplex and half duplex switched environments. The 82551QM flow control feature is not intended to be used in shared media environments. The PHY unit’s duplex and flow control enable can be selected using the NWay* Auto-Negotiation algorithm or through the Management Data Interface. 5.8.3 Address Filtering Modifications The 82551QM can be configured to ignore one bit when checking for its Individual Address (IA) on incoming receive frames. The address bit, known as the Upper/Lower (U/L) bit, is the second least significant bit of the first byte of the IA. This bit may be used, in some cases, as a priority indication bit. When configured to do so, the 82551QM passes any frame that matches all other 47 address bits of its IA, regardless of the U/L bit value. This configuration only affects the 82551QM specific IA and not multicast, multi-IA or broadcast address filtering. The 82551QM does not attribute any priority to frames with this bit set, it simply passes them to memory regardless of this bit. 5.8.4 VLAN Support The 82551QM supports the VLAN standard as currently defined by the IEEE 802.1 committee. All VLAN flows will be implemented by software. The 82551QM supports the reception of long frames, specifically frames longer than 1518 bytes, including the CRC, if software sets the Long Receive OK bit in the Configuration command. Otherwise, “long” frames are discarded. 5.9 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit through a control register in the 82551QM. This allows the software driver to place the PHY in specific modes such as full duplex, loopback, power down, etc., without the need for specific hardware pins to select the desired mode. This structure allows the 82551QM to query the PHY unit for status of the link. This register is the MDI Control Register and resides at offset 10h in the 82551QM CSR. (The MDI registers are described in detail in Section 11.0, “PHY Unit Registers”.) The CPU writes commands to this register and the 82551QM reads or writes the control/status parameters to the PHY unit through the MDI register. Although the 82551QM follows the MII format, the MI bus is not accessible on external pins. 36 Datasheet Networking Silicon — 82551QM 6.0 Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal or a 25 MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal transmit digital clocks from this crystal or oscillator input. The internal Transmit Clock signal is a derivative of the 25 MHz internal clock. The accuracy of the external crystal or oscillator must be ± 0.005% (30 ppm). 6.1.2 100BASE-TX Transmit Blocks The transmit subsection of the PHY unit accepts nibble-wide data from the CSMA/CD unit. The transmit subsection passes data unconditionally to a 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5- bit-wide parallel symbols according to the IEEE 802.3u 100BASE_TX standard. Next, the symbols are scrambled to reduce electromagnetic emissions during long sequences of high-frequency data codes. The MLT-3 (multi-level signal) encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT- 3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, negative and zero. The transmit differential pair line drivers are implemented with digital slope controlled current buffers that meet the TP-PMD specifications. Current is sinked from an isolation transformer by the TDP and TDN pins. The 125 Mbps bit stream is typically driven onto Unshielded Twisted Pair (UTP) cable. 6.1.3 100BASE-TX Receive Blocks The receive subsection of the PHY unit accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the PHY unit will accurately receive valid data from Category 5 (CAT5) UTP cables of lengths well in excess of 100 meters. The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal. The clock recovery circuit uses digital signal processing to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder. The PHY unit first decodes the MLT-3 data; afterwards, the descrambler reproduces the 5B symbols originated in the transmitter. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the PHY unit outputs the receive data to the CSMA unit. In 100BASE-TX mode, the PHY unit can detect errors in receive data in a number of ways, including link integrity failures, undetected start of stream delimiters, invalid symbols, or idles in the middle of a frame. Datasheet 37 82551QM — Networking Silicon 6.1.4 100BASE-TX Link Integrity Auto-Negotiation The 82551QM Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY unit supports 10BASE-T half duplex, 10BASE-T full duplex, 100BASE-TX half duplex, and 100BASE-TX full duplex. Speed and duplex auto-select are functions of Auto-Negotiation. However, these parameters may be manually configured through the MII management interface (MDI registers). Manual configurations override the auto-select. 6.2 10BASE-T PHY Functions 6.2.1 10BASE-T Transmit Clock Generation The 20 MHz and 10 MHz clocks needed for 10BASE-T are synthesized from the external 25 MHz crystal or oscillator. The PHY unit provides the transmit clock and receive clock to the internal MAC at 2.5 MHz. 6.2.2 10BASE-T Transmit Blocks After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs Manchester encoding. Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The PHY unit supports both technologies through one pair of TD pins and by externally sharing the same magnetics. In 10 Mbps mode, the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” Manchester pulses and maintain a full drive level during narrow pulses and the first half of the wide pulses. This reduces jitter caused by overcharging the line. 6.2.3 10BASE-T Receive Blocks The PHY unit performs Manchester decoding and timing recovery when in 10 Mbps mode. The Manchester-encoded data stream is decoded from the RD pair to separate Receive Clock and Receive Data from the differential signal. This data is transferred to the CSMA unit at 2.5 MHz/ nibble. In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The input differential voltage range capability for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and idles, according to the requirements of the 10BASE-T standard. In 10 Mbps mode, the PHY unit can detect errors in the receive data, including voltage drops prior to the end-of-frame bit. Collision detection in 10 Mbps mode is initiated by simultaneous transmission and reception. If the PHY unit detects this condition, it asserts a collision indication to the CSMA/CD unit. 38 Datasheet Networking Silicon — 82551QM 6.2.4 10BASE-T Link Integrity and Full Duplex The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also used to determine if the receive pair polarity is reversed. If it is, the polarity is corrected internally. The PHY unit supports 10 Mbps full duplex by disabling the collision function, the squelch test, and the carrier sense transmit function. This allows the PHY unit to transmit and receive simultaneously, achieving up to 20 Mbps network bandwidth using Auto-Negotiation. Full duplex can only be used in point-to-point connections (no shared media). 6.3 Auto-Negotiation The PHY unit supports Auto-Negotiation, which is an automatic configuration scheme designed to manage interoperability in multifunctional LAN environments. An Auto-Negotiation capable device can detect and automatically configure its port to take maximum advantage of common modes of operation without user intervention or prior knowledge by either station. Auto- Negotiation is described in IEEE Standard 802.3u, clause 28. 6.3.1 Description A PHY’s capability is encoded by bursts of link pulses called Fast Link Pulses (FLPs). Connection is established by FLP exchange and handshake during link initialization time. After the link is established by this handshake, the native link pulse scheme resumes. A reset or management re- negotiate command (through the MDI interface) will restart the process. If Auto-Negotiation is unsuccessful, the 82551QM will use Parallel Detection. The PHY unit supports four technologies: 100BASE-Tx Full and Half Duplex and 10BASE-T Full and Half Duplex. Since only one technology can be used at a time (after every re-negotiate command), a prioritization scheme is used to ensure that the ability of the highest common denominator is chosen. 6.3.2 Parallel Detect and Auto-Negotiation The PHY unit can automatically determine the speed of the link by using Parallel Detect as an alternative to Auto-Negotiation. Upon a reset, a link status fail, or a negotiate/re-negotiate command, the PHY unit inserts a long delay during which no link pulses are transmitted. This period insures that the PHY unit‘s link partner has gone into a Link Fail state before Auto- Negotiation or Parallel Detection begins. The PHY unit will look for both FLPs and link integrity pulses. The following diagram illustrates this process. Datasheet 39 82551QM — Networking Silicon Figure 11. Auto-Negotiation and Parallel Detect Force_Fail Ability detect either by parallel detect or auto- negotiation. Parallel Detection Auto-Negotiation 10Base-T or 100Base-TX Link FLP capable Ready Look at Link Pulse; Auto-Negotiation capable = 1 Auto-Negotiation capable = 0 Ability Match LINK PASS Auto-Negotiation Complete bit set 6.4 LED Description The PHY unit supports three LED pins to indicate link status, network activity and network speed. Each pin can source 10 mA. • Link: This LED is off until a valid link has been detected. After a valid link has been detected, the LED will remain on (active-low). • Activity: This LED blinks on and off when activity is detected on the wire. • Speed: This LED will be on if a 100BASE-TX link is detected and off if a 10BASE-T link is detected. If the link fails while in Auto-Negotiation, this LED will keep the last valid link state. If 100BASE-TX link is forced this LED will be on, regardless of the link status. This LED will be off if the 10BASE-T link is forced, regardless of the link status. MDI register 27 in Section 11.3.12, “Register 27: PHY Unit Special Control Register” details the information for LED function mapping and support enhancements. Figure 12 provides possible schematic diagrams for configurations using two and three LEDs. 40 Datasheet Networking Silicon — 82551QM Figure 12. Two and Three LED Schematic Diagram vcc R LILED# R ACTLED# SPDLED# 82551QM R LILED# R R ACTLED# SPDLED# Datasheet 41 82551QM — Networking Silicon Note: This page intentionally left blank. 42 Datasheet Networking Silicon — 82551QM 7.0 Modem Functionality The local port mimics the standard 8-bit interface of a modem to the host system and emulates a 16550 Universal Asynchronous Receiver/Transceiver (UART) modem interface. The modem interface includes the following: • 8-bit data bus: FLD7:0 • Control signals: AEN (FLCS#), MCNTSM# (FLA12), MINT (FLA11), MRING# (FLA10), MRST (FLA9), RD# (FLOE#), and WR# (FLWE#) • 4 address lines 7.1 PCI Address Mapping to the Modem The modem can be accessed by the PCI bus through either I/O or memory mapping. 7.2 Modem Read and Write Cycles Basic read/write cycles to the modem device are shown in the figure below. Modem AEN (CS#) Modem Addrsess Modem Data In / Out Modem IOCHRDY Modem WE# / RD# t2 t3 t1 t4 t8 t5 t6' t6 t7 t9 t10 t11 Figure 13. Modem Read/Write Cycles 7.3 Modem and Preboot eXtension Environment Coexistence The 82551QM local bus can interface with a Flash device or modem without external support. External logic can be implemented on the circuit board to support both devices by using the Modem Chip Select (MDMCS#) and Flash Chip Select (FLCS#) signals. Datasheet 43 82551QM — Networking Silicon 7.3.1 Programming Details For designs that use both Flash and modem devices, the 82551QM supports the coexistence of BootROM accesses (for Preboot eXtension Environment [PXE] code) and modem: 1. Set the EEPROM’s MDM bit. 2. Clear the BD bit in the EEPROM. This enables both the modem and boot ROM. This allows the Boot Enable bit in the Expansion BAR to select which external device (modem or Flash) is active on the local bus through the use of the MDMCS# pin. After initialization, the 82551QM enables the Flash on the local bus (in other words, the Boot Enable bit in the BAR equals 1b) and the modem is disabled. Following the execution of the boot code from the Flash device, the enable bit is cleared, and the modem is enabled. The clearing of the Boot Enable bit causes the MDMCS# pin to be asserted, enabling the modem and Function 1 (Modem) Configuration space to be available. 7.3.2 Support Circuitry An example of support circuitry is shown in Figure 14. When MDMCS# is low, the modem is enabled; MDMCS# is high, the Flash device is enabled. Figure 14. Support Circuitry Example FLCS# MODEM_CS# FLSH_CS# MDMCS# (Modem_Mode#) 44 Datasheet Networking Silicon — 82551QM 8.0 Manageability Functionality The 82551QM acts as an SMB slave when receiving alert information and as bus master to collect information. 8.1 Alert Standard Format The 82551QM supports the Alert Standard Format (ASF) Specification, version 1.0 to monitor the health of systems connected to the network, including desktop, workstation and server systems. Intel’s ASF hardware and software enables all systems on the network to report advanced warning and system failure messages to a network management console, in the powered-up, powered-down, and pre-boot state. This data network allows an IT manager to use ASF to remotely perform corrective action on a system. An example of how ASF adds values to a managed network environment is realized when a system cooling fan fails. The client sends an alert to the network management console. In turn the network IT Manager uses the remote control capabilities of ASF to shut the system down to prevent if from overheating. Another example would be if the operating system hangs. The network manager can re-boot or re-start the system remotely to recover the system. Both of these usages are performed by the IT Manager without leaving his desk. ASF is based on Intel’s Alert on LAN* 2 technology but adds standards-based interfaces and packets. ASF incorporates the System Management Bus, version 2.0 to monitor the system and detect hardware failures. SMB sensors are placed on the motherboard to detect hardware failures that include temperature, fan, and voltage failures. When a failure is detected, ASF requires a Platform Event Trap (PET) packet (for example, SNMP or UDP packet) to be generated to inform the network management console. These bit-based packets are lightweight because they are generated in the powered-down state or boot sequence. In the OS present state, ASF uses the Common Interface Model (CIM) to interact with software components. All warning or failure messages are CIM based. ASF provides pre-boot Firmware Progress messages and Firmware Error alerts. The Firmware Progress messages detail the progress of the system BIOS as it is running. The firmware error alerts detail hardware failures that the BIOS detects as the system is booting. The Watchdog Timer and the Watchdog Register are used to deliver the alerts to the network management console even if the system fails to boot. The ASF specification supports over twenty-five firmware messages and firmware error alerts. The system is monitored through SMB sensors, which may push alerts. Otherwise, the 82551QM polls the sensors. When an alert is detected the 82551QM generates a PET compliant packet and sends it to the network management console. Intel’s 82551QM implementation also supports Remote Management Control Protocol (RMCP) features such as heartbeat, LAN leash and presence ping/pong, along with the boot path definitions. The heartbeats and LAN leash alerts are supported in both the powered-up and powered-down state. Datasheet 45 82551QM — Networking Silicon The 82551QM provides 128 user defined alerts to monitor system hardware. The 82551QM supports SMB, version 2.0 sensors along with eight SMB, version 1.0 sensors as stated in the ASF specification. Some common SMB, version 1.0 sensors available on the market: • Voltage • Temperature • Fan Tach In addition, Intel’s 82551QM includes support for the following remote control operations: • Presence ping/pong • System capability request/response • System state request/response • Power up • Unconditional power down • Reset and power cycle reset • Boot path definitions —NOP — Force PXE boot — Force hard drive boot — Force diagnostic boot — Force CD/DVD boot 8.2 Heartbeat 82551QM can be configured to send a heartbeat packet periodically. The heartbeat period (10.7 seconds to 23 minutes) is controlled by the heartbeat timer. Heartbeat and Ping/Pong are mutually exclusive features. 82551QM can also send a heartbeat packet in response to an ICH event. 8.3 Ping/Pong Upon receiving a “presence ping” packet, 82551QM replies with a “presence pong” packet. Heartbeat and Ping/Pong are mutually exclusive features. This feature can be enabled remotely through a management packet. 46 Datasheet Networking Silicon — 82551QM 8.4 Watchdog A watchdog packet is sent when the watchdog timer expires. Software can use these registers to indicate the state of the system. For example, the watchdog timer can be set and enabled upon initial power up. If the system hangs before reaching this point, the watchdog timer expires and the 82551QM notifies the management console. When the watchdog timer expires, 82551QM enters Force TCO mode, enables reception of management packets, and sends a watchdog SOS packet if LINK is valid. Because a hard power loss can happen without software knowledge, it is important to disable watchdog events during low power modes. If a hard power loss occurs, an EEPROM load will reload the watchdog timer and possibly set it to be enabled. At the point that PWR_GOOD transitions high, the watchdog timer will become enabled (if configured enabled) and start counting from its initial loaded value, essentially restarting the boot-up time-out timer. 8.5 Advanced Power Management Modes Upon receiving certain packets, 82551QM can perform Advanced Power Management (APM) transitions such as reset, power-up, and power-down. 8.6 Polling 82551QM acts as a master on the SMB to poll slaves for status, or set APM bits remotely. Target addresses to be polled are stored in the 82551QM’s configuration EEPROM. 8.7 Link Loss If 82551QM detects a link loss for more than 5 seconds, it transmits an alert packet when the link is recovered. 8.8 Acknowledge Management packets transmitted by 82551QM can be classified in three categories: SOS packets (event notifications), one-shot packets (receive acknowledgments, heartbeats and pongs), and ARP replies. 82551QM can be configured to retransmit each SOS packet a pre-defined number of times at a predefined interval until the SOS packet has been acknowledged. This capability adds reliability to ASF data transfer. Datasheet 47 82551QM — Networking Silicon Note: This page intentionally left blank. 48 Datasheet Networking Silicon — 82551QM 9.0 Configuration Registers The 82551QM acts as both a master and a slave on the PCI bus. As a master, the 82551QM interacts with the system main memory to access data for transmission or deposit received data. As a slave, some 82551QM control structures are accessed by the host CPU to read or write information to the on-chip registers. The CPU also provides the 82551QM with the necessary commands and pointers that allow it to process receive and transmit data. 9.1 Function 0: LAN (Ethernet) PCI Configuration Space The 82551QM PCI configuration space is configured as 16 Dwords of Type 0 Configuration Space Header, as defined in the PCI Specification, Revision 2.1. A small section is also configured according to its device specific configuration space. The configuration space header is depicted below in Figure 15. Figure 15. PCI Configuration Registers Device ID Vendor ID 00h Status Command 04h Class Code Revision ID 08h BIST Header Type Latency Timer Cache Line Size 0Ch CSR Memory Mapped Base Address Register 10h CSR I/O Mapped Base Address Register 14h Flash Memory Mapped Base Address Register 18h Reserved Base Address Register 1Ch Reserved Base Address Register 20h Reserved Base Address Register 24h Reserved (PCI mode)/CIS Pointer (CardBus mode) 28h Subsystem ID Subsystem Vendor ID 2Ch Expansion ROM Base Address Register 30h Reserved Cap_Ptr 34h Reserved 38h Max_Lat Min_Gnt Interrupt Pin Interrupt Line 3Ch Power Management Capabilities Next Item Ptr Capability ID DCh Reserved Data Power Management CSR E0h 9.1.1 PCI Vendor ID and Device ID Registers The Vendor ID and Device ID of the 82551QM are both read only word entities. Their values are: Vendor ID: 8086h Device ID: 1229h (deskside/server) Device ID 1059h (mobile) Datasheet 49 82551QM — Networking Silicon 9.1.2 PCI Command Register The 82551QM Command register at word address 04h in the PCI configuration space provides control over the 82551QM’s ability to generate and respond to PCI cycles. If a 0 is written to this register, the 82551QM is logically disconnected from the PCI bus for all accesses except configuration accesses. The format of this register is shown in the Figure 16. Figure 16. PCI Command Register 15 10 7 6 5 4 3 2 1 0 9 8 Reserved 0 0 0 0 SERR# Enable Parity Error Response Memory Write and Invalidate Enable Bus Master Enable Memory Space IO space Note: Bits three, five, seven, and nine are set to 0b. The table below lists the bits of the PCI Command register. Table 15. PCI Command Register Bits Bits Name Description 15:10 Reserved These bits are reserved and should be set to 0b. This bit controls a device’s ability to enable the SERR# driver. A value of 0b disables the SERR# driver. A value of 1b enables the SERR# driver. This 8 SERR# Enable bit must be set to report address parity errors. In the 82551QM, this bit is configurable and has a default value of 0b. This bit controls a device’s response to parity errors. A value of 0b causes the device to ignore any parity errors that it detects and continue normal 6 Parity Error Control operation. A value of 1b causes the device to take normal action when a parity error is detected. This bit must be set to 0b after RST# is asserted. In the 82551QM, this bit is configurable and has a default value of 0b. This bit controls a device’s ability to use the Memory Write and Invalidate command. A value of 0b disables the device from using the Memory Write Memory Write and 4 and Invalidate Enable command. A value of 1b enables the device to use Invalidate Enable the Memory Write and Invalidate command. In the 82551QM, this bit is configurable and has a default value of 0b. 50 Datasheet Networking Silicon — 82551QM Table 15. PCI Command Register Bits Bits Name Description This bit controls a device’s ability to act as a master on the PCI bus. A value of 0b disables the device from generating PCI accesses. A value of 2 Bus Master 1b allows the device to behave as a bus master. In the 82551QM, this bit is configurable and has a default value of 0b. This bit controls a device’s response to the memory space accesses. A value of 0b disables the device response. A value of 1b allows the device 1 Memory Space to respond to memory space accesses. In the 82551QM, this bit is configurable and has a default value of 0b. This bit controls a device’s response to the I/O space accesses. A value of 0b disables the device response. A value of 1b allows the device to 0 I/O Space respond to I/O space accesses. In the 82551QM, this bit is configurable and has a default value of 0b. 9.1.3 PCI Status Register The 82551QM Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Figure 17. PCI Status Register 31 30 29 28 27 26 25 24 23 22 21 20 19 16 0 0 0 0 1 1 0 0 1 Reserved Detected Parity Error Signaled System Error Received Master Abort Received Target Abort Signaled Target Abort Devsel Timing Parity Error Detected Fast Back To Back (target) Capabilities List Note: Bits 21, 22, 26, and 27 are set to 0b and bits 20, 23, and 25 are set to 1b. The PCI Status register bits are described in the table below. Table 16. PCI Status Register Bits Bits Name Description This bit indicates whether a parity error is detected. This bit must be set by the device when it detects a parity error, even if parity error handling is 31 Detected Parity Error disabled (as controlled by the Parity Error Response bit in the PCI Command register, bit 6). In the 82551QM, the initial value of the Detected Parity Error bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates when the device has asserted SERR#. In the 82551QM, 30 Signaled System Error the initial value of the Signaled System Error bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates whether or not a master abort has occurred. This bit must Received Master be set by the master device when its transaction is terminated with a 29 Abort master abort. In the 82551QM, the initial value of the Received Master Abort bit is 0b. This bit is set until cleared by writing a 1b. Datasheet 51 82551QM — Networking Silicon Table 16. PCI Status Register Bits Bits Name Description This bit indicates that the master has received the target abort. This bit must be set by the master device when its transaction is terminated by a 28 Received Target Abort target abort. In the 82551QM, the initial value of the Received Target Abort bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates whether a transaction was terminated by a target abort. 27 Signaled Target Abort This bit must be set by the target device when it terminates a transaction with target abort. In the 82551QM, this bit is always set to 0b. These two bits indicate the timing of DEVSEL#: 00b - Fast 01b - Medium 26:25 DEVSEL# Timing 10b - Slow 11b - Reserved In the 82551QM, these bits are always set to 1b, medium. This bit indicates whether a parity error has been detected. This bit is set to 1b when the following three conditions are met: 1. The bus agent asserted PERR# itself or observed PERR# asserted. 2. The agent setting the bit acted as the bus master for the operation in 24 Parity Error Detected which the error occurred. 3. The Parity Error Response bit in the command register (bit 6) is set. In the 82551QM, the initial value of the Parity Error Detected bit is 0b. This bit is set until cleared by writing a 1b. This bit indicates a device’s ability to accept fast back-to-back transactions when the transactions are not to the same agent. A value of 0b disables 23 Fast Back-to-Back fast back-to-back ability. A value of 1b enables fast back-to-back ability. In the 82551QM, this bit is read only and is set to 1b. This bit indicates whether the 82551QM implements a list of new capabilities such as PCI Power Management. A value of 0b means that this function does not implement the Capabilities List. If this bit is set to 1b, the 20 Capabilities List Cap_Ptr register provides an offset into the 82551QM PCI Configuration space pointing to the location of the first item in the Capabilities List. This bit is set only if the power management bit in the EEPROM is set. 19:16 Reserved These bits are reserved and should be set to 0000b. 9.1.4 PCI Revision ID Register The Revision ID is an 8-bit read only register. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM (Section 5.7, “Serial EEPROM Interface”). The default value of the Revision ID is 82551QM (A-step): 0Fh 9.1.5 PCI Class Code Register The Class Code register is read only and is used to identify the generic function of the device and, in some cases, specific register level programming interface. The register is broken into three byte size fields. The upper byte is a base class code and specifies the 82551QM as a network controller, 2h. The middle byte is a subclass code and specifies the 82551QM as an Ethernet controller, 0h. The lower byte identifies a specific register level programming interface and the 82551QM always returns a 0h in this field. 52 Datasheet Networking Silicon — 82551QM 9.1.6 PCI Cache Line Size Register In order for the 82551QM to support the Memory Write and Invalidate (MWI) command, the 82551QM must also support the Cache Line Size (CLS) register in PCI Configuration space. The register supports only cache line sizes of 8 and 16 Dwords. Any value other than 8 or 16 that is written to the register is ignored and the 82551QM does not use the MWI command. If a value other than 8 or 16 is written into the CLS register, the 82551QM returns all zeroes when the CLS register is read. The figure below illustrates the format of this register. Figure 18. Cache Line Size Register 7 6543210 0 0 0 RW RW 000 Note: Bit 3 is set to 1b only if the value 00001000b (8h) is written to this register, and bit 4 is set to 1b only if the value of 00010000b (16h) is written to this register. All other bits are read only and will return a value of 0b on read. The BIOS is expected to write to this register. Therefore, the 82551QM driver should not write to it. 9.1.7 PCI Latency Timer The Latency Timer register is a byte wide register. When the 82551QM is acting as a bus master, this register defines the amount of time, in PCI clock cycles, that it may own the bus. 9.1.8 PCI Header Type The Header Type register is a byte read only register. It is equal to 00h for a single function Ethernet card and 80h for a combination Ethernet and modem card. The value of the header type is set by the EEPROM (Section 5.7, “Serial EEPROM Interface”). In a dual function card, the OS will read the next configuration registers bank at offset 100h. 9.1.9 PCI Base Address Registers One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in address spaces. The 82551QM contains three types of Base Address Registers (BARs). Two are used for memory mapped resources, and one is used for I/O mapping. Each register is 32 bits wide. The least significant bit in the BAR determines whether it represents a memory or I/O space. The figures below show the layout of a BAR for both memory and I/O mapping. After determining this information, power-up software can map the memory and I/O controllers into available locations and proceed with system boot. In order to do this mapping Datasheet 53 82551QM — Networking Silicon in a device independent manner, the base registers for this mapping are placed in the predefined header portion of configuration space. Device drivers can then access this configuration space to determine the mapping of a particular device. Figure 19. Base Address Register for Memory Mapping 4321 0 31 Base Address 0 Prefetchable The prefetchable bit is set to “0” Type 00 - locate anywhere in 32-bit address space 01 - locate below 1 MB 10 - locate anywhere in 64-bit address space 11 - reserved Memory space indicator Figure 20. Base Address Register for I/O Mapping 21 0 31 0 1 Base Address Reserved I/O space indicator Note: Bit 0 in all base registers is read only and used to determine whether the register maps into memory or I/O space. Base registers that map to memory space must return a 0b in bit 0. Base registers that map to I/O space must return 1b in bit 0. Base registers that map into I/O space are always 32 bits wide with bit 0 hard-wired to a 1b, bit 1 is reserved and must return 0b on reads, and the other bits are used to map the device into I/O space. The number of upper bits that a device actually implements depends on how much of the address space the device will respond to. For example, a device that wants a 1 MB memory address space would set the most significant 12 bits of the base address register to be configurable, setting the other bits to 0b. The 82551QM contains BARs for the Control/Status Register (CSR), Flash, and Expansion ROM. 9.1.9.1 CSR Memory Mapped Base Address Register The 82551QM requires one BAR for memory mapping. Software determines which BAR, memory or I/O, is used to access the 82551QM CSR registers. The memory space for the 82551QM CSR Memory Mapped BAR is 4 KB. The space is marked as not prefetchable and is mapped anywhere in the 32-bit memory address space. 54 Datasheet Networking Silicon — 82551QM 9.1.9.2 CSR I/O Mapped Base Address Register The 82551QM requires one BAR for I/O mapping. Software determines which BAR, I/O or memory, is used to access the 82551QM CSR registers. The I/O space for the 82551QM CSR I/O BAR is 64 bytes. 9.1.9.3 Flash Memory Mapped Base Address Register The Flash Memory BAR is a Dword register. The 82551QM physically supports a 128 KB Flash device. In a CardBus system, the upper section of the memory mapped window (above the physical Flash device) is used for CIS information. The 82551QM claims a window of 128 KB in CardBus mode and always claims a Flash memory window, regardless of whether or not a Flash device is connected. Datasheet 55 82551QM — Networking Silicon 9.1.9.4 Expansion ROM Base Address Register The Expansion ROM has a memory space of 1 MB and its BAR is a Dword register that supports a 128 KB memory via the 82551QM local bus. The Expansion ROM BAR can be disabled by setting the Boot Disable bit located in the EEPROM (word Ah, bit 11). If the Boot Disable bit is set, the 82551QM returns a 0b for all bits in this address register, avoiding request of memory allocation for this space. In LAN/modem combination designs using a Flash device, this bit controls the state of the Modem Chip Select (MDMCS#) pin and is cleared after the initial access of the expansion ROM area. Therefore, in LAN/modem combination designs the MDMCS# pin will be de-asserted (high) when the Boot Disable bit is not set in the EEPROM and the ROM enable bit is set in the Expansion ROM Base Address Register. After the initial access to the Expansion ROM BAR, the Boot Disable bit will be cleared and the MDMCS# signal is asserted (low) enabling the modem to use the local bus. 9.1.10 Base Address Registry Summary The preceding description of the Base Address Registers’ functions are listed in the following table: Table 17. Base Address Register Functions CardBus CardBus Register Name PCI Function PCI Window Function Window BAR0 Memory CSR 4 KB Memory CSR 4 KB BAR1 I/O CSR 4 KB I/O CSR 4 KB CIS at offset + BAR2 Flash 128 KB 128 KB 64 KB N/A (disabled by Expansion BAR BootROM 1 MB 1 MB EEPROM) 9.1.11 CardBus Card Information Structure (CIS) Pointer The Card Information Structure (CIS) pointer is a Dword hard-coded, read only register. It is meaningful only in a CardBus system (in a PCI system it is zero). The CIS pointer defines where the CIS structure is mapped in the Flash address space. Table 18. CIS Pointer Bits R/W Default Description 31:4 R 1000h Ethernet CIS Pointer (above the physical Flash window) 3:0 R 3h CIS in the Flash window 9.1.12 PCI Subsystem Vendor ID and Subsystem ID Registers The Subsystem Vendor ID field identifies the vendor of an 82551QM based solution. The Subsystem Vendor ID values are based upon the vendor’s PCI Vendor ID and is controlled by the PCI Special Interest Group (SIG). The Subsystem ID field identifies the 82551QM based specific solution implemented by the vendor indicated in the Subsystem Vendor ID field. 56 Datasheet Networking Silicon — 82551QM The 82551QM provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82551QM automatically reads addresses Ah through Ch of the EEPROM. The first of these 16-bit values is used for controlling various 82551QM functions. The second is the Subsystem ID value, and the third is the Subsystem Vendor ID value. Again, the default values for the Subsystem ID and Subsystem Vendor ID are 0h and 0h, respectively. The 82551QM checks bit numbers 15, 14, and 13 in the EEPROM, word Ah and functions according to Table 19 below. Table 19. ID Fields Programming a Signature ID AltID Device Vendor Revision ID Subsystem Subsystem (Bits 15:14) (Bit 13) (Bit 7) ID ID (A-0 and A-1) ID Vendor ID b 11b , 10b, X X 1229h 8086h 0Fh 0000h 0000h 00b Word Ah, bits 01b 1b X 1229h 8086h Word Bh Word Ch 10:8 01b 0b 1b 1229h 8086h 0Fh Word Bh Word Ch 01b 0b 0b 1229h 8086h 0Fh Word Bh Word Ch a. The Revision ID is subject to change according to the silicon stepping. b. If bit 15 equals 1b, the EEPROM is invalid and the default values are used. The above table implies that if the 82551QM detects the presence of an EEPROM (as indicated by a value of 1b in bits 15 and 14), then bit number 13 determines whether the values read from the EEPROM, words Bh and Ch, are loaded into the Subsystem ID (word Bh) and Subsystem Vendor ID (word Ch) fields. If bits 15 and 14 equal 1b and bit 13 equals 1b, the three least significant bits of the Revision ID field are programmed by bits 10:8 of the first EEPROM word, Ah. Between the de-assertion of reset and the completion of the automatic EEPROM read, the 82551QM does not respond to any PCI configuration cycles. If the 82551QM happens to be accessed during this time, it will Retry the access. More information on Retry is provided in Section 5.2.1.1.3, “Retry Premature Accesses”. 9.1.13 Capability Pointer The Capability Pointer is a hard-coded byte register with a value of DCh. It provides an offset within the Configuration Space for the location of the Power Management registers. 9.1.14 Interrupt Line Register The Interrupt Line register identifies which system interrupt request line on the interrupt controller the device’s PCI interrupt request pin (as defined in the Interrupt Pin register) is routed to. 9.1.15 Interrupt Pin Register The Interrupt Pin register is read only and defines which of the four PCI interrupt request pins, INTA# through INTD#, a PCI device is connected to. The 82551QM is connected the INTA# pin. Datasheet 57 82551QM — Networking Silicon 9.1.16 Minimum Grant Register The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI bus ownership when it initiates a transaction. The default value of this register for the 82551QM is 08h. 9.1.17 Maximum Latency Register The Maximum Latency (Max_Lat) register is an optional read only register for bus masters and is not applicable to non-master devices. This register defines how often a device needs to access the PCI bus. The default value of this register for the 82551QM is 18h. 9.1.18 Capability ID Register The Capability ID is a byte register. It signifies whether the current item in the linked list is the register defined for PCI Power Management. PCI Power Management has been assigned the value of 01h. The 82551QM is fully compliant with the PCI Power Management Specification, Revision 2.2. 9.1.19 Next Item Pointer The Next Item Pointer is a byte register. It describes the location of the next item in the 82551QM’s capability list. Since power management is the last item in the list, this register is set to 0b. 9.1.20 Power Management Capabilities Register The Power Management Capabilities register is a word read only register. It provides information on the capabilities of the 82551QM related to power management. The 82551QM reports a value of FE21h if it is connected to an auxiliary power source and 7E21h otherwise. It indicates that the 82551QM supports wake-up in the D3 state if power is supplied, either V or V . cc AUX Table 20. Power Management Capability Register Bits Default Read/Write Description 00011b PME Support. This five-bit field indicates the power states in which (no V ) the 82551QM may assert PME#. The 82551QM supports wake-up in AUX 31:27 Read Only all power states if it is fed by an auxiliary power supply (V ) and 11111b AUX D0, D1, D2, and D3 if it is fed by PCI power. (V ) hot AUX D2 Support. If this bit is set, the 82551QM supports the D2 power 26 1b Read Only state. D1 Support. If this bit is set, the 82551QM supports the D1 power 25 1b Read Only state. Auxiliary Current. This field reports whether the 82551QM implements the Data registers. The auxiliary power consumption is 24:22 000b Read Only the same as the current consumption reported in the D3 state in the Data register. Device Specific Initialization (DSI). The DSI bit indicates whether special initialization of this function is required (beyond the standard 21 1b Read Only PCI configuration header) before the generic class device driver is able to use it. DSI is required for the 82551QM after D3-to-D0 reset. 58 Datasheet Networking Silicon — 82551QM Table 20. Power Management Capability Register Bits Default Read/Write Description 0b (PCI) Reserved (PCI)/Auxiliary Power Source (CardBus). When this bit 20 Read Only is set to 1, it indicates that the 82551QM requires auxiliary power 1b supplied by the system for wake-up from the D3 state. (CardBus) cold PME Clock. The 82551QM does not require a clock to generate a 19 0b Read Only power management event. Version. A value of 010b indicates that the 82551QM complies with 18:16 010b Read Only of the PCI Power Management Specification, Revision 2.2. 9.1.21 Power Management Control/Status Register (PMCSR) The Power Management Control/Status is a word register. It is used to determine and change the current power state of the 82551QM and control the power management interrupts in a standard manner. Table 21. Power Management Control and Status Register Bits Default Read/Write Description PME Status. This bit is set upon a wake-up event. It is independent of the state of the PME Enable bit. If 1b is written to this bit, the bit will be cleared. It also de-asserts the PME# signal and clears the PME status bit in the Power Management Driver Register. When the PME# signal 15 0b Read/Clear is enabled, the PME# signal reflects the state of the PME status bit. In a CardBus system, writing a 1b to this bit clears the GWAKE bit in the Function Event register. Data Scale. This field indicates the data register scaling factor. It 14:13 00b Read Only equals 10b for registers zero through eight and 00b for registers nine through fifteen. Data Select. This field is used to select which data is reported through 12:9 0000b Read Only the Data register and Data Scale field. 8 0b Read Clear PME Enable. This bit enables the 82551QM to assert PME#. 7:5 000b Read Only Reserved. These bits are reserved and should be set to 000b. Dynamic Data. The 82551QM does not support the ability to monitor 4 0b Read Only the power consumption dynamically. 3:2 00b Read Only Reserved. These bits are reserved and should be set to 00b. Power State. This 2-bit field is used to determine the current power state of the 82551QM and to set the 82551QM into a new power state. The definition of the field values is as follows. 00 - D0 1:0 00b Read/Write 01 - D1 10 - D2 11 - D3 Datasheet 59 82551QM — Networking Silicon 9.1.22 Data Register The data register is an 8-bit read only register that provides a mechanism for the 82551QM to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written to the Data Select field in the PMCSR register. The power measurements defined in this register have a dynamic range of 0 to 2.55 W with 0.01 W resolution according to the Data Scale. The value in this register is hard-coded in the silicon. The structure of the data register is listed in Table 22. Table 22. Ethernet Data Register Data Select Data Scale Data Reported 0 2 D0 Power Consumption = 60 (600 mW) 1 2 D1 Power Consumption = 42 (420 mW) 2 2 D2 Power Consumption = 42 (420 mW) 3 2 D3 Power Consumption = 42 (420 mW) 4 2 D0 Power Dissipated = 60 (60 mW) 5 2 D1 Power Dissipated = 42 (420 mW) 6 2 D2 Power Dissipated = 42 (420 mW) 7 2 D3 Power Dissipated = 42 (420 mW) 8 2 Common Function Power Dissipated = 00 9-15 0 Reserved (00h) 9.2 Function 1: Modem PCI Configuration Space In PCI and CardBus system, the 82551QM supports a dual function device: LAN/modem. The LAN is defined as function zero, and the modem is defined as function one. The modem function is active depending on the EEPROM setup. Figure 21. Modem PCI Configuration Registers Modem Configuration ID 00h Modem Status Modem Command 04h Modem Revision ID 08h BIST Modem Header Type Latency Timer Cache Line Size 0Ch Modem I/O Mapped Base Address Register 10h Modem Memory Mapped Base Address Register 14h Reserved Base Address Register 18h Reserved Base Address Register 1Ch Reserved Base Address Register 20h Reserved Base Address Register 24h Reserved (PCI mode)/Modem CIS Pointer (CardBus mode) 28h Modem Subsystem ID Modem Subsystem Vendor ID 2Ch Expansion ROM Base Address Register 30h Reserved Cap_Ptr 34h 60 Datasheet Networking Silicon — 82551QM Figure 21. Modem PCI Configuration Registers Reserved 38h Max_Lat Min_Gnt Modem Interrupt 3Ch Modem Power Management Capabilities Next Item Ptr Capability ID DCh Reserved Modem Data Modem Power Management CSR E0h The modem configuration registers define the resources required by the modem function. It is meaningful in a multifunction card design only. Some of the modem configuration registers are a reflection of their matched Ethernet registers. The registers’ values are pre-defined by hardware, initialized by the EEPROM, or configurable through software. The shaded fields are described in detail in the following subsections. 9.2.1 Modem Configuration ID Register The Modem Configuration ID field is a Dword register composed of the Device ID and Vendor ID. It is a read only register and its value is loaded from the EEPROM. 9.2.2 Modem Command Register The Modem Command field is a 16-bit word register and provides basic control over the modem’s ability to respond to PCI/CardBus accesses. The Command register’s structure is shown in Table 23. Table 23. Power Management Control and Status Register Bits Default Read/Write Description 15:10 000000b Read Only Reserved. These bits are reserved and should be set to 000000b. 9 0b Read Only Fast Back-to-Back. 8 0b Read/Write System Error Enable. 7 0b Read Only Wait Cycle Enable. 6 0b Read/Write Parity Error Enable. 5 0b Read Only VGA (define). 4 0b Read Only Memory Write and Invalidate. 3 0b Read Only Special Cycle. 2 0b Read Only Master Enable. 1 0b Read/Write Memory Access Enable. 0 0b Read/Write I/O Access Enable. Datasheet 61 82551QM — Networking Silicon 9.2.3 Modem Status Register The Modem Status field is a 16-bit word register. It provides basic track of CardBus related events. All bits are cleared by RST#. Table 24. Modem Status Register Bits Default Read/Write Description 15 0 Read/Write Parity Error. 14 0 Read/Write System Error Enable. 13:11 000 Read Only Signaled/Received Target Abort. 10:9 01 Read Only Device Select Timing. 8 0 Read Only Data Parity Detect. 7 0 Read Only Fast Back-to-Back Capable. 6:5 00 Read Only Reserved. These bits are reserved and should be set to 00b. 4 1 Read Only New Capability. 3:0 0000 Read Only Reserved. These bits are reserved and should be set to 0000b. 9.2.4 Modem Revision ID Register The Modem Revision ID register is a Dword, read only field. It is composed of the Revision ID byte and a 24-bit Class Code register. Its value is loaded from the EEPROM. The Class Code identifies the function as a modem. The Class Code and Revision ID are listed in Table 25. Table 25. Modem Revision Register Bits Default Read/Write Description Base Class. This indicates that the 82551QM is a communication 31:24 07h Read Only device. 23:16 00h Read Only Subclass. This indicates the serial controller equals 00h. Program Interface. This indicates that the 82551QM is 16550 UART 15:8 02h Read Only compatible and initialized by EEPROM word FEh. Revision Number. This indicates the revision number and is initialized 7:0 XXH Read Only by EEPROM word FEh. 9.2.5 Modem Header Type Register The Modem Header Type field is a byte wide, read only register. It indicates that this is a multifunction card and a value of 80h is hard-coded in the silicon. 9.2.6 Modem I/O Base Address Register The Modem I/O BAR is a Dword register that specifies the I/O base address for accessing the 82551QM’s modem. The required I/O space is 8 bytes. 62 Datasheet Networking Silicon — 82551QM 9.2.7 Modem Memory Base Address Register The Modem Memory BAR is a Dword register that specifies the memory base address for accessing the 82551QM’s modem port. The required memory space is 4 KB. The memory space is used for both control registers and CIS mapping. 9.2.8 Modem CardBus CIS Pointer The CIS pointer is a Dword, hard-coded, read only register. The CIS pointer indicates whether or not the CIS structure is located in the memory address space. The physical location of the CIS structure is in the serial EEPROM. The EEPROM format is described in Section 5.7, “Serial EEPROM Interface”. Bits R/W Default Description 31:4 R 0010h Modem CIS Pointer (above the control registers) 3:0 R 2h CIS in the Memory Base Address Register 9.2.9 Modem Subsystem Vendor ID Register The Modem Subsystem Vendor ID is a 16-bit read only register. Its value is loaded from the EEPROM and is a reflection of register 2Ch in Function 0, LAN (Ethernet) function. 9.2.10 Modem Subsystem ID Register The Modem Subsystem ID is a 16-bit, read only register. Its value is loaded from the EEPROM and is a reflection of register 2Eh in Function 0, LAN (Ethernet) function. 9.2.11 Modem Capabilities Pointer The Modem Capability Pointer is a hard-coded, byte register that contains the value DCh. It provides an offset within the Configuration Space for the location of the power management registers. 9.2.12 Modem Interrupt Register The Modem Interrupt register specifies whether or not the modem requires an interrupt. This register is hard-coded identically to register 3Ch in Function 0, LAN (Ethernet). It indicates that the modem requires interrupt support. Note: The modem and Ethernet functions share the same INTA# pin. 9.2.13 Modem Power Management Capabilities Register The Modem Power Management Capabilities register is a Dword field that indicates if this function has power management capability. It also identifies which power management capabilities are supported. The 82551QM reports a value of FE31h if it is connected to an auxiliary power source; and 7E21h, otherwise. Datasheet 63 82551QM — Networking Silicon 9.2.14 Modem Power Management Control/Status Register The Modem Power Management Control/Status Register is a word register. It is used to manage the modem’s power management state. It also enables and monitors power management events. The Modem Power Management Control/Status Register structure is identical to register E0h in Function 0, LAN (Ethernet) function. 9.2.15 Modem Data Register The Modem Data register has similar functionality to register E2h in Function 0, LAN (Ethernet). The register at location E2h reports power consumption of the modem function. The value of power consumption and power dissipation are loaded from the EEPROM. Table 26. Ethernet Data Register Data Select Data Scale Data Reported D0 to D3 Power Consumption (loaded from 0 - 3 2 EEPROM) D0 to D3 Power Dissipated (loaded from 4 - 7 2 EEPROM) 8 - 15 0 Reserved (00h) 9.2.16 Modem Support in PCI Mode The 82551QM supports a modem interface in PCI mode. The Modem Enable (MDM) bit in the EEPROM can be activated in PCI systems without the loss of BootROM support. In addition, BootROM support has been simplified. The 82551QM supports the co-existence of a BootRom Flash device and a modem device. This is done by setting the MDM bit and clearing the Boot Disable (BD) bit in the EEPROM. With this configuration, both modem functionality and the BootRom BAR are active. The selection between the two functions is done through Boot Enable bit (the least significant bit of the BootRom BAR in the LAN PCI Configuration space). The 82551QM will not support a LAN/modem design if additional companion ASICs are operating on the Flash/modem interface. This limitation does not affect companion ASICs that reside on the SMB interface of the 82551QM. 64 Datasheet Networking Silicon — 82551QM 10.0 Control/Status Registers 10.1 LAN (Ethernet) Control/Status Registers The 82551QM’s Control/Status Register (CSR) is illustrated in the Table 22. Figure 22. Control/Status Register D31 Upper Word D16 D15 Lower Word D0 Offset SCB Command Word SCB Status Word 00h System Control Block General Pointer 04h PORT 08h EEPROM Control Register Flash Control Register 0Ch Management Data Interface (MDI) Control Register 10h Receive Direct Memory Access Byte Count 14h PMDR Flow Control Register Reserved 18h Reserved General Status General Control 1Ch Reserved 20h Command Block Pointer 24h Reserved 28h Reserved 2Ch Function Event Register 30h Function Event Mask Register 34h Function Present State Register 38h Force Event Register 3Ch NOTE: In Figure 22 above, SCB is defined as the System Control Block of the 82551QM, and PMDR is defined as the Power Management Driver Register. SCB Status Word: The 82551QM places the status of its Command and Receive units and interrupt indications in this register for the CPU to read. SCB Command Word: The CPU places commands for the Command and Receive units in this register. Interrupts are also acknowledged in this register. SCB General Pointer: The SCB General Pointer register points to various data structures in main memory depending on the current SCB Command word. PORT Interface: The PORT interface allows the CPU to reset the 82551QM, force the 82551QM to dump information to main memory, or perform an internal self test. Flash Control Register: The Flash Control register allows the CPU to enable writes to an external Flash. EEPROM Control Register: The EEPROM Control register allows the CPU to read and write to an external EEPROM. Datasheet 65 82551QM — Networking Silicon MDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit (or an external PHY component) through the Management Data Interface. Receive DMA Byte Count: The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA. Flow Control Register: This register holds the flow control threshold value and indicates the flow control commands to the 82551QM. PMDR: The Power Management Driver Register provides an indication in memory and I/O space that a wake-up interrupt has occurred. General Control: The General Control register allows the 82551QM to enter the deep power- down state and provides the ability to disable the Clock Run functionality. General Status: The General Status register describes the status of the 82551QM’s duplex mode, speed, and link. Function Event: The Function Event Register is used for CardBus power management applications and specifies the event that changed the status. Function Event Mask: The Function Event Mask register masks the CSTSCHG signal assertion for specified events. Function Present State: The Function Present State register reflects the current state of each condition that may cause a status change or interrupt. Force Event: The Force Event register simulates the status change events for troubleshooting purposes. 10.1.1 System Control Block Status Word The System Control Block (SCB) Status Word contains status information relating to the 82551QM’s Command and Receive units. Table 27. System Control Block Status Word Bits Name Description Command Unit (CU) Executed. The CX bit indicates that the CU has 15 CX completed executing a command with its interrupt bit set. Frame Received. The FR bit indicates that the Receive Unit (RU) has 14 FR finished receiving a frame. CU Not Active. The CNA bit is set when the CU is no longer active and in 13 CNA either an idle or suspended state. Receive Not Ready. The RNR bit is set when the RU is not in the ready 12 RNR state. This may be caused by an RU Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame Descriptor. Management Data Interrupt. The MDI bit is set when a Management Data Interface read or write cycle has completed. The management data interrupt 11 MDI is enabled through the interrupt enable bit (bit 29 in the Management Data Interface Control register in the CSR). Software Interrupt. The SWI bit is set when software generates an 10 SWI interrupt. 9 Reserved This bit is reserved and should be set to 0b. 66 Datasheet Networking Silicon — 82551QM Table 27. System Control Block Status Word Bits Name Description 8FCP Flow Control Pause. The FCP bit is used as the flow control pause bit. Command Unit Status. The CUS field contains the status of the Command 7:6 CUS Unit. 5:2 RUS Receive Unit Status. The RUS field contains the status of the Receive Unit. 1:0 Reserved These bits are reserved and should be set to 0b. 10.1.2 System Control Block Command Word Commands for the 82551QM’s Command and Receive units are placed in this register by the CPU. Table 28. System Control Block Command Word Bits Name Description Specific Interrupt Mask. Setting this bit to 1b causes the 82551QM to stop Specific 31:26 generating an interrupt (in other words, de-assert the INTA# signal) on the Interrupt Mask corresponding event. Software Generated Interrupt. Setting this bit to 1b causes the 82551QM 25 SI to generate an interrupt. Writing a 0b to this bit has no effect. Interrupt Mask. If the Interrupt Mask bit is set to 1b, the 82551QM will not 24 M assert its INTA# pin. The M bit has higher precedence that the Specific Interrupt Mask bits and the SI bit. 23:20 CUC Command Unit Command. This field contains the CU command. 19:16 RUC Receive Unit Command. This field contains the RU command. 10.1.3 System Control Block General Pointer The System Control Block (SCB) General Pointer is a 32-bit field that points to various data structures depending on the command in the CU Command or RU Command field. 10.1.4 PORT The PORT interface allows software to perform certain control functions on the 82551QM. This field is 32 bits wide: • Address and Data (bits 32:4) • PORT Function Selection (bits 3:0) The 82551QM supports four PORT commands: Software Reset, Self-test, Selective Reset, and Dump. 10.1.5 Flash Control Register The Flash Control Register is a 32-bit field that allows access to an external Flash device. Datasheet 67 82551QM — Networking Silicon 10.1.6 EEPROM Control Register The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external EEPROM. 10.1.7 Management Data Interface Control Register The Management Data Interface (MDI) Control register is a 32-bit field and is used to read and write bits from the MDI. Table 29. MDI Control Register Bits Description 31:30 These bits are reserved and should be set to 0b. Interrupt Enable. When this bit is set to 1b by software, the 82551QM asserts an interrupt to 29 indicate the end of an MDI cycle. Ready. This bit is set to 1b by the 82551QM at the end of an MDI transaction. Software should 28 set this bit to 0 at the same time the command is written. Opcode. These bits define the opcode: 01 for MDI write and 10 for MDI read. All other values 27:26 (00 and 11) are reserved. 25:21 PHY Address. This field of bits contains the PHY address. 20:16 PHY Register Address. This field of bits contains the PHY Register Address. Data. In a write command, software places the data bits in this field, and the 82551QM 15:0 transfers the data to the PHY unit. During a read command, the 82551QM reads these bits serially from the PHY unit, and software reads the data from this location. 10.1.8 Receive Direct Memory Access Byte Count The Receive DMA Byte Count register keeps track of how many bytes of receive data have been passed into host memory via DMA. 10.1.9 Flow Control Register The Flow Control Register contains the following fields: • Flow Control Command The Flow Control Command field describes the action of the flow control process (for example, pause, on, or off). • Flow Control Threshold The Flow Control Threshold field contains the threshold value (in other words, the number of free bytes in the Receive FIFO). 68 Datasheet Networking Silicon — 82551QM 10.1.10 Power Management Driver Register The 82551QM provides an indication in memory and I/O space that a wake-up event has occurred. It is located in the Power Management Driver (PMDR). The PMDR is used for CardBus mode only. Table 30. Power Management Driver Register Bits Default Read/Write Description Link Status Change Indication. The link status change bit is set 31 0b Read/Clear following a change in link status and is cleared by writing a 1b to it. Magic Packet*. This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable bit in the configuration 30 0b Read/Clear command and the PME Enable bit in the Power Management Control/ Status Register. This bit is cleared by writing 1b to it. Interesting Packet. This bit is set when an “interesting” packet is 29 0b Read/Clear received. Interesting packets are defined by the 82551QM packet filters. This bit is cleared by writing 1b to it. 28 0b Read Only Reserved. This bit is reserved and should be set to 0b. GCL Enable. This bit is set to 1b when the 82551QM is in GCL mode (in other words, the 82551QM handles management packets). If the 27 0b Read Only GCL Enable bit is set to 0b, the 82551QM does not handle management packets. In this mode, management packets are handled by an external TCO controller. 26 0b Read/Clear Force TCO Indication. This bit is reserved for testing. TCO Request. This bit is set to 1b when the 82551QM is busy with 25 0b Read/Clear TCO activity. PME Status. This bit is a reflection of the PME Status bit in the Power Management Control/Status Register (PMCSR). It is set upon a wake- up event and is independent of the PME Enable bit. 24 0b Read/Clear This bit is cleared by writing 1b to it. This also clears the PME Status bit in the PMCSR and de-asserts the PME signal. In a CardBus system, if 1b is written to this field, the General Wake-up (GWAKE) bit in the Function Event register is cleared. Datasheet 69 82551QM — Networking Silicon Note: The PMDR is initialized at ALTRST# reset only. 10.1.11 General Control Register The General Control register is a byte register and is described below. The General Control register is used in CardBus mode only. Table 31. General Control Register Bits Default Read/Write Description 7:2 000000b Read Only Reserved. These bits are reserved and should be set to 000000b. Deep Power-Down on Link Down Enable. If a 1b is written to this field, the 82551QM may enter a deep power-down state (sub-3 mA) in the D2 and D3 power states while the link is down. 1 0b Read/Write In this state, the 82551QM does not keep link integrity. This state is not supported for point-to-point connection of two end stations. Clock Run Signal Disable. If this bit is set to 1b, then the 82551QM always requests the PCI clock signal. This mode can be used to 0 0b Read/Write overcome potential receive overruns caused by Clock Run signal latencies over 5 µs. 10.1.12 General Status Register The General Status register is used in CardBus mode only and is a byte register that indicates the link status of the 82551QM. Table 32. General Status Register Bits Default Read/Write Description 7:3 00000b Read Only Reserved. These bits are reserved and should be set to 00000b. Duplex Mode. This bit indicates the wire duplex mode: full duplex (1b) 2 -- Read Only or half duplex (0b). Speed. This bit indicates the wire speed: 100 Mbps (1b) or 10 Mbps 1 -- Read Only (0b). Link Status Indication. This bit indicates the status of the link: valid 0 0b Read Only (1b) or invalid (0b). 10.1.13 Ethernet Card Status Change Registers The PME signal used in PCI systems is replaced by the Card Status Change (CSTSCHG) signal in CardBus systems. The CardBus specification requires the use of control/status registers related to CSTSCHG. There are four event related registers. 1. Function Event Register: Specifies the event that changed status 2. Function Event Mask Register: Masks CSTSCHG signal assertion for specified events 3. Function Present State Register: Reflects the current state of each condition that may cause a status change or interrupt 4. Force Event Register: Simulates status change events for troubleshooting purposes 70 Datasheet Networking Silicon — 82551QM These CardBus registers are used by software to determine which event has occurred, to manage the event, and to control the CSTSCHG signal. The 82551QM supports only the interrupt and general wake-up event bits in the card status change 1 registers . These registers complement the PCI Power Management registers in a non-ACPI compliant OS. They are initialized by a power-up reset on the ALTRST# pin. The location of these registers should be specified within the configuration space pointing to offset address 30h of the CSR. Note: Access to the CSTSCHG registers in PCI mode is not allowed. 10.1.13.1 LAN Function Event Register The Function Event register specified the event that changed the status. Table 33. LAN Function Event Register Bits Function Default Description 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification. This bit is used for as the interrupt bit. It is set when the Ethernet interrupt source is set, regardless of the mask value. It is cleared when 15 INTR 0b the OS writes 1b to this field and the interrupt source has been serviced. Writing 0b to this field has no effect. 14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification. This bit is used for general wake-up. It is set when the Ethernet wake- up source is set, regardless of the mask value. Writing 1b to this field 4 GWAKE 0b clears this bit and the PME Status bit in the PMCSR. Writing 0b to this field has no effect. Note that writing 1b to the PME Status bit in the PMCSR has the same effect. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 2 Reserved 0b Reserved. 1 Reserved 0b Reserved. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. 1. For a combination LAN/modem card, the 82551QM implements two independent sets of card status change registers. Each set controls its function separately. Datasheet 71 82551QM — Networking Silicon 10.1.13.2 LAN Function Event Mask Register The Function Event Mask register masks CSTSCHG and INTA# assertion. Table 34. LAN Function Event Mask Register Bits Function Default Description 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification. This bit is the interrupt mask. When this bit equals 0b, it masks the Ethernet function INTA# line but has no effect on the LAN Function Event register. The Ethernet function can assert the INTA# signal only 15 INTR 0b when both fields are enabled: the interrupt bit and the “M” bit in the System Control Block (SCB) register within the CSR space. The interrupt mask bit affects the INTA# masking. This bit is the wake-up mask. When this bit equals 0b, it masks the 14 WKUP 0b Ethernet function CSTSCHG signal but has no effect on the LAN Function Event register. This bit is dependent on bit 4 of this register. 13:7 Reserved 0 Bits [13:7] are reserved in the CardBus Specification. PWM These bits are used for Pulse Width Modulation Binary Audio Enable 6:5 0 BAM (PWM BAM). Note that the PWM BAM bits are not applicable for LAN. This bit is the general wake-up mask. When this bit equals 0b, it masks the Ethernet function wake-up events towards the CSTSCHG signal. It has no effect on the LAN Function Event register. The 82551QM can 4 GWAKE 0b assert the CSTSCHG signal in the following configuration of masked bits: wake-up bit AND general wake-up bit, or PME Enable bit in the PMCSR register only. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 2 Reserved 0b Reserved. 1 Reserved 0b Reserved. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. 10.1.13.3 LAN Function Present State Register The Function Present State register reflects the current state of the LAN function that may cause a status change or interrupt. Table 35. LAN Function Present State Register Bits Function Default Description 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification. This bit is used for interrupts. It reflects the current state of the Ethernet source of the interrupt regardless of the mask value. It is set when the 15 INTR 0 Ethernet function has a pending interrupt and cleared when the software driver acknowledges all active interrupts through the SCB Command Word. 14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification. This bit is used for general wake-up. It reflects the current state of the Ethernet source of CSTSCHG. It is a logical OR result of the gated three most significant bits in the PMDR: Link Status Change, Magic Packet, and Interesting Packet. The Link Status change bit is gated by 4 GWAKE 0 the Link Status Change Wake Enable bit in the Configuration command. The Magic Packet bit is gated by the Magic Packet Wake- up disable bit in the Configuration command. The Interesting Packet bit is gated by the programmable filter command. 72 Datasheet Networking Silicon — 82551QM Table 35. LAN Function Present State Register Bits Function Default Description 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 2 Reserved 0b Reserved. 1 Reserved 0b Reserved. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. 10.1.13.4 LAN Force Event Register The Force Event register simulates status change events for troubleshooting purposes. This register provides the ability to simulate events by forcing values into the Function Event register. Table 36. LAN Force Event Register Bits Function Default Description 31:16 Reserved 0 Bits [31:16] are reserved in the CardBus Specification. This bit is used for interrupts. Writing 1b in this field will set the interrupt 15 INTR 0 bit in the LAN Function Event register. If the INTA# pin is not masked, then it will also be activated. Writing 0b has no effect. 14:5 Reserved 0 Bits [14:5] are reserved in the CardBus Specification. This bit is used for general wake-up. Writing 1b in this field will set the 4 GWAKE 0 CSTSCHG bit in the LAN Function Event register. If the CSTSCHG pin is not masked, then it will also be activated. Writing 0b has no effect. 3:0 Reserved 0 Bits [3:0] are reserved in the CardBus Specification. 10.2 Statistical Counters The 82551QM provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82551QM when it completes the processing of a frame (that is, when it has completed transmitting a frame on the link or when it has completed receiving a frame). The Statistical Counters are reported to the software on demand by issuing the Dump Statistical Counters command or Dump and Reset Statistical Counters command in the SCB Command Unit Command (CUC) field. Table 37. Statistical Counters ID Counter Description This counter contains the number of frames that were transmitted properly on the link. It is updated only after the 0 Transmit Good Frames actual transmission on the link is completed, not when the frame was read from memory, as is done for the Transmit Command Block status. This counter contains the number of frames that were not Transmit Maximum Collisions 4 transmitted because they encountered the configured (MAXCOL) Errors maximum number of collisions. This counter contains the number of frames that were not Transmit Late Collisions 8 transmitted due to an encountered collision after the (LATECOL) Errors configured slot time. Datasheet 73 82551QM — Networking Silicon Table 37. Statistical Counters ID Counter Description A transmit underrun occurs because the system bus cannot keep up with the transmission. This counter contains the number of frames that were either not transmitted or 12 Transmit Underrun Errors retransmitted due to a transmit DMA underrun. If the 82551QM is configured to retransmit on underrun, this counter may be updated multiple times for a single frame. This counter contains the number of frames that were 16 Transmit Lost Carrier Sense (CRS) transmitted by the 82551QM despite the fact that it detected the de-assertion of CRS during the transmission. This counter contains the number of frames that were 20 Transmit Deferred deferred before transmission due to activity on the link. This counter contains the number of transmitted frames that 24 Transmit Single Collisions encountered one collision. This counter contains the number of transmitted frames that 28 Transmit Multiple Collisions encountered more than one collision. This counter contains the total number of collisions that were 32 Transmit Total Collisions encountered while attempting to transmit. This count includes late collisions and frames that encountered MAXCOL. This counter contains the number of frames that were received properly from the link. It is updated only after the 36 Receive Good Frames actual reception from the link is completed and all the data bytes are stored in memory. This counter contains the number of aligned frames discarded because of a CRC error. This counter is updated, if needed, 40 Receive CRC Errors regardless of the Receive Unit state. The Receive CRC Errors counter is mutually exclusive of the Receive Alignment Errors and Receive Short Frame Errors counters. This counter contains the number of frames that are both misaligned (for example, CRS de-asserts on a non-octal boundary) and contain a CRC error. The counter is updated, if 44 Receive Alignment Errors needed, regardless of the Receive Unit state. The Receive Alignment Errors counter is mutually exclusive of the Receive CRC Errors and Receive Short Frame Errors counters. This counter contains the number of good frames discarded due to unavailability of resources. Frames intended for a host whose Receive Unit is in the No Resources state fall into this 48 Receive Resource Errors category. If the 81551QM is configured to Save Bad Frames and the status of the received frame indicates that it is a bad frame, the Receive Resource Errors counter is not updated. This counter contains the number of frames known to be lost because the local system bus was not available. If the traffic 52 Receive Overrun Errors problem persists for more than one frame, the frames that follow the first are also lost; however, because there is no lost frame indicator, they are not counted. This counter contains the number of frames that encountered 56 Receive Collision Detect (CDT) collisions during frame reception. This counter contains the number of received frames that are shorter than the minimum frame length. The Receive Short Frame Errors counter is mutually exclusive to the Receive 60 Receive Short Frame Errors Alignment Errors and Receive CRC Errors counters. A short frame will always increment only the Receive Short Frame Errors counter. 74 Datasheet Networking Silicon — 82551QM Table 37. Statistical Counters ID Counter Description This counter contains the number of Flow Control frames transmitted by the 82551QM. This count includes both the 64 Flow Control Transmit Pause Xoff frames transmitted and Xon (PAUSE(0)) frames transmitted. This counter contains the number of Flow Control frames 68 Flow Control Receive Pause received by the 82551QM. This count includes both the Xoff frames received and Xon [PAUSE(0)] frames received. This counter contains the number of MAC Control frames received by the 82551QM that are not Flow Control Pause 72 Flow Control Receive Unsupported frames. These frames are valid MAC control frames that have the predefined MAC control Type value and a valid address but has an unsupported opcode. This counter contains the number of TCO packets received by 76 Receive TCO Frames the 82551QM. 78 Transmit TCO Frames This counter contains the number of TCO packets transmitted. The Statistical Counters are initially set to zero by the 82551QM after reset. They cannot be preset to anything other than zero. The 82551QM increments the counters by internally reading them, incrementing them and writing them back. This process is invisible to the CPU and PCI bus. In addition, the counters adhere to the following rules: • The counters are wrap-around counters. After reaching FFFFFFFFh the counters wrap around to 0. • The 82551QM updates the required counters for each frame. It is possible for more than one counter to be updated as multiple errors can occur in a single frame. • The counters are 32 bits wide and their behavior is fully compatible with the IEEE 802.1 standard. The 82551QM supports all mandatory and recommend statistics functions through the status of the receive header and directly through these Statistical Counters. The CPU can access the counters by issuing a Dump Statistical Counters SCB command. This provides a “snapshot”, in main memory, of the internal 82551QM statistical counters. The 82551QM supports 21 counters. The dump could consist of either 16 or 21 counters, depending on the status of the Extended Statistics Counters and TCO Statistics configuration bits in the Configuration command. 10.3 Modem Control/Status Registers Access to modem based memory or I/O ports are mapped to a modem cycle with the lowest 16 addresses of the PCI address space that is mapped to the modem address bus. This is connected to FLA3:0. Datasheet 75 82551QM — Networking Silicon 10.3.1 Modem Base Memory Addressing The modem base memory addressing is an 8-byte address space. There are three types of address spaces: 1. Modem chipset address space: 0h to Fh 2. Modem function address space: 80h to FFh (implemented in 82551QM) 3. Modem CIS address space: 100h to 1FFh (loaded from EEPROM) Table 38. Modem Based Memory Address Registers Byte Offset Register Description 0h:7h Modem controller mimic port, ISA address space 0:7 Modem controller Resource Management Port (RMP), ISA 8h:Fh address space 8:15 80h:83h Modem Control Register: Reset[0], Central Site Mode[1] E0h:E3h Reserved F0h:F3h Modem Function Event Register F4h:F7h Modem Function Mask Register F8h:FBh Modem Function Present Register FCh:FFh Modem Force Function Event Register 100h:1FFh CIS Area (loaded from the EEPROM) 10.3.2 Modem Base I/O Addressing The modem base I/O addressing is an 8-byte address space. During I/O cycles, accesses to the modem port are byte accesses. FLA3 is kept low while FLA2:0 are mapped according to the PCI byte address offset. Table 39. Modem Based I/O Address Registers Byte Offset Register Description 0h:7h Venus MIMIC port, ISA address space 7:0. 10.3.3 Modem CardBus CSTCHG Registers The modem CardBus CSTCHG registers are used in CardBus mode only. There are four event related registers. The CardBus software uses the registers to determine which event has occurred and manage the event and to control the CSTSCHG signal. The 82551QM supports only the interrupt and general wake-up event bits in the CSTSCHG registers. These registers complement the PCI Power Management registers and are used with non-ACPI compliant OS. It is initialized by power-up reset driven on the ALTRST# pin. 10.3.3.1 Modem Function Event Register The Modem Function Event register specifies the event that changed its status. It is identical to the Ethernet Function Event register described in Section 10.1.13.1, “LAN Function Event Register”. 76 Datasheet Networking Silicon — 82551QM 10.3.3.2 Modem Function Event Mask Register The Modem Function Event Mask register masks CSTSCHG and INTA# assertion as listed in Table 40. Table 40. Modem Function Event Mask Register Bits Function Default Description 31:16 Reserved 0 Bits 31:16 are reserved in the CardBus Specification. This bit is the interrupt mask. When this bit equals 0b, it masks the modem function INTA# line but has no effect on the Modem Function Event register. The modem function can assert the INTA# signal only when both fields are enabled: the interrupt bit and the modem control 15 INTR 0b bit in the System Control Block (SCB) register within the CSR space. The interrupt mask bit affects the INTA# masking only after the OS has set this register. Thus, on legacy systems that do not access the status change registers, the modem INTA# signal is not masked by the interrupt. This bit is the wake-up mask. When this bit equals 0b, it masks the 14 WKUP 0b modem function CSTSCHG signal but has no effect on the Function Event register. This bit is dependent on bit 4 of this register. 13:7 Reserved 0 Bits 13:7 are reserved in the CardBus Specification. PWM These bits are used for Pulse Width Modulation Binary Audio Enable. 6:5 0 BAM (PWM BAM). This bit is the general wake-up mask. When this bit equals 0b, it masks the modem function wake-up events towards the CSTSCHG signal. It has no effect on the Modem Function Event register. The can assert 4 GWAKE 0b the CSTSCHG signal in the following configuration of masked bits: wake-up bit AND general wake-up bit, or PME Enable bit in the PMCSR register only. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. 2 Reserved 0b Reserved. 1 Reserved 0b Reserved. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. 10.3.3.3 Modem Function Present State Register The Modem Function Present State register specifies the current state of an event’s sources as listed in Table 41. Table 41. Modem Function Present State Register Bits Function Default Description 31:16 Reserved 0 Bits 31:16 are reserved in the CardBus Specification. This bit is used for interrupts. It reflects the current state of the Modem 15 INTR 0 Interrupt (MINT) input pin from the modem. 14:5 Reserved 0 Bits 14:5 are reserved in the CardBus Specification. This bit is used for general wake-up. It reflects the current inverse state 4 GWAKE 0 of the Modem Ring (MRING#) input pin from the modem. 3 Reserved 0b Bit 3 is reserved in the CardBus Specification. Datasheet 77 82551QM — Networking Silicon Table 41. Modem Function Present State Register Bits Function Default Description 2 Reserved 0b Reserved. 1 Reserved 0b Reserved. 0 Reserved 0b Bit 0 is reserved in the CardBus Specification. 10.3.3.4 Modem Force Event Register The Modem Force Event register simulates status change events for troubleshooting purposes. It is identical to the Ethernet Force Event register described in Section 10.1.13.4, “LAN Force Event Register”. 78 Datasheet Networking Silicon — 82551QM 11.0 PHY Unit Registers The 82551QM provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows: SC - self cleared RO - read only E - EEPROM setting affects content LL - latch low LH - latch high 11.1 MDI Registers 0 - 7 11.1.1 Register 0: Control Register Table 42. Register 0: Control Bit(s) Name Description Default R/W 15 Reset This bit sets the status and control register of the PHY to 0RW their default states and is self-clearing. The PHY returns SC a value of one until the reset process has completed and accepts a read or write transaction. 1 = PHY Reset 14 Loopback This bit enables loopback of transmit data nibbles from 0RW the TXD[3:0] signals to the receive data path. The PHY unit’s receive circuitry is isolated from the network. Note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of “dead time.” Note also that the loopback configuration bit takes priority over the Loopback MDI bit. 1 = Loopback enabled 0 = Loopback disabled (Normal operation) 13 Speed Selection This bit controls speed when Auto-Negotiation is disabled 1RW and is valid on read when Auto-Negotiation is disabled. 1 = 100 Mbps 0 = 10 Mbps 12 Auto-Negotiation This bit enables Auto-Negotiation. Bits 13 and 8, Speed 1RW Enable Selection and Duplex Mode, respectively, are ignored when Auto-Negotiation is enabled. 1 = Auto-Negotiation enabled 0 = Auto-Negotiation disabled Datasheet 79 82551QM — Networking Silicon Table 42. Register 0: Control Bit(s) Name Description Default R/W 11 Power-Down This bit sets the PHY unit into a low power mode. In low 0RW power mode, the PHY unit consumes no more than 30 mA. 1 = Power-Down enabled 0 = Power-Down disabled (Normal operation) 10 Reserved This bit is reserved and should be set to 0b. 0 RW 9 Restart Auto- This bit restarts the Auto-Negotiation process and is self- 0RW Negotiation clearing. SC 1 = Restart Auto-Negotiation process 8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation 0RW is disabled. If the PHY reports that it is only able to operate in one duplex mode, the value of this bit shall correspond to the mode which the PHY can operate. When the PHY is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit, bit 8. 1 = Full Duplex 0 = Half Duplex 7 Collision Test This bit will force a collision in response to the assertion 0RW of the transmit enable signal. 1 = Force COL 0 = Do not force COL 6:0 Reserved These bits are reserved and should be set to 0b. 0 RW 11.1.2 Register 1: Status Register Table 43. Register 1: Status Bit(s) Name Description Default R/W 15 Reserved This bit is reserved and should be set to 0b. 0 RO E 14 100BASE-TX Full 1 = PHY able to perform full duplex 100BASE-TX 1 RO Duplex 13 100 Mbps Half 1 = PHY able to perform half duplex 100BASE-TX 1 RO Duplex 12 10 Mbps Full 1 = PHY able to operate at 10Mbps in full duplex 1RO Duplex mode 11 10 Mbps Half 1 = PHY able to operate at 10 Mbps in half duplex 1RO Duplex mode 10:7 Reserved These bits are reserved and should be set to 0b. 0 RO 6 Management 0 = PHY will not accept management frames with 0RO Frames Preamble preamble suppressed Suppression 5 Auto-Negotiation 1 = Auto-Negotiation process completed 0RO Complete 0 = Auto-Negotiation process has not completed 4 Remote Fault 0 = No remote fault condition detected 0 RO 80 Datasheet Networking Silicon — 82551QM Table 43. Register 1: Status Bit(s) Name Description Default R/W 3 Auto-Negotiation 1 = PHY is able to perform Auto-Negotiation 1 RO Ability 2 Link Status 1 = Valid link has been established 0RO 0 = Invalid link detected LL 1 Jabber Detect 1 = Jabber condition detected 0RO 0 = No jabber condition detected LH 0 Extended 1 = Extended register capabilities enabled 1 RO Capability 11.1.3 Register 2: PHY Identifier Register Table 44. Register 2: PHY Identifier Bit(s) Name Description Default R/W 15:0 PHY ID (high Value: 02A8h -- RO byte) 11.1.4 Register 3: PHY Identifier Register Table 45. Register 3 PHY Identifier Bit(s) Name Description Default R/W 15:0 PHY ID (low byte) Value: 0154h -- RO 11.1.5 Register 4: Auto-Negotiation Advertisement Register Table 46. Register 4: Auto-Negotiation Advertisement Bit(s) Name Description Default R/W 15 Next Page Constant 0 = Transmitting primary capability data 0RO page 14 Reserved This bit is reserved and should be set to 0b. 0 RO 13 Remote Fault 1 = Indicate link partner’s remote fault 0RW 0 = No remote fault 12:5 Technology Ability Technology Ability Field is an 8-bit field containing 00101111 RW Field information indicating supported technologies specific to the selector field value. 4:0 Selector Field The Selector Field is a 5-bit field identifying the type of 00001 RO message to be sent via Auto-Negotiation. This field is read only in the 82551QM and contains a value of 00001b, IEEE Standard 802.3. Datasheet 81 82551QM — Networking Silicon 11.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Table 47. Auto-Negotiation Link Partner Ability Bit(s) Name Description Default R/W 15 Next Page This bit reflects the PHY’s link partner’s Auto- -- RO Negotiation ability. 14 Acknowledge This bit is used to indicate that the 82551QM’s PHY -- RO unit has successfully received its link partner’s Auto- Negotiation advertising ability. 13 Remote Fault This bit reflects the PHY’s link partner’s Auto- -- RO Negotiation ability. 12:5 Technology Ability This bit reflects the PHY’s link partner’s Auto- -- RO Field Negotiation ability. 4:0 Selector Field This bit reflects the PHY’s link partner’s Auto- -- RO Negotiation ability. 11.1.7 Register 6: Auto-Negotiation Expansion Register Table 48. Register 6: Auto-Negotiation Expansion Bit(s) Name Description Default R/W 15:5 Reserved These bits are reserved and should be set to 0b. 0 RO 4 Parallel Detection 1 = Fault detected via parallel detection (multiple link 0RO Fault fault occurred) SC 0 = No fault detected via parallel detection LH This bit will self-clear on read 3 Link Partner Next 1 = Link Partner is Next Page able 0RO page Able 0 = Link Partner is not Next Page able 2 Next Page Able 1 = Local drive is Next Page able 0RO 0 = Local drive is not Next Page able 1 Page Received 1 = New Page received 0RO 0 = New Page not received SC This bit will self-clear on read. LH 0 Link Partner Auto- 1 = Link Partner is Auto-Negotiation able 0RO Negotiation Able 0 = Link Partner is not Auto-Negotiation able 11.2 MDI Registers 8 - 15 Registers 8 through 15 are reserved for IEEE. 82 Datasheet Networking Silicon — 82551QM 11.3 MDI Register 16 - 31 11.3.1 Register 16: PHY Unit Status and Control Register Table 49. PHY Unit Status and Control Bit(s) Name Description Default R/W 15:14 Reserved These bits are reserved and should be set to 00b 00 RW 13 Carrier Sense This bit enables the disconnect function. 0RW Disconnect 1 = Disconnect function enabled Control 0 = Disconnect function disabled 12 Transmit Flow This bit enables Transmit Flow Control 0RW Control Disable 1 = Transmit Flow Control enabled 0 = Transmit Flow Control disabled 11 Receive De- This bit indicates receipt status of the 100BASE-TX -- RO Serializer In-Sync receive de-serializer in-sync. Indication 10 100BASE-TX This bit indicates the power state of 100BASE-TX 1RO Power-Down PHY unit. 1 = Power-Down 0 = Normal operation 9 10BASE-T This bit indicates the power state of 100BASE-TX 1RO Power-Down PHY unit. 1 = Power-Down 0 = Normal operation 8 Polarity This bit indicates 10BASE-T polarity. -- RO 1 = Reverse polarity 0 = Normal polarity 7:2 Reserved These bits are reserved and should be set to 0B. 000000 RO 1 Speed This bit indicates the Auto-Negotiation result. -- RO 1 = 100 Mbps 0 = 10 Mbps 0 Duplex Mode This bit indicates the Auto-Negotiation result. -- RO 1 = Full Duplex 0 = Half Duplex 11.3.2 Register 17: PHY Unit Special Control Register Table 50. Register 17: PHY Unit Special Control Bit(s) Name Description Default R/W 15 Scrambler By- 1 = By-pass Scrambler 0RW pass 0 = Normal operations 14 By-pass 4B/5B 1 = 4 bit to 5 bit by-pass 0RW 0 = Normal operation 13 Force Transmit H- 1 = Force transmit H-pattern 0RW Pattern 0 = Normal operation Datasheet 83 82551QM — Networking Silicon Table 50. Register 17: PHY Unit Special Control Bit(s) Name Description Default R/W 12 Force 34 1 = Force 34 transmit pattern 0RW Transmit Pattern 0 = Normal operation 11 Good Link 1 = 100BASE-TX link good 0RW 0 = Normal operation 10 Reserved This bit is reserved and should be set to 0b. 0 RW 9 Transmit Carrier 1 = Transmit Carrier Sense disabled 0RW Sense Disable 0 = Transmit Carrier Sense enabled 8 Disable Dynamic 1 = Dynamic Power-Down disabled 0RW Power-Down 0 = Dynamic Power-Down enabled (normal) 7 Auto-Negotiation 1 = Auto-Negotiation loopback 0RW Loopback 0 = Auto-Negotiation normal mode 6 MDI Tri-State 1 = MDI Tri-state (transmit driver tri-states) 0RW 0 = Normal operation 5 Filter By-pass 1 = By-pass filter 0RW 0 = Normal filter operation 4 Auto Polarity 1 = Auto Polarity disabled 0RW Disable 0 = Normal polarity operation 3 Squelch Disable 1 = 10BASE-T squelch test disable 0RW 0 = Normal squelch operation 2 Extended 1 = 10BASE-T Extended Squelch control enabled 0RW Squelch 0 = 10BASE-T Extended Squelch control disabled 1 Link Integrity 1 = Link disabled 0RW Disable 0 = Normal Link Integrity operation 0 Jabber Function 1 = Jabber disabled 0RW Disable 0 = Normal Jabber operation 11.3.3 Register 18: PHY Address Register Table 51. Register 18: PHY Address Bit(s) Name Description Default R/W 15:5 Reserved These bits are reserved and should be set to a 0RO constant ‘0’ 4:0 PHY Address These bits are set to the PHY’s address, 00001b. 1 RO 11.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Table 52. Register 19: 100BASE-TX Receive False Carrier Counter Bit(s) Name Description Default R/W 15:0 Receive False These bits are used for the false carrier counter. -- RO Carrier SC 84 Datasheet Networking Silicon — 82551QM 11.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Table 53. Register 20: 100BASE-TX Receive Disconnect Counter Bit(s) Name Description Default R/W 15:0 Disconnect Event This field contains a 16-bit counter that increments for -- RO each disconnect event. The counter freezes when full SC and self-clears on read 11.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Table 54. Register 21: 100BASE-TX Receive Error Frame Counter Bit(s) Name Description Default R/W 15:0 Receive Error This field contains a 16-bit counter that increments -- RO Frame once per frame for any receive error condition (such SC as a symbol error or premature end of frame) in that frame. The counter freezes when full and self-clears on read. 11.3.7 Register 22: Receive Symbol Error Counter Table 55. Register 22: Receive Symbol Error Counter Bit(s) Name Description Default R/W 15:0 Symbol Error This field contains a 16-bit counter that increments for -- RO Counter each symbol error. The counter freezes when full and SC self-clears on read. In a frame with a bad symbol, each sequential six bad symbols count as one. 11.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Table 56. Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit(s) Name Description Default R/W 15:0 Premature End of This field contains a 16-bit counter that increments for -- RO Frame each premature end of frame event. The counter SC freezes when full and self-clears on read. 11.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Table 57. Register 24: 10BASE-T Receive End of Frame Error Counter Bit(s) Name Description Default R/W 15:0 End of Frame This is a 16-bit counter that increments for each end -- RO Counter of frame error event. The counter freezes when full SC and self-clears on read. Datasheet 85 82551QM — Networking Silicon 11.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Table 58. Register 25: 10BASE-T Transmit Jabber Detect Counter Bit(s) Name Description Default R/W 15:0 Jabber Detect This is a 16-bit counter that increments for each -- RO Counter jabber detection event. The counter freezes when full SC and self-clears on read. 11.3.11 Register 26: Equalizer Control and Status Register Table 59. Register 26: Equalizer Control and Status Bit(s) Name Description Default R/W 15:0 RFU Reserved for Future Use -- RW 11.3.12 Register 27: PHY Unit Special Control Register Table 60. Register 27: PHY Unit Special Control Bit(s) Name Description Default R/W 15:3 Reserved These bits are reserved and should be set to 0b. 0 RW 2:0 LED Switch Value ACTLED# LILED# 000 RW Control 000 Activity Link 001 Speed Collision 010 Speed Link 011 Activity Collision 100 Off Off 101 Off On 110 On Off 111 On On 86 Datasheet Networking Silicon — 82551QM 11.3.13 Register 28: MDI/MDI-X Control Register Table 61. Register 28: MDI/MDI-X Control Bit(s) Name Definition Default R/W 15:8 Reserved Reserved for future use. Set these bits to 0. 0 R/W Enables the MDI/MDI-X feature (writing to this bit overwrites the default value). Auto Switch 7 0R/W Enable 1 = Enabled. 0 = Disabled. Manual switch (valid only if bit 7 is set to 0). 6Switch 1 = Forces the port to be MDI-X (cross-over). 0R/W 0 = Forces the port to be MDI (straight-through) Indicates the state of the MDI pair. 5Status 1 = MDI-X (cross-over). 0RO 0 = MDI (straight-through). Indicates when the correct configuration is achieved. Auto Switch 4 1 = Resolution algorithm has completed. 1RO Complete 0 = Resolution algorithm has not completed. Defines the minimum slot time the algorithm uses in order to switch between one configuration or another. 3:0 Resolution Timer 0000 R/W 0000 = 80ms. 1111 = 105ms. 11.3.14 Register 29: Hardware Integrity Control Register Table 62. Register 29: Hardware Integrity Control Bit(s) Name Description Default R/W 15 HWI Enable This bit enables the HWI feature causing the PHY unit 0RW to enter HWI test mode. 1 = HWI enabled 0 = HWI disabled 14 Ability Check This bit reports the results of the HWI ability check RO and is valid 100 µs after the HWI Enabled bit (bit 15 of this register) is set (1b). 1 = Test passed 0 = Test failed (HWI ability not detected) 13 Test Execute When this bit is set, the PHY unit launches test pulses WO on the wire to determine the distance to the cable’s high or low impedance point. 1 = Execute test 0 = Do not execute test Datasheet 87 82551QM — Networking Silicon Table 62. Register 29: Hardware Integrity Control Bit(s) Name Description Default R/W 12:11 Reserved These bits are reserved and should be set to 0b. 00 RO 10:9 LowZ/HighZ This field of bits indicates either a short (Low Z) or RO open (high Z) on the line. It is valid 100 µs after the Test Execute bit (bit 13 of this register) is set. 1 = Short (low Z) 0 = Open (high Z) 8:0 Distance These bits define the distance to the short or open in RO the cable and are valid 100 µs after the Test Execute bit (bit 13 of this register) is set. The distance is defined in granularities of 80 cm (35 inches). 88 Datasheet Networking Silicon — 82551QM 12.0 Electrical and Timing Specifications Note: This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. 12.1 Absolute Maximum Ratings Maximum ratings are listed below: Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0° C to 85° C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65° C to 140° C Outputs and Supply Voltages (except PCI and SMB) . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.0 V PCI and SMB Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 5.25 V Transmit Data Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 8.0 V Input Voltages (except PCI and SMB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 V to 5.0 V PCI and SMB Input Voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V 6.0 V Note: The 82551IT maximum rating for the Ambient Temperature is -40° C to 85° C. Stresses above the listed absolute maximum ratings may cause permanent damage to the 82551QM device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Datasheet 89 82551QM — Networking Silicon 12.2 DC Specifications Table 63. General DC Specifications Symbol Parameter Condition Min Typical Max Units Notes V Supply Voltage 3.0 3.3 3.6 V CC PCI 4.75 5.0 5.25 V 1 Periphery Clamp V IO Voltage CardBus 3.0 3.3 3.6 V 1 D0 10BASE-T full a 85 100 mA 2 function D1, D2, D3 10BASE-T hot 65 75 mA wake-up enabled Power Supply (10BASE-T) D3 10BASE-T wake- cold 40 50 mA up enabled D3 10BASE-T wake- cold 1.5 2.0 mA up disabled I CC D0a 100BASE-TX full 135 155 mA 2 function D1, D2, D3 100BASE- hot 110 125 mA TX wake-up enabled Power Supply (100BASE-TX) D3 100BASE-TX cold 95 110 mA wake-up enabled D3 100BASE-TX cold 1.5 2.0 mA wake-up disabled NOTES: 1. Preferably, VIO should be 5 V ± 5% in any PCI environment (either 5 V or 3.3 V signaling). If 5 V is not available in a 3.3 V signaling environment, 3.3 V ± 5% may be used instead. In CardBus, V must be IO identical to V . CC 2. Typical current consumption is in nominal operating conditions (V = 3.3 V) and average link activity. CC Maximum current consumption is in maximum V and maximum link activity. CC The 82551QM supports both the PCI and CardBus interface standards. In the PCI mode, it is five volts tolerant and supports both 5 V and 3.3 V signaling environments. Table 64. PCI/CardBus Interface DC Specifications Symbol Parameter Condition Min Max Units Notes V Input High Voltage 0.475V V + 0.5 V IHP CC IO V Input Low Voltage -0.5 0.325V V ILP CC V Input Pull-up Voltage 0.7V V1 IPUP CC V Input Pull-down Voltage 0.2V V1 IPDP CC I Input Leakage Current 0 < V < V ±10 µA 2 ILP IN CC I = -2 mA 2.4 V PCI out V Output High Voltage I = -500 µA 0.9V V OHP out CC I = -150 µA 0.9V V CardBus out CC I = 3 mA, 6 mA 0.55 V 3, PCI out V Output Low Voltage I = 1500 µA 0.1V V OLP out CC I = 700 µA 0.1V V CardBus out CC C Input Pin Capacitance 10 pF 4 INP 90 Datasheet Networking Silicon — 82551QM Table 64. PCI/CardBus Interface DC Specifications C CLK Pin Capacitance 5 12 pF 4 CLKP C IDSEL Pin Capacitance 8 pF 4 IDSEL L Pin Inductance 20 nH 4 PINP PME# Input Leakage I V < V 1mA 5 OFFPME O IO Current NOTES: 1. These values are only applicable in 3.3 V signaling environments. Outside of this limit the input buffer must consume its minimum current. 2. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs. 3. Signals without pull-up resistors have 3 mA low output current; and signals requiring pull-up resistors, 6 mA. The signals requiring pull-up resistors include: FRAME#, TRDY#, IRDY#, DEVSEL#, STOP#, SERR# and PERR#. 4. This value is characterized but not tested. 5. This input leakage current is the maximum allowable leakage into the PME# open drain driver when power is removed from V of the component. This assumes that no event has occurred to cause the device to CC assertion of PME#. Table 65. SMB Interface DC Specifications Symbol Parameter Condition Min Max Units Notes V Input High Voltage 2.1 V + 0.5 V 1 IHS IO V Input Low Voltage -0.5 0.8 V 1 ILS Input Low Leakage I 0 < V < V ±5.0 µA 1 ILS IN CC Current V Output Low Voltage I = 100 µA 0.4 V 1 OLS PDNS Current through pull-up I 100 350 µA 1, 2 PDNS resistor NOTES: 1. SMB outputs (SMB_ALERT#, SMBDATA, and SMBCLK) are open drain. 2. The input leakage current through the pull-up resistor is the maximum allowable leakage into the SMB open drain driver when power is removed from V of the component. It assumes that no event has occurred to CC cause the device to assert SMB. Table 66. Flash/Modem/EEPROM Interface DC Specifications Symbol Parameter Condition Min Max Units Notes V Input High Voltage 2.0 V + 0.5 V IHL CC V Input Low Voltage -0.5 0.8 V ILL Input Low Leakage I 0 < V < V ±20 µA ILL IN CC Current V Output High Voltage I = -1 mA 2.4 V OHL out V Output Low Voltage I = 2 mA 0.4 V OLL out C Input Pin Capacitance 10 pF 1 INL NOTE: 1. This value is characterized but not tested. Datasheet 91 82551QM — Networking Silicon Table 67. LED Voltage/Current Characteristics Symbol Parameter Condition Min Typical Max Units Notes V Output High Voltage I = -10 mA 2.4 V OHLED out V Output Low Voltage I = 10 mA 0.7 V OLLED out Table 68. 100BASE-TX Voltage/Current Characteristics Symbol Parameter Condition Min Typical Max Units Notes Input Differential R DC 10 K ID100 Impedance Input Differential V ±500 mV IDA100 Accept Peak Voltage Input Differential V ±100 mV IDR100 Reject Peak Voltage Input Common Mode V V /2 V ICM100 CC Voltage Output Differential V 0.95 1.00 1.05 V OD100 Peak Voltage Line Driver Supply I RBIAS100 = 649  20 mA 1, 2 CCT100 Peak Current NOTES: 1. Current is measured on all V pins (V = 3.3 V). Recommended starting value for RBIAS100. CC CC 2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value. Table 69. 10BASE-T Voltage/Current Characteristics Symbol Parameter Condition Min Typical Max Units Notes Input Differential R 10 MHz 10 K ID10 Impedance Input Differential V 5 MHz  f  10 MHz ±585 ±440 ±3100 mV IDA10 Accept Peak Voltage Input Differential V 5 MHz  f  10 MHz 0 ±440 ±300 mV IDR10 Reject Peak Voltage Input Common Mode V V /2 V ICM10 CC Voltage Output Differential V R = 100  2.2 2.8 V OD10 L Peak Voltage Line Driver Supply I R = 619  20 mA 1, 2 CCT10 BIAS10 Peak Current NOTES: 1. Current is measured on all V pins (V = 3.3 V). Recommended starting value for RBIAS10. CC CC 2. Transmitter peak current is attained by dividing the measured maximum differential output peak voltage by the load resistance value. 92 Datasheet Networking Silicon — 82551QM Table 70. Digital I/O Characteristics Symbol Parameter Min Typical Max Units Notes V Output High Voltage 2.0 Vcc+0.5 V IH V Output Low Voltage -0.5 0.8 V IL Table 71. Crystal Input One (X1) Characteristics Symbol Parameter Min Typical Max Units Notes V Input High Voltage 2.0 Vcc+0.5 V IH V Input Low Voltage -0.5 0.8 V IL 12.3 AC Specifications Table 72. AC Specifications for PCI Signaling Symbol Parameter Condition Min Max Units Notes 0 < V  1.4 -44 mA 1 OUT Switching 1.4 < V < 0.9V -17.1(V - V)mA1 OUT CC CC OUT Current High I OH(AC) 0.7V < V < V Eqn A mA 2 CC OUT CC (Test Point) V = 0.7V -32V mA 2 OUT CC CC V  2.2 95 mA 1 OUT Switching 2.2 > V > 0.1V V /0.023 mA 1 OUT CC OUT Current Low I OL(AC) 0.18V > V > 0 Eqn B mA 2 CC OUT (Test Point) V = 0.18V 38V mA 2 OUT CC CC Low Clamp I -3 < V  -1 -25 + (V + 1)/0.015 mA 3, 4 CL IN IN Current High Clamp 25 + (V - V -1)/ IN CC I V + 4 > V  V + 1 mA 3 CH CC IN CC Current 0.015 PCI Output Rise slew 0.4 V to 2.4 V 1 4 V/ns RP Slew Rate PCI Output Fall slew 2.4 V to 0.4 V 1 4 V/ns FP Slew Rate NOTES: 1. Switching Current High specifications are not relevant to PME#, SERR#, or INTA#, which are open drain outputs. 2. Maximum current requirements will be met as drivers pull beyond the first step voltage (AC drive point). Equations defining these maximums (A and B) are provided. To facilitate component testing, a maximum current test point is defined for each side of the output driver. Equation A. I = (98/V ) (V - V ) (V + 0.4V ), for V > V > 0.7V OH CC * out CC * out CC CC out CC Equation B. I = (256/V ) (V ) (V - V ), for 0 < V < 0.18V OL CC * out * CC out out CC 3. This parameter is also applicable to CardBus environment. 4. Do not test. Guranteed by design. Datasheet 93 82551QM — Networking Silicon Table 73. AC Specifications for CardBus Signaling Symbol Parameter Condition Min Max Units Notes CardBus Output t 0.2V to 0.6V 0.25 1.0 V/ns RCB CC CC Rise Time CardBus Output t 0.6V to 0.2V 0.25 1.0 V/ns FCB CC CC Fall Time 12.4 Timing Specifications 12.4.1 Clocks Specifications 12.4.1.1 PCI/CardBus Clock Specifications The 82551QM uses the PCI Clock signal directly. Figure 23 shows the clock waveform and required measurement points for the PCI Clock signal. Table 74 summarizes the PCI Clock specifications. Figure 23. PCI/CardBus Clock Waveform 0.6V CC 0.475V CC 0.4V 0.4V p-to-p CC CC (minimum) 0.325V CC 0.2V CC T_high T_low T_cyc Table 74. PCI/CardBus Clock Specifications Symbol Parameter Min Max Units Notes T1 T CLK Cycle Time 30 ns 1 cyc T2 T CLK High Time 11 ns high T3 T CLK Low Time 11 ns low T4 T CLK Slew Rate 1 4 V/ns 2 slew NOTES: 1. The 82551QM will work with any PCI clock frequency up to 33 MHz. 2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate is met across the minimum peak-to-peak portion of the clock waveform as shown in Figure 23. 94 Datasheet Networking Silicon — 82551QM 12.4.1.2 X1 Specifications X1 serves as a signal input from an external crystal or oscillator. Table 75 defines the 82551QM requirements from this signal. Table 75. X1 Clock Specifications Symbol Parameter Min Typical Max Units Notes T8 Tx1_dc X1 Duty Cycle 40% 60% T9 Tx1_pr X1 Period 40 ns ±30PPM 12.4.2 Timing Parameters 12.4.2.1 Measurement and Test Conditions Figure 24, Figure 25, and Table 76 define the conditions under which timing measurements are done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must guarantee that minimum timings are also met with maximum clock slew rate (fastest edge) and voltage swing. In addition, the design must guarantee proper input operation for input voltage swings and slew rates that exceed the specified test conditions. Figure 24. Output Timing Measurement Conditions V_th CLK V_test V_tl T_val OUTPUT V_step DELAY Tri-State V_test V_test OUTPUT T_on T_off Datasheet 95 82551QM — Networking Silicon Figure 25. Input Timing Measurement Conditions V_th V_test CLK V_tl T_su T_h V_th inputs V_test V_test V_max INPUT valid V_tl Table 76. Measure and Test Condition Parameters Symbol PCI Level CardBus Level Units Notes V 0.6V 0.6V V th CC CC V 0.2V 0.2V V tl CC CC V 0.4V 0.4V V test CC CC 0.325V V Min Delay CC V (rising edge) 0.285V step CC 0.475V VMax Delay CC 0.475V V Min Delay CC V (falling edge) 0.615V step CC 0.325V VMax Delay CC V 0.4V 0.4V V max CC CC Input Signal Edge 11 V/ns Rate NOTE: Input test is done with 0.1V overdrive. V specifies the maximum peak-to-peak waveform allowed CC max for testing input timing. 96 Datasheet Networking Silicon — 82551QM 12.4.2.2 PCI/CardBus Timings Table 77. PCI/CardBus Timing Parameters Symbol Parameter Min Max Units Notes PCI CLK to Signal Valid Delay 2 11 ns 1, 2, 3 T14 t val CardBus CLK to Signal Valid Delay 2 18 ns 1, 7 PCI CLK to Signal Valid Delay (point- T15 t 2 12 ns 1, 2, 3 val(ptp) to-point) T16 t Float to Active Delay 2 ns 1 on T17 t Active to Float Delay 28 ns 1 off T18 t Input Setup Time to CLK 7 ns 3, 4 su PCI Input Setup Time to CLK (point-to- T19 t 10 ns 3, 4 su(ptp) point) T20 t Input Hold Time from CLK 0 ns 5 h T21 t Reset Active Time After Power Stable 1 ms 5 rst PCI Reset Active Time After CLK 100 clocks 5 Stable T22 T rst-clk CardBus Reset Active Time After CLK 100 clocks 5 Stable T23 T Reset Active to Output Float Delay 40 ns 5, 6 rst-off NOTES: 1. Timing measurement conditions are illustrated in Figure 24. 2. PCI minimum times are specified with loads as detailed in the PCI Bus Specification, Revision 2.1, Section 4.2.3.2. 3. n a PCI environment, REQ# and GNT# are point-to-point signals and have different output valid delay times and input setup times than bussed signals. All other signals are bussed. 4. Timing measurement conditions are illustrated in Figure 25. 5. RST# is asserted and de-asserted asynchronously with respect to the CLK signal. 6. All PCI and CardBus interface output drivers are floated when RST# is active. 7. CardBus minimum times are specified with a 0 pF equivalent load. Maximum times are specified with a 30 pF equivalent load. Actual test loads may vary but must be correlated to these loads. 12.4.2.3 Flash/Modem Interface Timings The 82551QM is designed to support up to 150 ns of Flash access time. The V signal in the Flash PP implementation should be connected permanently to 12 V. Thus, writing to the Flash is controlled only by the FLWE# pin. Table 78 provides the timing parameters for the Flash interface signals. The timing parameters are illustrated in Figure 26 and Figure 27. Modem is supported through the Flash interface when the following conditions apply: • FLA6:0, FLD7:0, FLCS#, FLOE#, and FLWE# have the same functions for Flash and modem. Datasheet 97 82551QM — Networking Silicon • FLA8 acts as IOCHRDY asynchronous input in modem mode. Table 78. Flash Timing Parameters Symbol Parameter Min Max Units Notes 1, Flash t AVAV T35 t Flash Read/Write Cycle Time 150 ns flrwc = 150 ns 1, Flash t AVQV T36 t FLA to Read FLD Setup Time 150 ns flacc = 150 ns 1, Flash t ELQV T37 t FLCS# to Read FLD Setup Time 150 ns flce = 150 ns 1, Flash t GLQV T38 t FLOE# Active to Read FLD Setup Time 120 ns floe = 55 ns FLOE# Inactive to FLD Driven Delay 1, Flash t GHQZ T39 t 50 ns fldf Time = 35 ns 2, Flash t AVWL T40 t FLA Setup Time before FLWE# 5 ns flas = 0 ns 2, Flash t WLAX T41 t FLA Hold Time after FLWE# 200 ns flah = 60 ns 2, Flash t ELWL T42 t FLCS# Hold Time before FLWE# 30 ns flcs = 20 ns 2, Flash t WHEH T43 t FLCS# Hold Time after FLWE# 30 ns flch = 0 ns 2, Flash t DVWH T44 t FLD Setup Time 150 ns flds = 50 ns 2, Flash t WHDX T45 t FLD Hold Time 10 ns fldh = 10 ns 2, Flash t WLWH T46 t Write Pulse Width 120 ns flwp = 60 ns 2, Flash t WHWL T47 t Write Pulse Width High 25 ns flwph = 20 ns IOCHRDY Hold Time after FLWE# or T48 t 25 ns Mioha FLOE# Active IOCHRDY Hold Time after FLWE# or T49 t 0ns Miohi FLOE# Inactive NOTES: 1. These timing specifications apply to Flash read cycles. The Flash timings referenced are 28F020-150 timings. 2. These timing specifications apply to Flash write cycles. The Flash timings referenced are 28F020-150 timings. 98 Datasheet Networking Silicon — 82551QM Figure 26. Flash/Modem Timings for a Read Cycle FLADDR Address Stable T35 FLCS# T37 FLOE# T38 T39 T36 FLDATA-R Data In T49 T48 IOCHRDY Figure 27. Flash/Modem Timings for a Write Cycle T35 FLADDR Address Stable T40 T41 FLCS# T42 T46 T43 FLWE# T47 T44 T45 FLDATA-W Data Out T49 T48 IOCHRDY Datasheet 99 82551QM — Networking Silicon 12.4.2.4 EEPROM Interface Timings The 82551QM is designed to support a standard 64x16 or 256x16 serial EEPROM. Table 79 provides the timing parameters for the EEPROM interface signals. The timing parameters are illustrated in Figure 28. Table 79. EEPROM Timing Parameters Symbol Parameter Min Max Units Notes EEPROM tcss T51 t Delay from EECS High to EESK High 300 ns ECSS = 50 ns EEPROM tcsh T52 t Delay from EESK Low to EECS Low 30 ns ECSH = 0 ns EEPROM tdis T53 t Setup Time of EEDI to EESK 300 ns EDIS = 150 ns EEPROM tdih T54 t Hold Time of EEDI after EESK 300 ns EDIH = 150 ms EEPROM tcs = T55 t EECS Low Time 750 ns ECS 250 ns Figure 28. EEPROM Timings EECS T51 T52 FLA15/EESK T53 T54 FLA13/EEDI 100 Datasheet Networking Silicon — 82551QM 12.4.2.5 PHY Timings Table 80. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Symbol Parameter Condition Min Typ Max Units T56 T NLP Width 10 Mbps 100 ns nlp_wid T57 T NLP Period 10 Mbps 8 24 ms nlp_per Figure 29. 10BASE-T Normal Link Pulse (NLP) Timings T57 T56 Normal Link Pulse Table 81. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Symbol Parameter Min Typ Max Units T58 T FLP Width (clock/data) 100 ns flp_wid T59 T Clock Pulse to Clock Pulse Period 111 125 139 µs flp_clk_clk T60 T Clock Pulse to Data Pulse Period 55.5 62.5 69.5 µs flp_clk_dat T61 T Number of Pulses in one burst 17 33 flp_bur_num T62 T FLP Burst Width 2 ms flp_bur_wid T63 T FLP Burst Period 8 24 ms flp_bur_per Figure 30. Auto-Negotiation Fast Link Pulse (FLP) Timings T59 T60 T58 Fast Link Pulse Clock Pulse Data Pulse Clock Pulse T63 T62 FLP Bursts Datasheet 101 82551QM — Networking Silicon Table 82. 100Base-TX Transmitter AC Specification Symbol Parameter Condition Min Typ Max Units TDP/TDN Differential T64 T HLS Data 1400 ps jit Output Peak Jitter 12.4.2.6 SMB Interface Timings Table 83. Flash Timing Parameters Symbol Parameter Min Max Units Notes f SMB Operating Frequency 1 MHz smb T84 t Data Hold Time 300 ns dhs T85 t Data Setup Time 250 ns dsus 102 Datasheet Networking Silicon — 82551QM 13.0 82551QM Test Port Functionality 13.1 Introduction The 82551QM’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 13.2 Test Function Description The 82551QM TAP mode supports two tests that can be used in board level design. These tests help verify basic functionality as well as test the integrity of solder connection on the board. The tests are described in the following subsections. 13.2.1 Tristate The tristate command sets all 82551QM input and output pins into a tristate (high-Z) mode (all internal pull-ups and pull-downs are disabled). This mode is entered by setting the following test pin combination and resetting the device: TEST = 1 TEXEC = 0 TCK = 0 TI = 1 Datasheet 103 82551QM — Networking Silicon 13.2.2 XOR Tree The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82551QM to be validated at board test. The XOR Tree was chosen for its speed advantages. Modern automated test equipment can perform a complete peripheral scan without support at the board level. This command connects all outputs of the input buffers in the device periphery into a XOR Tree scheme. All the output drivers of the output buffers, except the Test Port Data Output (TO) pin, are put into high-Z mode. These pins are driven to affect the output of the tree. There are two separate chains and associated outputs for speed. Any hard strapped pins will prevent the tester from scanning correctly. This mode is entered by placing the test pins in the following combination: TEST = 1 TEXEC = 1 TCK = 0 TI = 1 ISOLATE# = 1 Note: ISOLATE# must be driven high in order to enter test mode and must be kept high throughout the entire test. There are two XOR Tree chains with two separate outputs assigned to FLOE# (Chain 1) and FLWE# (Chain 2). Table 84. XOR Tree Chains Chain Order Chain 1 Chain 2 (XOR Tree Output) (FLOE#) (FLWE#) 1RST# LILED# 2 IDSEL ACTLED# 3 REQ# SPDLED# 4 AD[23] 5 SERR# 6 AD[22] 7 AD[21] 8 AD[20] ALTRST# 9 AD[19] CLK_RUN# 10 AD[18] AD[31] 11 AD[17] AD[30] 12 C/BE#[2] AD[29] 13 FRAME# AD[28] 14 IRDY# AD[27] 15 TRDY# PME# 16 CLK 17 DEVSEL# AD[26] 18 INTA# AD[25] 19 STOP# C/BE#[3] 20 GNT# AD[24] 21 PERR# FLD0 104 Datasheet Networking Silicon — 82551QM Table 84. XOR Tree Chains Chain Order Chain 1 Chain 2 (XOR Tree Output) (FLOE#) (FLWE#) 22 PAR FLD1 23 AD[16] FLD2 24 C/BE#[1] FLD3 25 AD[15] FLD4 26 AD[14] FLD5 27 AD[13] FLD6 28 AD[12] FLD7 29 AD[11] FLA0 30 AD[10] FLA1 31 AD[9] FLA2 32 AD[8] FLA3 33 C/BE#[0] FLA4 34 AD[7] FLA5 35 AD[6] FLA6 36 AD[5] FLA7 37 AD[4] FLA8 37 AD[3] FLA9 39 AD[2] FLA10 40 AD[1] FLA11 41 AD[0] FLA12 42 EECS FLA13/EEDI 43 FLA14/EEDO 44 FLA15/EESK 45 FLA16 46 FLCS# Datasheet 105 82551QM — Networking Silicon Note: This page is intentionally left blank. 106 Datasheet Networking Silicon — 82551QM 14.0 Package and Pinout Information 14.1 Package Information The 82551QM is a 196-pin Ball Grid Array (BGA) package. Package dimensions are shown in ® Figure 31. More information on Intel device packaging is available in the Intel Packaging Handbook. Figure 31. Dimension Diagram for the 196-pin BGA 1.56 +/-0.19 o 30 0.85 0.40 +/-0.10 Seating Plate 0.32 +/-0.04 Note: All dimensions are in millimeters. Substrate change from 0.36 mm to 0.32 mm Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Datasheet 107 82551QM — Networking Silicon Figure 32. 196 PBGA Package Pad Detail Detail Area 0.45 Solder Resist Opening 0.60 Metal Diameter As illustrated in Figure 32, the 82551QM package uses solder mask defined pads. The copper area is 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is 0.50 mm. 108 Datasheet Networking Silicon — 82551QM 14.2 Pinout Information 14.2.1 Pin Assignments Table 85. Pin Assignments Pin Name Pin Name Pin Name A1 NC A2 SERR# A3 VCC A4 IDSEL A5 AD[25] A6 PME# A7 VCC A8 AD[30] A9 ALTRST# A10 SMBCLK A11 VCC A12 LILED# A13 TEST A14 NC B1 AD[22] B2 AD[23] B3 VSSPP B4 AD[24] B5 AD[26] B6 AD[27] B7 VSSPP B8 AD[31] B9 ISOLATE# SMB_ALERT#/ B10 LAN_PWR_ B11 SPDLED# B12 TO GOOD B13 RBIAS100 B14 RBIAS10 C1 AD[21] C2 RST# C3 REQ# C4 C/BE#[3] C5 CSTSCHG C6 AD[28] C7 AD[29] C8 CLK_RUN# C9 SMBDATA C10 VSSPT C11 ACTLED# C12 VREF C13 TDP C14 TDN D1 AD[18] D2 AD[19] D3 AD[20] D4 VSS D5 VSS D6 VSS D7 VSS D8 VSS D9 NC D10 NC D11 NC D12 TI D13 TEXEC D14 TCK E1 VCC E2 VSSPP E3 AD[17] E4 VSS E5 VSS E6 VSS E7 VSS E8 VSS E9 VSS E10 VSS E11 NC E12 VCC E13 RDP E14 RDN F1 IRDY# F2 FRAME# F3 C/BE#[2] F4 VSS F5 VSS F6 VSS F7 VSS F8 VSS F9 VSS F10 VSS F11 VSS F12 FLD2 F13 FLD1 F14 FLD0 G1 CLK G2 VIO G3 TRDY# G4 NC G5 VCC G6 VCC G7 VSS G8 VSS G9 VSS Datasheet 109 82551QM — Networking Silicon Table 85. Pin Assignments Pin Name Pin Name Pin Name G10 VSS G11 VSS G12 FLD3 G13 VCC G14 VSSPL H1 STOP# H2 INTA# H3 DEVSEL# H4 NC H5 VCC H6 VCC H7 VCC H8 VCC H9 VSS H10 VSS H11 NC H12 FLD6 H13FLD5H14 FLD4 J1 PAR J2 PERR# J3 GNT# J4 NC J5 VCC J6 VCC J7 VCC J8 VCC J9 VCC J10 VCCR J11 VCCR J12 FLA1 J13FLA0J14 FLD7 K1 AD[16] K2 VSSPP K3 VCC K4 VCC K5 VCC K6 VCC K7 VCC K8 VCC K9 VCC K10 VCC K11 VCC K12 VSSPL K13 VCC K14 FLA2 L1 AD[14] L2 AD[15] L3 C/BE#[1] L4 VCC L5 VCC L6 VSS L7 MDMCS# L8 NC L9 VCC L10 VCC L11 VSS L12 FLA5 L13 FLA4 L14 FLA3 M1 AD[11] M2 AD[12] M3 AD[13] M4 C/BE#[0] M5 AD[5] M6 VSSPP M7 AD[1] M8 FLOE# M9 FLWE# M10 FLA15/EESK M11 FLA12 M12 FLA11 M13FLA7M14 FLA6 N1 VSSPP N2 AD[10] N3 AD[9] N4 AD[7] N5 AD[4] N6 VCC N7 AD[0] N8 VCC N9 FLCS# N10 FLA14/EEDO N11 X1 N12 VSSPL N13 FLA10 N14 FLA8/IOCHRDY P1 NC P2 VCC P3 AD[8] P4 AD[6] P5 AD[3] P6 AD[2] P7 EECS P8 VSSPL P9 FLA16 P10 FLA13/EEDI P11 X2 P12 VCC P13FLA9P14 NC 110 Datasheet Networking Silicon — 82551QM 14.2.2 Ball Grid Array Diagram Figure 33. Ball Grid Array Diagram AB C D E F G H J K L M NP NC AD[22] AD[21] AD[18] VCC IRDY# CLK STOP# PAR AD[16] AD[14] AD[11] VSSPP NC 1 SERR# AD[23] RST# AD[19] VSSPP FRAME# VIO INTA# PERR# VSSPP AD[15] AD[12] AD[10] VCC 2 VCC VSSPP REQ# AD[20] AD[17] C/BE#[2] TRDY# DVSEL# GNT# VCC C/B3#[1] AD[13] AD[9] AD[8] 3 C/BE#[3] C/BE#[0] IDSEL AD[24] VSS VSS VSS NC NC NC VCC VCC AD[7] AD[6] 4 AD[25] AD[26] CSTSCHG VSS VSS VSS VCC VCC VCC VCC VCC AD[5] AD[4] AD[3] 5 PME# AD[27] AD[28] VSS VSS VSS VCC VCC VCC VCC VSS VSSPP VCC AD[2] 6 VCC VSSPP AD[29] VSS VSS VSS VSS VCC VCC VCC MDMCS# AD[1] AD[0] EECS 7 CLK_ AD[30] AD[31] VSS VSS VSS VSS VCC VCC VCC NC FLOE# VCC VSSPL 8 RUN# ALTRST# ISOLATE# SMBDATA 9 NC VSS VSS VSS VSS VCC VCC VCC FLWE# FLCS# FLA16 SMB_ ALERT#/ FLA15/ FLA14/ FLA13/ SMBCLK VSSPT NC VSS VSS VSS VSS VCCR VCC VCC 10 LAN_PWR_ EESK EEDO EEDI GOOD VCC SPDLED# ACTLED# NC NC VSS VSS NC VCCR VCC VSS FLA12 X1 X2 11 LILED# TO VREF TI VCC FLD2 FLD3 FLD6 FLA1 VSSPL FLA5 FLA11 VSSPL VCC 12 RBIAS TEST TDP TEXEC RDP FLD1 VCC FLD5 FLA0 VCC FLA4 FLA7 FLA10 FLA9 13 100 RBIAS FLA8/ NC TDN TCK RDN FLD0 VSSPL FLD4 FLD7 FLA2 FLA3 FLA6 NC 14 10 IOCHRDY Datasheet 111 82551QM — Networking Silicon 15.0 Reference Schematics This section shows a 10/100 Mbps design using the 82551QM Fast Ethernet Multifunction PCI/ CardBus Controller. 112 Datasheet Networking Silicon — 82551QM 3VSB The 82551IT can drive three LEDs with the cathode of 2 1 12 each device connected to the 82551IT as shown with 330 the SPEEDLED or a two LED L E D 330 configuration can be used, as shown. In the two LED configuration the link and the activity functions share an A12 indicator. In this scheme the LILED C11 LINK LED would flash LOW AC TL ED each time activity is detected. B11 2 1 S P E E D L E D L ED This capacitor is normally not installed; however a placement can be provided. It might need to be placed based on the results of FCC conformance testing. If it is required, values in the pico fared range can be used. Large capacitance values installed in this location can have a negative effect on long cable performance. So care must be taken in selecting the values used. 8-22 pF Keep trace length from magnetics to RJ-45 connector under one inch. TDP C13 TDN C14 RDP E13 RDN E14 Keep all termination resistors as close to the 82551 as possible. Termplane Use plane for this signal to 0.1 uF make a board CGND = Chassis ground capacitor. Use plane for this signal Termplane pF Optional capacitor 0.1 uF 0.1 uF 82551QM to help with EFT uF Create termination plane in PCB. This plane conformance. RECEIVE acts as a path for low-frequency noise that RD+ 1 7 RX+ might be coupled to unused pins. The plane should not have any direct connection. 5 CT RD- 2 6 RX- MDI-X Mode Only 7 RDC 3 RD+ 1 RX+ 1:1 TD+ 16 10 TX+ TXCT RD- 2 6 RX- TDC 14 1:1 75 Ohms RECEIVE TD- 15 11 TX- 11 TX- TD- 15 1500pF 2kV TRANSMIT TD+ 16 10 TX+ 1:1 TRANSMIT MDI Mode Only 3VSB 4.7uF 4.7uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Place decoupling capacitors as close to the 82551 as possible. If component placements are used on the bottom side of the board, then place decoupling under the 82551IT. Figure 34. Reference Schematic Layout (Sheet 1 of 2) Datasheet 113 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 2 1 82551QM — Networking Silicon PCI_5V 2) The voltage on VIO determines the slope of the signals on the bus. Although the device communicates if VIO is connected to 3.3V in 3.3V PCI systems, optimal performance is acheived if this signal is connected to +5V in PCI bus systems regardless of bus voltage. 100 K ohm All Vcc pins are connected together on the PCB level. The power on the symbol is broken down between core power (Vcc), local bus power (Vccpl), 1) The decoupling transmit power (Vcct), and PCI power (Vccpp) just 2 1 capacitor should be for clarity. added to the VIO pin. 0.1uF G 2 VIO 82551QM AD[31:0] A D 0 N 7 A D 0 A D 1 M 7 A D 1 A D 2 P6 A D 2 A D 3 P5 A D 3 A D 4 N 5 A D 4 A D 5 M 5 A D 5 A D 6 P4 A D 6 A D 7 N 4 A D 7 A D 8 P3 A D 8 A D 9 N 3 A D 9 A D 10 N 2 A D 1 0 A D 11 M 1 A D 1 1 A D 12 M 2 A D 1 2 A D 13 M 3 A D 1 3 A D 14 L1 A D 1 4 A D 5 1 L2 A D 1 5 A D 16 K1 P9 A D 1 6 FLA16 A D 17 E3 3VSB M 1 0 A D 1 7 FLA15/EESK A D 18 D 1 N 10 A D 18 FLA14/EEDO A D 19 D 2 P10 A D 1 9 A D 20 FLA13/EEDI D 3 M 1 1 A D 20 FL A 1 2 A D 21 C 1 M 1 2 A D 2 1 FLA11 A D 22 B1 3VSB EEDI N 13 3 1 A D 2 2 FLA10 DI C S A D 23 B2 P13 A D 2 3 FLA9 A D 24 B4 E E D O N 1 4 4 A D 2 4 A D 25 FLA8/IOCHRDY D O A5 M 1 3 A D 2 5 FLA7 A D 26 B5 EESK M 1 4 2 A D 2 6 FLA6 S K A D 27 B6 L12 3.3K A D 2 7 FLA5 A D 28 C 6 L13 93C46 A D 2 8 FLA4 A D 29 C 7 L14 A D 2 9 A D 30 FLA3 A8 K14 A D 3 0 FLA2 A D 31 B8 J12 A D 3 1 F L A 1 / A U X P W R J13 FL A0 J14 FLD 7 H 12 FL D 6 H 1 3 F LD 5 H 14 FL D 4 G 1 2 FL D3 F12 FL D2 F13 FL D1 F14 FL D0 C/BE[3:0] E E CS C/BE0 M 4 P7 E E C S C/BE0# C/BE1 L3 N 9 FLCS# C/BE1# C/BE2 F3 C/BE2# N 9 C/BE3 C 4 FLCS# C/BE3# F2 FRAME# F R A M E # M 8 F1 F L O E # IRDY# IRDY# M 9 G 3 F L W E # TRDY# TRDY# H 3 D E VSEL# D E V S E L # A13 H 1 TEST STOP# STOP# D 1 3 J1 TEXEC P A R P A R D1 4 INTA H 2 TCK INTA# D1 2 P E R R # J2 TI P E R R # B12 VREF: External VREF can be applied here if the internal reference S E R R # A2 TO S E R R # is not used. The internal reference is recommended, but if an IDSEL A4 1 K ohm IDSEL external reference is implemented, then this will cause the RBIAS C 12 R E Q# C 3 V R E F R E Q # values to change. GNT# J3 GNT# RST# C 2 RST# B14 1 2 RBIAS10 and RBIAS100 C L K G 1 RBIAS10 C L K should be tuned for your ISOLATE# B9 619 ISOLATE# specific application. The AUX_GOOD A9 ALTRS T # PME# B13 1 2 values shown are a A6 RBIAS100 P M E # good starting value. C 5 649 C L K R U N # C 8 Pulldown resistors are used C L K R U N # N 11 X1 on strapped pins to enable P11 The ISOLATE signal should be a signal that X2 the NAND tree test mode to B10 is driven low just prior to the PCI bus shutting work. The value of 1 K ohm down and it should be driven high immediately A10 was chosen strictly on the basis 2 1 following the PCI bus re-activation. of Intel’s test fixturing requirements C 9 Other values can be used, but it is recommended that resistors be used All Vss pins are connected together on the PCB 25 MHz 62 K ohm other than hard strapping the pins. level. The power on the symbol is broken down between core power (Vss), local bus power (Vsspl), 22 pF 22 pF transmit power (Vsst), and PCI power (Vsspp) just for clarity. PME# To PIIX4 Figure 35. Reference Schematic Layout (Sheet 2 of 2) 114 Datasheet TO PCI BUS 2 1 2 1 2 1 2 1 2 1 8 VCC 2 1