TS-PMC A40 & A30 High Performance Video and Signal Processing Features • Ideal for signal pre-processing, video, compression, software defined radio, radar, sonar and other high performance applications • Micro-mezzanine I/O board allows for standard configuration and customization of I/O signals • Micro-mezzanine connects to the front or rear panel interface for I/O flexibility • User defined data can be routed through the P4 connection up to 1 Gigabytes/ sec • Stratix® EP1S40 or EP1S30 FPGA delivers superior processing performance The TS-PMC A40 & A30 is an FPGA processor solution • 1.8 Gigabyte per second targeted at high performance military and commercial computing applications. combined memory bandwidth The large Stratix FPGA and high bandwidth capability, make it ideal for video from two banks of SRAM and and image processing, software defined radio, radar, sonar as well as other two banks of SDRAM high performance signal processing applications. • 2 x 2Mbyte SRAM The TS-PMC module uses a micro-mezzanine I/O concept to support off-the- shelf as well as custom I/O requirements. The micro-mezzanine offers the • 2 x 128Mbyte SDRAM flexibility of front or rear panel connections. • 64/ 66MHz PCI bus High bandwidth processing is critical to most FPGA-based applications. TS- • TS-Development Kits gets you PMC offers four high speed/ high capacity memory banks, which can be two up and running on an FPGA SRAM or SDRAM. This memory configuration offers over 500Mbytes/ second of computing platform in less than memory access speed per SRAM bank and 400Mbytes/ second per SDRAM an hour! bank - delivering an aggregate memory bandwidth of over 1.8 Gigabytes/ second. • Wave FPGA Software Tool Kit provides API, drivers, memory The TS-PMC is also available in a powerful, easy-to-use development kit controller, source code, environment, including Wave FPGA Software Tool Kit from SBS and Altera®’s application examples and more soft-core Nios® II evaluation edition processor, and SOPC Builder – giving • Software compatible with other developers full access to SBS’s resources with minimum effort. TS-Series FPGA computing products All TS-Series of FPGA processors operate in a common Wave software development environment for easy migration across standard platforms. Develop on a TS-PCI and deploy it on a PMC! The TS-PMC is one in a family of FPGA processors and I/O modules provided by SBS Technologies in many form factors including PCI, PCI-104 and CPCI. FPGA COMPUTING TS-PMC A40 & A30 Configuration 7LED Indicators Rs-422 JTAG 4 FGPA controlled Interface I/G 1 watchdog timer 2 CPLC controlled Specifications Input/Output: ZBT SRAM Bank0 • Selectable 32 differential pairs 2 MB between micro-mezzanine, P4 32 Diff pairs ZBT SRAM Bank1 2 MB Altera Stratix FPGA Rear Panel I/O and FPGA Front MICRO EP1S30-7 SDRAM MEZZ Panel Bank2 • 64 bit/ 66MHz PCI bus 128 MB Board 32 Diff pairs I/O between PMC connection and Temp SDRAM Diode Bank3 Temp 128 MB FPGA Local bus Monitoring Internal Local • 32 bit/ 50 MHz PCI local bus to PLL clock Avalon circuitry 16 Diff pairs • LVDS I/O Mezzanine Bridge Res. 32 Diff pairs PMC Rear DMUX P4 I/O • 16 LVDS Input Ntwrk 16 • 16 LVDS Outputs System Monitoring Bus • 68 pin SCSI 3 Connection 32 bit Local Bus front panel connection • Video PMC Mezzanine 3.3V 12V 5V • Two RS-170 Video Inputs Voltage/ Current Clock Generation Configuration & Address Decode PLD 4 • One RS-170 Video Output Monitoring Clock • P4 rear panel connection Distribution Buffer Power Distribution • Single analogue input 8 bit +2.5V Regulator Ref Programmable EEPROM 133 KHz typically for IRIG OSC Clock Device Cfg +1.5V Regulator PLX PCI9656 Device data input EEPROM VPD Filtering Operating System Support: 64 bit/ 66 M Hz PCI Bus • Windows® XP/ 2000, Linux™, Integrity consult manufacturer Ordering Information FPGA Resources: Products • Altera Stratix EP1S40 TS-PMC-3001 PMC, A30 Commercial Grade with 41,250 LUTS per FPGA EP1S30-C7 FPGA, 2 x 128MB SDRAM, 2 x 2MB SRAM, No Mezzanine I/O 14 DSP Blocks per FPGA TS-PMC-4001 PMC, A40 Commercial Grade with • Altera Stratix EP1S30 EP1S40-C5 FPGA, 2 x 128MB SDRAM, 2 x 2MB SRAM, No Mezzanine I/O 32,470 LUTS per FPGA 12 DSP Blocks per FPGA TS-PMC-4002 PMC, A40 Conduction Cooled with EP1S40-I6 FPGA, 2 x 128MB SDRAM, 2 x 2MB SRAM, No Mezzanine I/O Memory Resources: • Two x 2Mbyte ZBT SRAM TS-IX-RS01 RS170 Video Mezzanine I/O for PMC with • Two x 128Mbyte SDRAM 2-RS170 input, 1 RS-170 output, rear panel I/O, conduction cooled compatible TS-IX-RS02 RS-170 Conduction Cooled Micro-Mezzanine I/O for PMC Power Requirements: 2-RS-170 input, 1 RS-170 output, rear panel I/O • 7.5 watts for typical PMC applications TS-IX-LV01 LVDS Mezzanine I/O for PMC with • 12.5 Watts for PrPMC 16 LVDS input, 16 LVDS output, SCSI3 front panel I/O applications TS-IP-MP41 MPEG-4 encode algorithm optimized for the TS-PMC platform. See available Temperature: datasheet for details Commercial Grade Development Kits o o • Operating: 0 to 55 C o o TS-DK-PMC03 PMC LVDS General Purpose Development Kit with • Storage: -45 to 85 C TS-PMC-4001, TS-IX-LV01, Wave Software, Altera Quartus® II, Nios II • Humidity: 5% to 90%, non- evaluation edition and SOPC Builder condensing • Air flow 100 LFPM TS-DK-PMC02 PMC Video Development Kit with TS-PMC-4001, TS-IX-RS01, Wave Software, Altera Quartus II, Nios II Conduction Cooled evaluation edition and SOPC Builder Corporate Headquarters European Headquarters 7401 Snaproll NE Memminger Str. 14 Albuquerque, NM 87109 D-86159 Augsburg, Germany Tel 505.875.0600 Fax 505.875.0400 Tel +49-821-5034-0 Fax +49-821-5034-119 Email info@sbs.com Email sales@sbs-europe.com For additional contact information, please visit our web site at www.sbs.com Specifications subject to change without notice. All trademarks and logos are property of their respective owners. ©2004 SBS Technologies, Inc. 20041112