Allen-Bradley Enhanced and User Ethernet PLC-5 Programmable Manual Controllers (Cat. Nos. 1785-L11B, -L20B, -L30B, -L40B, -L40L, -L60B, -L60L, -L80B, -L20E, -L40E, -L80E, -L26B, -L46B, -L86B) Important User Information 6ROLG�VWDWH�HTXLSPHQW�KDV�RSHUDWLRQDO�FKDUDFWHULVWLFV�GLIIHULQJ�IURP� WKRVH�RI�HOHFWURPHFKDQLFDO�HTXLSPHQW��‡6DIHW\�*XLGHOLQHV�IRU�WKH� $SSOLFDWLRQ��,QVWDOODWLRQ�DQG�0DLQWHQDQFH�RI�6ROLG�6WDWH�&RQWUROV·� �3XEOLFDWLRQ�6*,������GHVFULEHV�VRPH�LPSRUWDQW�GLIIHUHQFHV�EHWZHHQ� VROLG�VWDWH�HTXLSPHQW�DQG�KDUG�ZLUHG�HOHFWURPHFKDQLFDO�GHYLFHV�� %HFDXVH�RI�WKLV�GLIIHUHQFH��DQG�DOVR�EHFDXVH�RI�WKH�ZLGH�YDULHW\�RI� XVHV�IRU�VROLG�VWDWH�HTXLSPHQW��DOO�SHUVRQV�UHVSRQVLEOH�IRU�DSSO\LQJ� WKLV�HTXLSPHQW�PXVW�VDWLVI\�WKHPVHOYHV�WKDW�HDFK�LQWHQGHG�DSSOLFDWLRQ� RI�WKLV�HTXLSPHQW�LV�DFFHSWDEOH� ,Q�QR�HYHQW�ZLOO�WKH�$OOHQ�%UDGOH\�&RPSDQ\�EH�UHVSRQVLEOH�RU�OLDEOH� IRU�LQGLUHFW�RU�FRQVHTXHQWLDO�GDPDJHV�UHVXOWLQJ�IURP�WKH�XVH�RU� DSSOLFDWLRQ�RI�WKLV�HTXLSPHQW� 7KH�H[DPSOHV�DQG�GLDJUDPV�LQ�WKLV�PDQXDO�DUH�LQFOXGHG�VROHO\�IRU� LOOXVWUDWLYH�SXUSRVHV��%HFDXVH�RI�WKH�PDQ\�YDULDEOHV�DQG�UHTXLUHPHQWV� DVVRFLDWHG�ZLWK�DQ\�SDUWLFXODU�LQVWDOODWLRQ��WKH�$OOHQ�%UDGOH\� &RPSDQ\�FDQQRW�DVVXPH�UHVSRQVLELOLW\�RU�OLDELOLW\�IRU�DFWXDO�XVH� EDVHG�RQ�WKH�H[DPSOHV�DQG�GLDJUDPV� 1R�SDWHQW�OLDELOLW\�LV�DVVXPHG�E\�$OOHQ�%UDGOH\�&RPSDQ\�ZLWK� UHVSHFW�WR�XVH�RI�LQIRUPDWLRQ��FLUFXLWV��HTXLSPHQW��RU�VRIWZDUH� GHVFULEHG�LQ�WKLV�PDQXDO� 5HSURGXFWLRQ�RI�WKH�FRQWHQWV�RI�WKLV�PDQXDO��LQ�ZKROH�RU�LQ�SDUW�� ZLWKRXW�ZULWWHQ�SHUPLVVLRQ�RI�WKH�$OOHQ�%UDGOH\�&RPSDQ\�LV� SURKLELWHG� 7KURXJKRXW�WKLV�PDQXDO�ZH�XVH�QRWHV�WR�PDNH�\RX�DZDUH�RI�VDIHW\� FRQVLGHUDWLRQV� $77(17,21� ,GHQWLILHV�LQIRUPDWLRQ�DERXW�SUDFWLFHV� RU�FLUFXPVWDQFHV�WKDW�FDQ�OHDG�WR�SHUVRQDO�LQMXU\�RU� � GHDWK��SURSHUW\�GDPDJH��RU�HFRQRPLF�ORVV� $WWHQWLRQV�KHOS�\RX� � LGHQWLI\�D�KD]DUG � DYRLG�WKH�KD]DUG � UHFRJQL]H�WKH�FRQVHTXHQFHV ,PSRUWDQW���,GHQWLILHV�LQIRUPDWLRQ�WKDW�LV�HVSHFLDOO\�LPSRUWDQW�IRU� VXFFHVVIXO�DSSOLFDWLRQ�DQG�XQGHUVWDQGLQJ�RI�WKH�SURGXFW� (WKHUQHWLDUHJVLVWHUHGWUDGHPDURNI,QWHO&RUSRUDWLRQ;HUR[&RUSRUDWLRQDQG’LJLWDO(TXLSPQHW &RUSRUDWLRQ +’DWDLJKZD\3OXV’+3/3/&3/&/&/ (DQ(G(DUHWUDGHPDURINV5RFNZHOO$XWRPDWLRQ $OOHQ%UDGOWH\DLVUDGHPDUNRI5RFNZHOO$XWRPDWLRQDFRUHEXLRVQVIRNOHV5FZHO,QWHUQDWLRQDO &RUSRUDWLRQ Summary of Changes Introduction 7KLV�UHOHDVH�FRQWDLQV�QHZ�DQG�XSGDWHG�LQIRUPDWLRQ� 7R�KHOS�\RX�ILQG�QHZ�DQG�XSGDWHG�LQIRUPDWLRQ��ORRN�IRU�WKH�FKDQJH� EDUV�DV�VKRZQ�RQ�WKLV�SDUDJUDSK� Updated Information For this new/updated information: See chapter: 2000 elements per data table file 4 recommendations for using 230.4K bit/s 6, 10 performing block-transfers on the extended-local I/O channel 8 enhancements when using the serial port in master mode 11 communicating with ControlLogix devices over Ethernet 12 extended force tables 14 EEPROM information 20 1785-6.5.12 November 1998 soc-ii Notes: 1785-6.5.12 November 1998 Preface Using This Manual How to Use Your Documentation @� Example Variable Explanation N[N7:0]:0 File number The file number is stored in integer address N7:0. N7:[C5:7.ACC] Structure number The word number is the accumulated value of counter 7 in file 5. B3/[I:017] Bit number The bit number is stored in input word 17. N[N7:0]:[N9:1] File and word number The file number is stored in integer address N7:0 and the word number in integer address N9:1. $77(17,21� ,I�\RX�LQGLUHFWO\�DGGUHVV�WKH�LQSXW�RU� RXWSXW�LPDJH�WDEOH��WKH�YDOXH�\RX�VSHFLI\�LQ�WKH�LQWHJHU� � ILOH�WKDW�\RX�XVH�IRU�WKH�LQGLUHFWLRQ��WKH�SRLQWHU��LV� FRQYHUWHG�WR�RFWDO�ZKHQ�H[HFXWHG�E\�WKH�LQVWUXFWLRQ� )RU�H[DPSOH��LI�\RX�HQWHU�2�>1���@�DQG�1����FRQWDLQV�WKH�YDOXH����� WKH�YDOXH�DW�1����LV�FRQYHUWHG�WR�RFWDO�DQG�WKH�UHVXOWLQJ�DGGUHVV�LV� 2������QRW�2����� 7R�PRQLWRU�IRU�LQYDOLG�LQGLUHFW�DGGUHVVHV��FRQGLWLRQ�WKH�UXQJ�ZLWK�WKH� LQGLUHFW�DGGUHVV�ZLWK�D�OLPLW�WHVW�RI�WKH�LQGLUHFW�DGGUHVV�WR�HQVXUH�WKDW� WKH�DGGUHVV�VWD\V�ZLWKLQ�WKH�LQWHQGHG�UDQJH��7KLV�LV�HVSHFLDOO\� DGYLVDEOH�LI�WKH�3/&���SURFHVVRU�KDV�QR�FRQWURO�RYHU�WKH�LQGLUHFW� DGGUHVV��VXFK�DV�WKH�YDOXH�LV�GHWHUPLQHG�E\�YDOXHV�IURP�DQ�,�2� PRGXOH�RU�D�SHHU�SURFHVVRU� 1785-6.5.12 November 1998 Addressing I/O and Processor Memory 4-19 Specifying Indexed Addresses 7KH�SURFHVVRU�VWDUWV�RSHUDWLRQ�DW�WKH�EDVH�DGGUHVV�SOXV�WKH�RIIVHW��� 6WRUH�WKH�RIIVHW�YDOXH�LQ�WKH�RIIVHW�ZRUG�LQ�WKH�SURFHVVRU¶V�VWDWXV�ILOH��� #N5:10 R6:0 O:000 FD 00 Block-Transfers in Selectable Timed Interrupts (STIs) ,I�WKH�SURFHVVRU�UXQV�DQ�67,�WKDW�FRQWDLQV�EORFN�WUDQVIHU�LQVWUXFWLRQV�� WKH�SURFHVVRU�SHUIRUPV�WKHVH�EORFN�WUDQVIHUV�LPPHGLDWHO\�RQ� FRPSOHWLQJ�DQ\�EORFN�WUDQVIHUV�FXUUHQWO\�LQ�WKH�DFWLYH�EXIIHU��DKHDG�RI� EORFN�WUDQVIHU�UHTXHVWV�ZDLWLQJ�LQ�WKH�TXHXH� = preset Done See page 24-8 for a description of prescan operation for this instruction. Timer Off Delay TOF If the input conditions are false, timer T4:1 starts incrementing in TOF 10 1-ms intervals as long as the rung remains false. When the TIMER OFF DELAY accumulated value is greater than or equal to the preset value Timer T4:1 (180), the timer stops and resets the timer done bit. .01 Status Bits: Time Base Preset EN - Enable 180 EN TT DN ACC TOF TT - Timer Timing Accum 0 Rung DN - Done Condition 15 14 13 Value Status True 1 0 1 0 Reset False 0 1 1 increase Timing False 0 0 0 >= preset Done See page 24-8 for a description of prescan operation for this instruction. 1785-6.5.12 November 1998 22-4 Instruction Set Quick Reference Instruction Description Retentive Timer On RTO If the input conditions go true, timer T4:10 starts incrementing in RTO 1-second intervals as long as the rung remains true. When the rung RETENTIVE TIMER ON goes false, the timer stops. If the rung goes true again, the timer Timer T4:10 continues. When the accumulated value is greater than or equal to th 1.0 Time Base preset (10), the timer stops and sets the timer done bit. Preset 10 Status Bits: Accum 0 EN - Enable EN TT DN ACC RTO Rung TT - Timer Timing Condition 15 14 13 Value Status DN - Done False 0 0 0 0 Disabled True 1 1 0 increase Timing False 0 0 0 maintains Disabled True 1 0 1 >= preset Done Timer Reset If the input conditions go true, timer T4:1 is reset. This instruction T4:1 RES resets timers and counters, as well as control blocks. This is �� RES necessary to reset the RTO accumulated value. Counter Instructions Instruction Description Count Up CTU If the input conditions go true, counter C5:1 starts counting, CTU COUNT UP incrementing by 1 every time the rung goes from false-to-true. When the accumulated value is greater than or equal to the preset Counter C5:1 value (10), the counter sets the counter done bit. Preset 10 Accum 0 CU DN OV ACC CTU Status Bits: Rung Condition 15 13 12 Value Status CU-Count Up CD-Count Down False 0 0 0 0 Disabled DN-Count Up done OV-Overflow UN-Underflow incr by 1 Counting Toggle True 1 0 0 True 1 1 0 >= preset Done True 1 1 1 >32767 Overflow See page 24-8 for a description of prescan operation for this instruction. 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-5 Instruction Description Count Down CTD If the input conditions go true, counter C5:1 starts counting, CTD decrementing by 1 every time the rung goes from false-to-true. COUNT DOWN When the accumulated value is less than the preset value (10), Counter C5:1 the counter resets the counter done bit. Preset 10 Accum 35 CD DN UN ACC CTD Status Bits: Rung CU-Count Up Condition 14 13 11 Value Status CD-Count Down False 0 0 0 0 Disabled DN-Count Down done OV-Overflow False 0 1 0 >= preset Preload UN-Underflow Toggle True 1 1 0 dec by 1 Counting True 1 0 0 < preset Done True 1 0 1 < -32768 Underflow See page 24-8 for a description of prescan operation for this instruction. Compare Instructions Instruction Description Limit Test LIM If the Test value (N7:15) is >= the Low Limit (N7:10) and <= the Hig LIM Limit (N7:20), this instruction is true. LIMIT TEST (CIRC) Low limit N7:10 Low Limit Test High Limit LIM 3 Test N7:15 0 0 10 T 4 -5 5 10 T High limit N7:20 22 5 11 10 F 10 0 0 T 10 5 -5 F 10 11 5 T Mask Compare Equal MEQ The processor takes the value in the Source (D9:5) and passes that MEQ value through the Mask (D9:6). Then the processor compares the MASKED EQUAL result to the Compare value (D9:10). If the result and this compariso Source D9:5 values are equal, the instruction is true. 0000� Mask D9:6 Source Mask Compare MEQ 0000 T Compare D9:10 0008 0008 0009 0000 F 0008 0001 0001 000F T 0087 0007 00F0 F 0087 0007 1785-6.5.12 November 1998 22-6 Instruction Set Quick Reference Instruction Description Compare If the expression is true, this input instruction is true. The CMP CMP CMP instruction can perform these operations: equal (=), less than (<), COMPARE less than or equal (<=), greater than (>), greater than or equal (>=), Expression not equal (<>), and complex expressions (up to 80 characters). N7:5 = N7:10 xxx Source A Source B EQU GEQ GRT LEQ LES NEQ xxxxxxxxxxxxx 10 10 T T F T F F Source A N7:5 5 6 F F F T T T 3 Source B N7:10 21 20 F T T F F T 1 -30 -31 F T T F F T -15 -14 F F F T T T Equal to If the value in Source A (N7:5) is = to the value in Source B (N7:10), EQU this instruction is true. Greater than or Equal If the value in Source A (N7:5) is > or = the value in Source B (N7:10), GEQ this instruction is true. Greater than If the value in Source A (N7:5) is > the value in Source B (N7:10), this GRT instruction is true. Less than or Equal If the value in Source A (N7:5) is < or = the value in Source B (N7:10), LEQ this instruction is true. Less than If the value in Source A (N7:5) is < the value in Source B (N7:10), this LES instruction is true. Not Equal If the value in Source A (N7:5) is not equal to the value in Source B NEQ (N7:10), this instruction is true. 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-7 Compute Instructions Instruction Description Compute CPT If the input conditions go true, evaluate the Expression N7:4 - (N7:6 CPT N7:10) and store the result in the Destination (N7:3). COMPUTE The CPT instruction can perform these operations: add (+), subtract Dest N7:3 (-), multiply (*), divide (|), convert from BCD (FRD), convert to BCD 3 (TOD), square root (SQR), logical and (AND), logical or (OR), logical n Expression (NOT), exclusive or (XOR), negate (-), clear (0), and move, X to the N7:4 - (N7:6 * N7:10) power of Y (**), radians (RAD), degrees (DEG), log (LOG), natural log (LN), sine (SIN), cosine (COS), tangent (TAN), inverse sine (ASN), inverse cosine (ACS), inverse tangent (ATN), and complex expressio (up to 80 characters) Note: Any value entered (i.e., 2.3) expands to 8 characters (2.3000000). Arc cosine ACS If input conditions go true, take the arc cosine of the value in ACS F8:19 and store the result in F8:20. ARCCOSINE Source F8:19 Status 0.7853982 Description Bit Dest F8:20 C always resets 0.6674572 sets if overflow is generated; V otherwise resets sets if the result is zero; Z otherwise resets always resets S Addition ADD When the input conditions are true, add the value in Source A ADD (N7:3) to the value in Source B (N7:4) and store the result in the ADD Destination (N7:12). Source A N7:3 3 Source B N7:4 Status Description 1 Bit Dest N7:12 4 sets if carry is generated; C otherwise resets sets if overflow is generated; V otherwise resets sets if the result is zero; Z otherwise resets sets if the result is negative; S otherwise resets 1785-6.5.12 November 1998 22-8 Instruction Set Quick Reference Instruction Description Arc sine ASN When input conditions go true, take the arc sine of the value in ASN F8:17 and store the result in F8:18. ARCSINE Source F8:17 Status 0.7853982 Description Bit Dest F8:18 0.9033391 C always resets V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets always resets S Arc tangent ATN When input conditions go true, take the arc tangent of the value ATN in F8:21 and store the result in F8:22. ARCTANGENT Source F8:21 Status Description 0.7853982 Bit Dest F8:22 C always resets 0.6657737 V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets Average AVE When the input conditions go from false-to-true, take the average o AVE the file #N7:1 and store the result in N7:0. AVERAGE FILE File #N7:1 Status Bits: Status Description Dest N7:0 EN - Enable Bit DN - Done bit Control R6:0 ER - Error Bit C always resets Length 4 Position 0 V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-9 Instruction Description Clear CLR When the input conditions are true, clear decimal file 9, word 34 (se CLR to zero). CLR Dest D9:34 0000 Status Description Bit C always reset V always reset Z always set S always reset Cosine COS When input conditions go true, take the cosine of the value in COS F8:13 and store the result in F8:14. COSINE Source F8:13 Status 0.7853982 Description Bit Dest F8:14 0.7071068 C always resets V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets 1785-6.5.12 November 1998 22-10 Instruction Set Quick Reference Instruction Description Division DIV When the input conditions are true, divide the value in Source A DIV DIVIDE (N7:3) by the value in Source B (N7:4) and store the result in the Destination (N7:12). Source A N7:3 3 Status Description Source B N7:4 Bit 1 C always resets Dest N7:12 3 V sets if division by zero or overflow; otherwise resets Z sets if the result is zero; otherwise resets; undefined if overflow is set S sets if the result is negative; otherwise resets; undefined if overflow is set Natural log LN When input conditions go true, take the natural log of the value in LN N7:0 and store the result in F8:20. NATURAL LOG Source N7:0 Status Description 5 Bit Dest F8:20 C always resets 1.609438 sets if overflow is generated; V otherwise resets sets if the result is zero; Z otherwise resets sets if the result is negative; S otherwise resets LOG When input conditions go true, take the log base 10 of the value in N7:2 and store the result in F8:3. LOG BASE 10 Source N7:2 Status 5 Description Bit Dest F8:3 0.6989700 C always resets sets if overflow is generated; V otherwise resets sets if the result is zero; Z otherwise resets sets if the result is negative; S otherwise resets 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-11 Instruction Description Multiply MUL When the input conditions are true, multiply the value in Source MUL A (N7:3) by the value in Source B (N7:4) store the result in the MULTIPLY Destination (N7:12). Source A N7:3 3 Status Description Source B N7:4 Bit 1 C always resets Dest N7:12 3 V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets Negate NEG When the input conditions are true, take the opposite sign of the NEG Source (N7:3) and store the result in the Destination (N7:12). This NEGATE instruction turns positive values into negative values and negative Source N7:3 values into positive values. 3 Status Dest N7:12 Description Bit -3 C sets if the operation generates a carry; otherwise resets V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets Sine SIN When input conditions go true, take the sine of the value in F8:11 SIN and store the result in F8:12. SINE Status Source F8:11 Description 0.7853982 Bit Dest F8:12 C always resets 0.7071068 V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets 1785-6.5.12 November 1998 22-12 Instruction Set Quick Reference Instruction Description Square Root SQR When the input conditions are true, take the square root of the Sourc SQR (N7:3) and store the result in the Destination (N7:12). SQUARE ROOT Source N7:3 25 Status Description Dest N7:12 Bit 5 C always resets V sets if overflow occurs during floating point to integer conversion; otherwise resets Z sets if the result is zero; otherwise resets S always reset Sort SRT When the input conditions go from false-to-true, the values in N7:1 SRT N7:2, N7:3.and N7:4 are sorted into ascending order. SORT File #N7:1 Status Bits: Control R6:0 EN-Enable Length DN-Done Bit 4 ER-Error Bit Position 0 Standard Deviation STD When the input conditions go from false-to-true, take the STD standard deviation of the values in file #N7:1 and store the STANDARD DEVIATION result in the Destination (N7:0). File #N7:1 Status Bits: Dest N7:0 EN - Enable Status Control DN - Done Bit R6:0 Description Bit ER - Error Bit Length 4 Position 0 C always resets V sets if overflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S always resets 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-13 Instruction Description Subtract SUB When the input conditions are true, subtract the value in Source B SUB (N7:4) from the value in Source A (N7:3) and store the result in the SUBTRACT Destination (N7:12). Source A N7:3 3 Source B N7:4 Status Description 1 Bit Dest N7:12 C sets if borrow is generated; 2 otherwise resets V sets if underflow is generated; otherwise resets Z sets if the result is zero; otherwise resets S sets if the result is negative; otherwise resets Tangent TAN When input conditions go true, take the tangent of the value in TAN F8:15 and store the result in F8:16. TANGENT Status Source F8:15 Description 0.7853982 Bit Dest F8:16 C always resets 1.000000 sets if overflow is generated; V otherwise resets sets if the result is zero; Z otherwise resets sets if the result is negative; S otherwise resets X to the power of Y XPY When input conditions go true, take the the value in N7:4, raise it XPY to the power stored in N7:5, and store the result in N7:6. X TO POWER OF Y Source A N7:4 Status Description 5 Bit Source B N7:5 C always resets 2 Dest N7:6 sets if overflow is generated; 25 V otherwise resets sets if the result is zero; Z otherwise resets sets if the result is negative; S otherwise resets 1785-6.5.12 November 1998 22-14 Instruction Set Quick Reference Logical Instructions Instruction Description AND AND When the input conditions are true, the processor performs an AND operation (bit-by-bit) between Source A (D9:3) and Source B (D9:4) BITWISE AND and stores the result in the Destination (D9:5). The truth table for a Source A D9:3 AND operation is: 3F37 Source B D9:4 Source A Source B Result 00FF 000 Dest D9:5 100 0037 010 111 NOT Operation When the input conditions are true, the processor performs a NOT NOT (takes the opposite of) operation (bit-by-bit) on the Source (D9:3) an NOT stores the result in the Destination (D9:5). The truth table for a NOT operation is: Source A D9:3 00FF Source Destination Dest D9:5 01 FF00 10 OR OR When the input conditions are true, the processor performs an OR operation (bit-by-bit) between Source A (D9:3) and Source B (D9:4) BITWISE INCLUSIVE OR and stores the result in the Destination (D9:5). The truth table for a Source A D9:3 OR operation is: 3F37 Source B D9:4 Source A Source B Result 00FF 000 Dest D9:5 101 3FFF 011 111 Exclusive OR XOR When the input conditions are true, the processor performs an XOR exclusive OR operation (bit-by-bit) between Source A (D9:3) and BITWISE EXCLUSIVE OR Source B (D9:4) and stores the result in the Destination (D9:5). The D9:3 Source A truth table for an XOR operation is: 3F37 Source B D9:4 Source A Source B Result 3F37 000 101 Dest D9:5 0000 011 110 Status Description Bit C always resets V always resets Z sets if the result is zero; otherwise resets S sets if the most significant bit (bit 15 for decimal or bit 17 for octal) is set (1); otherwise resets 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-15 Conversion Instructions Instruction Description Convert from BCD FRD When the input conditions are true, convert the BCD value in the FRD Source (D9:3) to a integer value and store the result in the FROM BCD Destination (N7:12). The source must be in the range of Source D9:3 0-9999 (BCD). 0037 Dest N7:12 Status Description 37 Bit C always resets V always resets Z sets if the destination value is zero; otherwise resets S always resets Convert to BCD TOD When the input conditions are true, convert the integer value in TOD Source (N7:3) to a BCD format and store the result in the TO BCD Destination (D9:5). Source N7:3 Status 44 Description Bit Dest D9:5 0044 C always resets V sets if the source value is negative or greater than 9999 (i.e. outside of the range of 0-9999) sets if the destinationvalue is zero; Z otherwise resets S always resets Convert to Degrees DEG When the input conditions are true, convert radians (the value in DEG Source A) to degrees and stores the result in the Destination RADIANS TO DEGREE (Source times 180/p). Source F8:7 0.7853982 Status Description Dest F8:8 Bit 45 C always resets V sets if overflow generated; otherwise resets sets if result is zero; otherwise resets Z S sets if result is negative; otherwise resets 1785-6.5.12 November 1998 22-16 Instruction Set Quick Reference Instruction Description Convert to Radians RAD When the input conditions are true, convert degrees (the value in RAD Source A) to radians and stores the result in the Destination DEGREES TO RADIAN (Source times p/180). N7:9 Source 45 Status Description Dest F8:10 Bit 0.7853982 C always resets V sets if overflow generated; otherwise resets sets if result is zero; otherwise resets Z S sets if result is negative; otherwise resets Bit Modify and Move Instructions Instruction Description Move MOV When the input conditions are true, move a copy of the value in MOV Source (N7:3) to the Destination (F8:12), converting from one data MOVE type to another This overwrites the original value in Source N7:3 the Destination. 20 Dest F8:12 Status Description 20.000000 Bit C always resets V sets if overflow is generated during floating point-to-integer conversion; otherwise resets sets if the destination value is zero; Z otherwise resets S sets if result MSB is set; otherwise resets Masked Move When the input conditions are true, the processor passes the value MVM MVM the Source (D9:3) through the Mask (D9:5) and stores the result in t MASKED MOVE Destination (D9:12). This overwrites the original value in the Source D9:3 Destination. 478F Status Description Mask D9:5 Bit 00FF Dest D9:12 C always resets 008F V always resets Z sets if the result is zero; otherwise resets S sets if most significant bit of resulting value is set; otherwise resets. 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-17 Instruction Description Bit Distribute When the input conditions are true, the processor copies the number BTD BTD of bits specified by Length, starting with the Source bit (3) of the BIT FIELD DISTRIB Source (N7:3), and placing the values in the Destination (N7:4), Source N7:3 starting with the Destination bit (10). 0 Source bit 3 Dest N7:4 0 Dest bit 10 Length 6 File Instructions Instruction Description File Arithmetic and Logic When the input conditions go from false-to-true, the processor FAL FAL reads 8 elements of N14:0, and subtracts 256 (a constant) from each element. This example shows the result being stored in the FILE ARITH/LOGICAL Status Bits: eight elements beginning with N15:10. The control element R6:1 Control R6:1 EN - Enable controls the operation. The Mode determines whether the Length 8 DN - Done Bit processor performs the expression on all elements in the files Position 0 ER - Error Bit (ALL) per program scan, one element in the files (INC) per Mode ALL false-to-true transition, or a specific number of elements (NUM) Dest #N15:10 per scan. Expression #N14:0 - 256 The FAL instruction can perform these operations: add (+), subtract (-), multiply (*), divide (|), convert from BCD (FRD), convert to BCD (TOD), square root (SQR), logical and (AND), logical or (OR), logical not (NOT), exclusive or (XOR), negate (-), clear (0), move, and the new math instructions (see the CPT list). File Search and When the input conditions go from false-to-true, the processor FSC Compare performs the not-equal-to comparison on 10 elements between FILE SEARCH/COMPARE FSC files B4:0 and B5:0. Mode determines whether the processor performs the expression on all elements in the files (ALL) per Control R9:0 Status Bits: program scan, one element in the files (INC) per false-to-true Length 90 EN - Enable transition, or a specific number of elements (NUM) per scan. Position 0 DN - Done Bit Control element R9:0 controls the operation. Mode 10 ER - Error Bit When the corresponding source elements are not equal (element Expression #B4:0 <> #B5:0 IN - Inhibit Bit B4:4 and B5:4 in this example), the processor stops the search FD - Found Bit and sets the found .FD and inhibit .IN bits so your ladder program can take appropriate action. To continue the search comparison, you must reset the .IN bit. To see a list of the available comparisons, see the comparisons listed under the CMP instruction. 1785-6.5.12 November 1998 22-18 Instruction Set Quick Reference Instruction Description File Copy When the input conditions are true, the processor copies the COP COP contents of the Source file (N7) into the Destination file (N12). COPY FILE The source remains unchanged. The COP instruction copies the Source #N7:0 number of elements from the source as specified by the Length. Dest #N12:0 As opposed to the MOV instruction, there is no data type conversion for this instruction. Length 5 File Fill When the input conditions are true, the processor copies the FLL FLL value in Source (N10:6) to the elements in the Destination (N12). FILL FILE The FLL instruction only fills as many elements in the destination as specified in the Length. Source N10:6 Dest #N12:0 As opposed to the MOV instruction, there is no data type conversion for this instruction. Length 5 Diagnostic Instructions Instruction Description File Bit Compare When the input conditions go from false-to-true, the processor FBC FBC compares the number of bits specified in the CMP Control Length FILE BIT COMPARE (48) of the Source file (#I:031) with the bits in the Reference file Status Bits: (#B3:1). The processor stores the results (mismatched bit numbers) Source #I:031 EN - Enable in the Result file (#N7:0). File R6:4 controls the compare and file R6:5 Reference #B3:1 DN - Done Bit controls the file that contains the results. The file containing the Result #N7:0 ER - Error Bit results can hold up to 10 (the number specified in the Length field) Cmp Control R6:4 IN - Inhibit Bit mismatches between the compared files. Length 48 FD - Found Bit Note: To avoid encountering a possible run-time error when Position 0 executing this instruction, add a ladder rung that clears S:24 (indexed Result Control R6:5 addressing offset) immediately before a FBC instruction. Length 10 Position 0 Diagnostic Detect When the input conditions go from false-to-true, the processor DDT DDT compares the number of bits specified in the CMP Control Length DIAGNOSTIC DETECT (20) of the Source file (# I:030) with the bits in the Reference file Source #I:030 Status Bits: (#B3:1). The processor stores the results (mismatched bit numbers) Reference #B3:1 EN - Enable in the Result file (#N10:0). Control element R6:0 controls the compare DN - Done Bit and the control element R6:1 controls the file that contains the Result #N10:0 ER - Error Bit results (#N10:0). The file containing the results can hold up to 5 (the Cmp Control R6:0 IN - Inhibit Bit number specified in the Length field) mismatches between the Length 20 FD - Found Bit compared files. The processor copies the source bits to the reference Position 0 file for the next comparison. Result Control R6:1 Length The difference between the DDT and FBC instruction is that each 5 Position time the DDT instruction finds a mismatch, the processor changes 0 the reference bit to match the source bit. You can use the DDT instruction to update your reference file to reflect changing machine or process conditions. Note: To avoid encountering a possible run-time error when executing this instruction, add a ladder rung that clears S:24 (indexed addressing offset) immediately before a DDT instruction. 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-19 Instruction Description Data Transition The DTR instruction compares the bits in the Source (I:002) through a DTR DTR Mask (0FFF) with the bits in the Reference (N63:11). When the DATA TRANSITION masked source is different than the reference, the instruction is true Source I:002 for only 1 scan. The source bits are written into the reference address for the next comparison. When the masked source and the reference Mask 0FFF are the same, the instruction remains false. Reference N63:11 Shift Register Instructions Instruction Description Bit Shift Left If the input conditions go from false-to-true, the BSL instruction shifts BSL BSL the number of bits specified by Length (5) in File (B3), starting at bit BIT SHIFT LEFT 16 (B3:1/0 = B3/16), to the left by one bit position. The source bit Status Bits: (I:022/12) shifts into the first bit position, B3:1/0 (B3/16). The fifth bit, File #B3:1 EN - Enable B3:1/4 (B3/20), is shifted into the UL bit of the control structure Control R6:53 DN - Done Bit (R6:53). Bit Address I:022/12 ER - Error Bit Length 5 UL - Unload Bit Bit Shift Right If the input conditions go from false-to-true, the BSR instruction shifts BSR BSR the number of bits specified by Length (3) in File (B3), starting with BIT SHIFT RIGHT B3:2/0 (=B3/32), to the right by one bit position. The source bit File #B3:2 Status Bits: (I:023/06) shifts into the third bit position B3/34. The first bit (B3/32) EN - Enable is shifted into the UL bit of the control element (R6:54). Control R6:54 DN - Done Bit Bit Address I:023/06 ER - Error Bit Length 3 UL - Unload Bit FIFO Load When the input conditions go from false-to-true, the processor loads FFL FFL N60:1 into the next available element in the FIFO file, #N60:3, as FIFO LOAD pointed to by R6:51. Each time the rung goes from false-to-true, the Source N60:1 Status Bits: processor loads another element. When the FIFO file (stack) is full, EN - Enable Load (64 words loaded), the DN bit is set. FIFO #N60:3 R6:51 DN - Done Bit Control See page 24-8 for a description of prescan activities for EM - Empty Bit 64 Length this instruction. Position 0 FIFO Unload When the input conditions go from false-to-true, the processor FFU FFU unloads an element from #N60:3 into N60:2. Each time the rung goes FIFO UNLOAD from false-to-true, the processor unloads another value. All the data Status Bits: in file #N60:3 is shifted one position toward N60:3. When the file is FIFO #N60:3 EU - Enable Unload empty, the EM bit is set. Dest N60:2 DN - Done Bit R6:51 Control See page 24-8 for a description of prescan activities for this EM - Empty Bit 64 Length instruction. Position 0 1785-6.5.12 November 1998 22-20 Instruction Set Quick Reference Instruction Description LIFO Load When the input conditions go from false-to-true, the processor loads LFL LFL N70:1 into the next available element in the LIFO file #N70:3, as LIFO LOAD pointed to by R6:61. Each time the rung goes from false-to-true, the Source N70:1 Status Bits: processor loads another element. When the LIFO file (stack) is full (64 EN - Enable words have been loaded), the DN bit is set. LIFO #N70:3 R6:61 Load Control See page 24-8 for a description of prescan activities for this DN - Done Bit 64 Length instruction. EM - Empty Bit Position 0 LIFO Unload When the input conditions go from false-to-true, the processor LFU LFU unloads the last element from #N70:3 and puts it into N70:2. Each LIFO UNLOAD time the rung goes from false-to-true, the processor unloads another Status Bits: element. When the LIFO file is empty, the EM bit is set. LIFO #N70:3 EU - Enable Dest N70:2 See page 24-8 for a description of prescan activities for this Unload R6:61 Control instruction. DN - Done Bit 64 Length EM - Empty Bit Position 0 Sequencer Instructions Instruction Description Sequencer Input The SQI instruction filters the Source (I:031) input image data through SQI SQI a Mask (FFF0) and compare the result to Reference data (#N7:11) to SEQUENCER INPUT see if the two values are equal. The operation is controlled by the information in the control file R6:21. When the status of all unmasked File #N7:11 bits of the word pointed to by control element R6:21 matches the Mask FFF0 corresponding reference bits, the rung condition remains true if Source I:031 preceded by a true rung condition. Control R6:21 Length 4 Position 0 Sequencer Load The SQL instruction loads data into the sequencer File (#N7:20) from SQL SQL the source word (I:002) by stepping through the number of elements SEQUENCER LOAD specified by Length (5) of the Source (I:002), starting at the Position File #N7:20 Status Bits: (0). The operation is controlled by the information in the control file Source I:002 EN - Enable R6:22. When the rung goes from false-to-true, the SQL instruction Control R6:22 DN - Done Bit increments the next step in the sequencer file and loads the data into Length 5 ER - Error Bit it for every scan that the rung remains true. Position 0 See page 24-8 for a description of prescan operation for this instruction. Sequencer Output When the rung goes from false-to-true, the SQO instruction SQO SQO increments to the next step in the sequencer File (#N7:1). The data in SEQUENCER OUTPUT the sequencer file is transferred through a Mask (0F0F) to the Status Bits: Destination (O:014) for every scan that the rung File #N7:1 # EN - Enable remains true. Mask 0F0F DN - Done Bit Dest See page 24-8 for a description of prescan operation for O:014 ER - Error Bit Control R6:20 this instruction. Length 4 Position 0 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-21 Program Control Instructions Instruction Description Master Control Reset If the input conditions are true, the program scans the rungs between �� MCR MCR MCR instruction rungs and processes the outputs normally. If the input condition is false, rungs between the MCR-instruction rungs are executed as false. Jump If the input conditions are true, the processor skips rungs by jumping 10 JMP to the rung identified by the label (10). �� JMP Label When the processor reads a JMP instruction that corresponds to label 10 LBL 10, the processor jumps to the rung containing the label and starts executing. LBL Important: Must be the first instruction on a rung. FOR Loop The processor executes the rungs between the FOR and the NXT FOR FOR instruction repeatedly in one program scan, until it reaches the FOR terminal value (10) or until a BRK instruction aborts the operation. Step size is how the loop index is incremented. Label Number 0 Index N7:0 See page 24-8 for a description of prescan operation for Initial Value this instruction. 0 Terminal Value 10 Step Size 1 Next The NXT instruction returns the processor to the corresponding FOR NXT NXT instruction, identified by the label number specified in the FOR NEXT instruction. NXT must be programmed on an unconditional rung that Label Number 0 is the last rung to be repeated in a For-Next loop. Break When the input conditions go true, the BRK instruction aborts a BRK BRK For-Next loop. Jump to Subroutine If the input conditions are true, the processor starts running a JSR JSR subroutine Program File (90). The processor passes the Input JUMP TO SUBROUTINE Parameters (N16:23, N16:24, 231) to the subroutine and the RET instruction passes Return Parameters (N19:11, N19:12) back to the Program File 90 main program, where the processor encountered the JSR instruction. Input par N16:23 Input par N16:24 Input par 231 Return par N19:11 Return par N19:12 Subroutine The SBR instruction is the first instruction in a subroutine file. This SBR SBR instruction identifies Input Parameters (N43:0, N43:1, N43:2) the SUBROUTINE processor receives from the corresponding JSR instruction. You do Input par N43:0 not need the SBR instruction if you do not pass input parameters to Input par the subroutine. N43:1 Input par N43:2 Return If the input conditions are true, the RET instruction ends the RET RET subroutine and stores the Return Parameters (N43:3, N43:4) to be RETURN ( ) returned to the JSR instruction in the main program. Return par N43:3 Return par N43:4 1785-6.5.12 November 1998 22-22 Instruction Set Quick Reference Instruction Description Always False The AFI instruction disables the rung (i.e., the rung is always false). AFI AFI Temporary End If the input conditions are true, the TND instruction stops the �� TND TND processor from scanning the rest of the program (i.e., this instruction temporarily ends the program). One Shot If the input conditions preceding the ONS instructions on the same B3 ONS rung go from false-to-true, the ONS instruction conditions the rung so ONS that the output is true for one scan. The rung is false on successive 110 scans. See page 24-8 for a description of prescan operation for this instruction. One Shot Falling The OSF instruction triggers an event to occur one time. Use the OSF OSF OSF instruction whenever an event must start based on the change of ONE SHOT FALLING state of a rung from true-to-false, not on the resulting rung status. Storage Bit B3/0 Status Bits: The output bit (N7:0/15) is set (1) for one program scan when the OB - Output Bit rung goes from true-to-false. Output Bit 15 SB - Storage Bit Output Word N7:0 See page 24-8 for a description of prescan operation for this instruction. One Shot Rising The OSR instruction triggers an event to occur one time. Use the OSR OSR OSR instruction whenever an event must start based on the change of ONE SHOT RISING state of a rung from false-to-true, not on the resulting rung status. Storage Bit B3/0 Status Bits: The output bit (N7:0/15) is set (1) for one program scan when the Output Bit OB - Output Bit rung goes from false-to-true. 15 Output Word N7:0 SB - Storage Bit See page 24-8 for a description of prescan operation for this instruction. SFC Reset The SFR instruction resets the logic in a sequential function chart. SFR SFR When the SFR instruction goes true, the processor performs a SFC Reset lastscan/postscan on all active steps and actions in the selected file, Prog File Number 3 and then resets the logic in the SFC on the next program scan. The Restart Step At chart remains in this reset state until the SFR instruction goes false. End of Transition The EOT instruction should be the last instruction in a transition file. �� EOT EOT If you do not use an EOT instruction, the processor always evaluates the transition as true. See page 24-8 for a description of prescan operation for this instruction. User Interrupt Disable The UID instruction temporarily disables an interrupt-driven ladder �� UID UID program (such as an STI or PII) from interrupting the currently executing program. User Interrupt Enable The UIE instruction re-enables the interrupt-driven ladder program to �� UIE UIE interrupt the currently executing ladder program. 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-23 Process Control, Message Instructions Instruction Description Proportional, Integral, The control block (PD10:0) contains the instruction information for PID and Derivative the PID. The PID gets the process variable from N15:13 and sends PID PID the PID output to N20:21. The tieback stored in N15:14 handles the Control Block PD10:0 manual control station. Proc Variable N15:13 Status Bits: If you use an N control block, the rung must transition from false to Tieback N15:14 EN - Enable true for execution. Control Output N20:21 DN - Done Bit (for N If you use PD control block, then there is no done bit. Also, the rung control blocks only) input conditions need to be true. See page 24-8 for a description of prescan operation for this instruction. If the input conditions go from false to true, the data is transferred MSG according to the instruction parameters you set when you entered the message instruction. The Control Block (MG7:10) contains status and SEND/RECEIVE MESSAGE instruction parameters. Control Block MG7:10 You can also use N control blocks. For continuous MSGs, condition the rung to be true for only one scan. Bit # Status Bits 15 EN - Enable See page 24-8 for a description of prescan operation for 14 ST - Start Bit this instruction. 13 DN - Done Bit 12 ER - Error Bit 11 CO - Continuous 10 EW - Enabled-Waiting 9 NR - No Response 8 TO - Time Out Bit 1785-6.5.12 November 1998 22-24 Instruction Set Quick Reference Block Transfer Instructions Integer (N) control block Block Transfer (BT) control block Word Word Offset Description Mnemonic Description 0 status bits (see below) .EN through .RW status bits 1 requested word count .RLEN requested length 2 transmitted word count .DLEN transmitted word length/error code 3 file number .FILE file number 4 element number .ELEM element number .RGS rack/group/slot Word 0 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EN ST DN ER CO EW NR TO RW ** rack ** ** group** slot Instruction Description Block Transfer Read If the input conditions go from false to true, a block transfer read is BTR BTR initiated for the I/O module located at rack 1, group 0, module 0. The BLOCK TRANSFER READ Control Block (BT11:100, 6-word file) contains status for the transfer. The Data File (N10:110) is where the data read from the module is Rack 1 stored. The BT Length (40) identifies the number of words in the Group 0 transfer. A non-continuous block transfer is queued and run only Module 0 once on a false-to-true rung transition; a continuous block transfer is Control Block BT11:100 repeatedly requeued. Data File N10:110 Length You can also use the N data type for the control blocks. 40 Continuous See page 24-8 for a description of prescan operation for Y this instruction. PLC-5/30, -5/40, -5/40E, -5/40L PLC-5/40, -5/40L, -5/60, PLC-5/60, -5/60L, -5/60, -5/60L, -5/80, -5/80E -5/60L, -5/80, -5/40E, -5/80, -5/80E processors processors -5/80E processors S:7 BT queue S:32 BT queue S:34 BT queue bit # full for rack bit # full for rack bit # full for rack 1 0 08 100820 08 1 1 09 110921 09 1 2 10 121022 10 1 3 11 131123 11 12 4 12 141224 13 5 13 151325 14 6 14 161426 15 7 15 171527 3/&��������������DQG�����(�SURFHVVRUV�DOVR 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-25 Instruction Description Block Transfer Write If the input conditions go from false-to-true, the block transfer BTW BTW write is initiated for the I/O module located at rack 1, group 0, BLOCK TRANSFER WRITE module 0. The Control Block (BT11:0, 6-word file) contains Rack 1 status for the transfer. The Data File contains the data to write to the module (N10:10). The BT Length (40) identifies the number of Group 0 words in the transfer. A non-continuous block transfer is queued Module 0 and run only once on a false-to-true rung transition; a continuous Control Block BT11:0 block transfer is repeatedly requeued. You can also use the N Data File N10:10 data type for the control block. Length 40 See page 24-8 for a description of prescan operation for this Continuous Y instruction. ASCII Instructions Status Bits: EN - Enable EM - Empty Bit DN - Done Bit EU - Queue ER - Error Bit FD - Found Bit Instruction Description ASCII Test for Line If input conditions go from false-to-true, the processor reports ABL ABL the number of characters in the buffer, up to and including the ASCII TEST FOR LINE end-of-line characters and puts this value into the position word Channel 0 of the control structure (R6:32.POS). The processor also displays this value in the characters field of the display. Control R6:32 Characters See page 24-8 for a description of prescan operation for this instruction. ASCII Characters in If input conditions go from false-to-true, the processor reports ACB Buffer the total number of characters in the buffer and puts this value ASCII CHARS IN BUFFER ACB into the position word (.POS) of the control structure. The Channel 0 processor also displays this value in the characters field of the Control R6:32 display. Characters See page 24-8 for a description of prescan operation for this instruction. Convert ASCII String to If input conditions are true, the processor converts ACI Integer ACI the string in ST38:90 to an integer and stores the STRING TO INTEGER CONVERSION result in N7:123. Source ST38:90 Dest N7:123 Status Description Bit 75 set if a carry was generated during the C conversion; otherwise resets set if source is > 32,767 or < -32,768, V otherwise resets set if source is zero; otherwise resets Z S set if destination is negative; otherwise resets 1785-6.5.12 November 1998 22-26 Instruction Set Quick Reference Instruction Description ASCII String If input conditions are true, the processor concatenates ACN Concatenate ACN the string in ST38:90 with the string in ST37:91 and store STRING CONCATENATE the result in ST52:76. Source A ST38:90 ST37:91 Source B Dest ST52:76 ASCII String Extract If input conditions are true, the processor extracts 10 AEX AEX characters starting at the 42nd character of ST38:40 and STRING EXTRACT store the result in ST52:75. Source ST38:40 Index 42 Number 10 Dest ST52:75 Convert Integer to ASCII If input conditions are true, the processor converts the AIC String value 876 to a string and store the result in ST38:42. INTEGER TO STRING CONVERSION AIC Source 876 ST38:42 Dest ASCII Handshake Lines If input conditions go from false-to-true, the processor AHL AHL uses the AND and OR masks to determine whether to set ASCII HANDSHAKE LINE or reset the DTR (bit 0) and RTS (bit 1) lines, or leave Status Bits: Channel 0 them unchanged. Bit 0 and 1 of the AND mask cause the EN-Enable line(s) to reset if 1 and leave the line(s) unchanged if 0. AND Mask 0001 DN-Done Bit BIt 0 and 1 of the OR mask cause the line(s) to set if 1 OR Mask 0003 ER-Error Bit and leave the line(s) unchanged if 0. Control R6:23 Channel Status See page 24-8 for a description of prescan operation for this instruction. ASCII Read If input conditions go from false-to-true, read 50 ARD ARD characters from the buffer and move them to ST52:76. ASCII READ The number of characters read is stored in R6:32.POS Channel 0 Status Bits and displayed in the Characters Read Field of the EN - Enable instruction display. Dest ST52:76 DN - Done Bit Control R6:32 See page 24-8 for a description of prescan operation for ER - Error Bit String Length 50 this instruction. UL - Unload Characters Read EM - Empty EU - Queue ASCII Read Line If input conditions go from false-to-true, read 18 ARL ARL characters (or until end-of-line) from the buffer and move ASCII READ LINE them to ST50:72. The number of characters read is Channel 0 Status Bits stored in R6:30.POS and displayed in the Characters Dest ST50:72 EN - Enable Read Field of the instruction display. Control DN - Done Bit R6:30 See page 24-8 for a description of prescan operation for ER - Error Bit String Length 18 this instruction. UL - Unload Characters Read EM - Empty EU - Queue 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-27 Instruction Description ASCII String Search If input conditions are true, search ST52:80 starting at ASC ASC the 35th character, for the string found in ST38:40. In this STRING SEARCH example, the string was found at index 42. If the string is Source ST38:40 not found, the ASCII instruction minor fault bit S:17/8 is set and the result is zero. Index 35 Search ST52:80 Result 42 ASCII String Compare If the string in ST37:42 is identical to the string in ASR ASR ST38:90, the instruction is true. Note that this is an input ASCII STRING COMPARE instruction. An invalid string length causes the ASCII Source A ST37:42 instruction error minor fault bit S:17/8 to be set, and the Source B ST38:90 instruction is false. ASCII Write Append If input conditions go from false-to-true, read 50 AWA AWA characters from ST52:76 and write it to channel 0 and ASCII WRITE APPEND append the two character configuration in the channel Channel 0 Status Bits configuration (default CR/LF). The number of characters EN - Enable sent is stored in R6:32.POS and displayed in the Source ST52:76 DN - Done Bit characters sent field of the instruction display. Control R6:32 ER - Error Bit String Length 50 See page 24-8 for a description of prescan operation for UL - Unload Characters Sent this instruction. EM - Empty EU - Queue ASCII Write If input conditions go from false-to-true, write 40 AWT AWT characters from ST37:40 to channel 0. The number of ASCII WRITE characters sent is stored in R6:23.POS and displayed in Channel � Status Bits the characters sent field of the instruction display. EN - Enable Source ST37:40 See page 24-8 for a description of prescan operation for DN - Done Bit Control R6:23 this instruction. ER - Error Bit String Length 40 UL - Unload Characters Sent EM - Empty EU - Queue 1785-6.5.12 November 1998 22-28 Instruction Set Quick Reference Bit and Word Instructions Category Code Title Execution Time Words of Execution Time (μs) integer 1 (μs) Memory floating point True False True False 2 Relay XIC examine if closed .32 .16 1 2 XIO examine if open .32 .16 1 2 OTL output latch .48 .16 1 2 OTU output unlatch .48 .16 1 2 OTE output energize .48 .48 1 Branch branch end .16 .16 1 next branch 1 branch start 1 Timer and Counter TON timer on (0.01 base) 3.8 2.6 2-3 (1.0 base) 4.1 2.5 TOF timer off (0.01 base) 2.6 3.2 2-3 (1.0 base) 2.6 3.2 RTO retentive timer on 2-3 (0.01 base) 3.8 2.4 (1.0 base) 4.1 2.3 CTU count up 3.4 3.4 2-3 CTD count down 3.3 3.4 2-3 RES reset 2.2 1.0 2-3 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� )RU�HYHU\�ELW�DGGUHVV�DERYH�WKH�ILUVW�����ZRUGV�RI�PHPRU\�LQ�WKH�GDWD�WDEOH��DGG������μV�DQG���ZRUG RIPHPRU\� 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-29 Category Code Title Execution Time (μs) Execution Time (μs) Words of 1 integer floating point Memory True False True False Arithmetic ADD add 6.1 1.4 14.9 1.4 4-7 SUB subtract 6.2 1.4 15.6 1.4 4-7 MUL multiply 9.9 1.4 18.2 1.4 4-7 DIV divides 12.2 1.4 23.4 1.4 4-7 SQR square root 9.9 1.3 35.6 1.3 3-5 NEG negate 4.8 1.3 6.0 1.3 3-5 CLR clear 3.4 1.1 3.9 1.1 2-3 AVE average file 152+E25.8 30 162+E22.9 36 4-7 STD standard deviation 262+E92.5 34 295+E85.5 34 4-7 TOD convert to BCD 7.8 1.3 3-5 FRD convert from BCD 8.1 1.3 3-5 RAD radian 57.4 1.4 50.1 1.4 3-5 DEG degree 55.9 1.4 50.7 1.4 3-5 SIN sine 414 1.4 3-5 COS cosine 404 1.4 3-5 TAN tangent 504 1.4 3-5 ASN inverse sine 426 1.4 3-5 ACS inverse cosine 436 1.4 3-5 ATN inverse tangent 375 1.4 3-5 LN natural log 409 1.4 403 1.4 3-5 LOG log 411 1.4 403 1.4 3-5 XPY X to the power of Y 897 1.5 897 1.5 4-7 SRT sort file 3-5 (5/11, -5/20) 276 + 12[E**1.34] 227 278 + 16[E**1.35] 227 (-5/30, -5/40, -5/60, 224 + 25[E**1.34] 189 230 + 33[E**1.35] 189 -5/80) 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� (� �QXPEHU�RI�HOHPHQWV�DFWHG�RQ�SHU�VFDQ 657�WUXH�LV�RQO\�DQ�DSSUR[LPDWLRQ���$FWXDO�WLPH�GHSHQGV�RQ�WKH�UDQGRPQHVV�RI�WKH�QXPEHUV� 1785-6.5.12 November 1998 22-30 Instruction Set Quick Reference Category Code Title Execution Time (μs) Execution Time (μs) Words of 1 integer floating point Memory True False True False Logic AND and 5.9 1.4 4-7 OR or 5.9 1.4 4-7 XOR exclusive or 5.9 1.4 4-7 NOT not 4.6 1.3 3-5 Move MOV move 4.5 1.3 5.6 1.3 3-5 MVM masked move 6.2 1.4 4-7 BTD bit distributor 10.0 1.7 6-9 Comparison EQU equal 3.8 1.0 4.6 1.0 3-5 NEQ not equal 3.8 1.0 4.5 1.0 3-5 LES less than 4.0 1.0 5.1 1.0 3-5 LEQ less than or equal 4.0 1.0 5.1 1.0 3-5 GRT greater than 4.0 1.0 5.1 1.0 3-5 GEQ greater than or equal 4.0 1.0 5.1 1.0 3-5 LIM limit test 6.1 1.1 8.4 1.1 4-7 MEQ mask compare if 5.1 1.1 4-7 equal Compare CMP all 2.48 + (Σ[0.8 + i]) 2.16 + 2.48 + (Σ[0.8 + i]) 2.16 + 2+Wi Wi[0.56] Wi[0.56] Compute CPT all 2.48.+ (Σ[0.8 + i]) 2.16 + 2.48.+ (Σ[0.8 + i]) 2.16 + 2+Wi Wi[0.56] Wi[0.56] 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� L� �H[HFXWLRQ�WLPH�RI�HDFK�LQVWUXFWLRQ��H�J���$’’��68%��HWF���XVHG�ZLWKLQ�WKH�&03�RU�&37�H[SUHVVLRQ :L� �QXPEHU�RI�ZRUGV�XVHG�E\�WKH�LQVWUXFWLRQ��H�J���$’’��68%��HWF��ZLWKLQ�WKH�&03�RU�&37�H[SUHVVLRQ &03�RU�&37�LQVWUXFWLRQV�DUH�FDOFXODWHG�ZLWK�VKRUW�GLUHFW�DGGUHVVLQJ 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-31 File, Program Control, and ASCII Instructions Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False File Arithmetic FAL all 11 + (S[2.3 + 6.16 + Wi[0.16] 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 3-5 +Wi and Logic i])E File Search and FSC all 11 + (S[2.3 + 6.16 + Wi[0.16] 11 + (Σ[2.3 + i])E 6.16 + Wi[0.16] 3-5 +Wi Compare i])E File COP copy 16.2+E[0.72] 1.4 17.8+E[1.44] 1.4 4-6 counter, timer, and 15.7+E[2.16] 1.4 control FLL fill 15.7+E[0.64] 1.5 18.1+E[0.80] 1.5 4-6 counter, timer, and 15.1+E[1.60] 1.5 control Shift Register BSL bit shift left 10.6+B[0.025] 5.2 4-7 BSR bit shift right 11.1 + 5.2 4-7 B[0.025] FFL FIFO load 8.9 3.8 4-7 FFU FIFO unload 10.0+E[0.43] 3.8 4-7 LFL LIFO load 9.1 3.7 4-7 LFU LIFO unload 10.6 3.8 4-7 Diagnostic FBC 0 mismatch 15.4 + 2.9 6-11 B[0.055] 1 mismatch 22.4 + 2.9 B[0.055] 2 mismatches 29.9+ B[0.055] 2.9 DDT 0 mismatch 15.4 + 2.9 6-11 B[0.055] 1 mismatch 24.5 + 2.9 B[0.055] 2 mismatches 34.2 + 2.9 B[0.055] DTR data transitional 5.3 5.3 4-7 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� L� �H[HFXWLRQ�WLPH�RI�HDFK�LQVWUXFWLRQ��H�J���$’’��68%��HWF���XVHG�ZLWKLQ�WKH�)$/�RU�WKH�)6&�H[SUHVVLRQ (� �QXPEHU�RI�HOHPHQWV�DFWHG�RQ�SHU�VFDQ %� �QXPEHU�RI�ELWV�DFWHG�RQ�SHU�VFDQ :L� �QXPEHU�RI�ZRUGV�XVHG�E\�WKH�LQVWUXFWLRQ��H�J���$’’��68%��HWF���ZLWKLQ�WKH�)$/�RU�)6&�H[SUHVVLRQ )$/�RU�)6&�LQVWUXFWLRQV�DUH�FDOFXODWHG�ZLWK�VKRUW�GLUHFW�DGGUHVVLQJ 1785-6.5.12 November 1998 22-32 Instruction Set Quick Reference Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False Sequencer SQI sequencer input 7.9 1.3 5-9 SQL sequencer load 7.9 3.5 4-7 SQO sequencer output 9.7 3.7 5-9 2 IIN immediate input 1.1 2 Immediate I/O • PLC-5/11, -5/20, • 357 and -5/20E • 307 • PLC5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, and -5/80, -5/80E IOT immediate output 1.1 2 • PLC-5/11, -5/20, • 361 and -5/20E • 301 • PLC5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E Zone Control MCR master control 0.16 0.16 1 Program Control JMP jump 8.9+(file# - 2) * 1.4 2 0.96 3 jump to subroutine 3+parameter JSR /return s/JSR /RET — 0 parameters 12.3 1.0 not applicable not applicable 1+parameter s/RET — 1 parameter 16.1 1.0 17.3 1.0 — increase/ 3.8 not applicable 5.0 not applicable parameter SBR 1+ parameters 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� 7LPLQJ�IRU�LPPHGLDWH�,�2�LQVWUXFWLRQV�LV�WKH�WLPH�IRU�WKH�LQVWUXFWLRQ�WR�TXHXH�XS�IRU�SURFHVVLQJ� &DOFXODWH�H[HFXWLRQ�WLPHV�DV�IROORZV����WLPH�����TXDQWLW\�RI�DGGLWLRQDO�SDUDPHWHUV��WLPH�SDUDPHWHU����)RU H[DPSOH���LI�\RX�DUH�SDVVLQJ���LQWHJHU�SDUDPHWHUV�LQ�D�-65�ZLWKLQ�D�3/&������SURFHVVRU��WKH�H[HFXWLRQ�WLPH� ����� ����������� ������PV 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-33 Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False Program Control LBL label 0.16 0.16 2 END end negligible 1 TND temporary end 1 EOT end of transition 1 AFI always false 0.16 0.16 1 ONS one shot 3.0 3.0 2-3 OSR one shot rising 6.2 6.0 4-6 OSF one shot falling 6.2 5.8 4-6 FOR/ for next loop 8.1+ L[15.9]+ 5.3 + N[0.75] FOR 5-9 NXT (file# - 2) * 0.96 NXT 2 BRK break 11.3 + N[0.75] 0.9 1 UID user interrupt disable 1.0 1 (PLC-5/11, -5/20, 175 -5/30, -5/40, -5/60, 119 and -5/80 processors) UIE user interrupt enable 1.0 1 (PLC-5/11, -5/20, 170 -5/30, -5/40, -5/60, 100 and -5/80 processors) 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� /� �QXPEHU�RI�)25�1;7�ORRSV 1� �QXPEHU�RI�ZRUGV�LQ�PHPRU\�EHWZHHQ�)25�1;7�RU�%5.�1;7 1785-6.5.12 November 1998 22-34 Instruction Set Quick Reference Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False Process Control PID PID loop control 5-9 Gains Independent 3.0 1120 58 • PLC-5/11, -5/20, • 462 -5/20E • 655 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L -5/80, -5/80E ISA 1180 • PLC-5/11, -5/20, • 560 and -5/20E • 895 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E Modes Manual 1150 • PLC-5/11, -5/20, • 372 and -5/20E • 420 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E Set Output 1130 • PLC-5/11, -5/20, • 380 and -5/20E • 440 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E Cascade Slave 1530 Master 1080 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-35 Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False 2 ABL test buffer for line 3-5 ASCII • PLC-5/11, -5/20, • 316 • 214 and -5/20E • 388 • 150 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ACB no. of characters in 3-5 buffer • 316 • 214 • PLC-5/11, -5/20, • 389 • 150 and -5/20E • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ACI string to integer 1.4 3-5 • PLC-5/11, -5/20, • 220 + C[11] and -5/20E • 140 + • PLC-5/30, -5/40, C[21.4] -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ACN string concatenate 1.9 4-7 • PLC-5/11, -5/20, • 237 + C[2.6] and -5/20E • 179 + C[5.5] • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E AEX string extract 1.9 5-9 • PLC-5/11, -5/20, • 226 + C[1.1] and -5/20E • 159 + C[2.2] • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E AHL£ set or reset lines 5-9 • PLC-5/11, -5/20, • 318 • 213 and -5/20E • 526 • 157 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� 7LPLQJ�IRU�$6&,,�LQVWUXFWLRQV�LV�WKH�WLPH�IRU�WKH�LQVWUXFWLRQ�WR�TXHXH�XS�IRU�SURFHVVLQJ�LQ�FKDQQHO��� &� �QXPEHU�RI�$6&,,�FKDUDFWHUV 1785-6.5.12 November 1998 22-36 Instruction Set Quick Reference Category Code Title Words of Time (μs) Time (μs) 1 integer floating point Memory True False True False 2 AIC integer to string 1.4 3-5 ASCII • PLC-5/11, -5/20, • 260 and -5/20E • 270 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ARD read characters 4-7 • PLC-5/11, -5/20, • 315 • 214 and -5/20E • 380 • 149 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ARL read line 4-7 • PLC-5/11, -5/20, • 316 • 214 and -5/20E • 388 • 151 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ASC string search 1.9 5-9 • PLC-5/11, -5/20, • 222 + C[1.7] and -5/20E • 151 + C[3.0] • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E ASR string compare 3-5 • PLC-5/11, -5/20, • 234 + C[1.3] • 202 and -5/20E • 169 + C[2.4] • 119 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� 7LPLQJ�IRU�$6&,,�LQVWUXFWLRQV�LV�WKH�WLPH�IRU�WKH�LQVWUXFWLRQ�WR�TXHXH�XS�IRU�SURFHVVLQJ�LQ�FKDQQHO��� &� �QXPEHU�RI�$6&,,�FKDUDFWHUV 1785-6.5.12 November 1998 Instruction Set Quick Reference 22-37 Category Code Title Time (μs) Time (μs) Words of 1 integer floating point Memory True False True False 2 AWA write with append 4-7 ASCII • PLC-5/11, -5/20, • 319 • 215 and -5/20E • 345 • 154 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E AWT write 4-7 • PLC-5/11, -5/20, • 318 • 215 and -5/20E • 344 • 151 • PLC-5/30, -5/40, -5/40E, -5/40L -5/60, -5/60L, -5/80, and -5/80E 8VH�WKH�ODUJHU�QXPEHU�IRU�DGGUHVVHV�EH\RQG������ZRUGV�LQ�WKH�SURFHVVRU¶V�GDWD�WDEOH� 7LPLQJ�IRU�$6&,,�LQVWUXFWLRQV�LV�WKH�WLPH�IRU�WKH�LQVWUXFWLRQ�WR�TXHXH�XS�IRU�SURFHVVLQJ�LQ�FKDQQHO��� &� �QXPEHU�RI�$6&,,�FKDUDFWHUV 1785-6.5.12 November 1998 22-38 Instruction Set Quick Reference Notes: 1785-6.5.12 November 1998 Chapter 23 Switch Setting Reference Using This Chapter For this switch setting: Go to page: Enhanced and Ethernet PLC-5 switch 1 for defining the processor’s 23-2 DH+ address Enhanced and Ethernet PLC-5 switch 2 for defining the processor’s 23-3 serial port electrical interface I/O chassis containing a PLC-5 processor 23-4 I/O chassis containing a 1771-ASB, remote I/O adapter module 23-5 I/O chassis configuration plug for defining an external or slot power 23-6 supply 1771-ASB not using complementary I/O 23-7 1771-ALX adapter module 23-9 1785-6.5.12 November 1998 23-2 Switch Setting Reference Processor Switches Switch 1 Side View of PLC-5/11, -5/20, -5/26, -5/20E Side View of PLC-5/30, -5/40, -5/46, -5/40L, processors Switch Assembly SW1 -5/60, -5/60L, -5/80, -5/86, -5/40E, and -5/80E processors Switch Assembly SW1 1234567 1234567 toggle pushed down on toggle pushed up off To select DH+ baud rate for channel 1A: Set switch: To: DH+ address 1 through 6 (See below) DH+ baud rate 7 on (down) 57.6 kbps off (up) 230.4 kbps Switch Switch DH+ DH+ Station Station Number 1 2 3 4 5 6 Number 1 2 3 4 5 6 0 on on on on on on 40 on on on on on off 1 off on on on on on 41 off on on on on off 2 on off on on on on 42 on off on on on off 3 off off on on on on 43 off off on on on off 4 on on off on on on 44 on on off on on off 5 off on off on on on 45 off on off on on off 6 on off off on on on 46 on off off on on off 7 off off off on on on 47 off off off on on off 10 on on on off on on 50 on on on off on off 11 off on on off on on 51 off on on off on off 12 on off on off on on 52 on off on off on off 13 off off on off on on 53 off off on off on off 14 on on off off on on 54 on on off off on off 15 off on off off on on 55 off on off off on off 16 on off off off on on 56 on off off off on off 17 off off off off on on 57 off off off off on off 20 on on on on off on 60 on on on on off off 21 off on on on off on 61 off on on on off off 22 on off on on off on 62 on off on on off off 23 off off on on off on 63 off off on on off off 24 on on off on off on 64 on on off on off off 25 off on off on off on 65 off on off on off off 26 on off off on off on 66 on off off on off off 27 off off off on off on 67 off off off on off off 30 on on on off off on 70 on on on off off off 31 off on on off off on 71 off on on off off off 32 on off on off off on 72 on off on off off off 33 off off on off off on 73 off off on off off off 34 on on off off off on 74 on on off off off off 35 off on off off off on 75 off on off off off off 36 on off off off off on 76 on off off off off off 37 off off off off off on 77 off off off off off off 1785-6.5.12 November 1998 Switch Setting Reference 23-3 Switch 2 Bottom View of PLC-5/11, -5/20, -5/26, and Bottom View of PLC-5/30, -5/40, -5/46 -5/40L, -5/60, -5/60L, -5/80, -5/20E processors Switch Assembly SW2 -5/86, -5/40E, and -5/80E processors Switch Assembly SW2 Front of Processor Front of Side View Processor toggle pushed toward bottom on toggle pushed 12 345 67 8 9 10 12 3 4 5 6 7 8 9 10 toward top off Set Switches: To Specify: 1 2 3 4 5 6 7 8 9 10 RS-232C on on on off off on on off on off RS-422A off off on off off off off off on off RS-423 on on on off off on off off on off 1785-6.5.12 November 1998 23-4 Switch Setting Reference I/O Chassis Backplane PLC-5 Processor in the I/O Chassis Switch Last State 1 Outputs of this I/O chassis remain in their last state when on a hardware failure occurs. 1 Outputs of this I/O chassis are turned off when a off hardware failure occurs. 1 Always Switches Off Addressing 45 2- slot off off 1- slot off on 1/2 - slot on off Not allowed on on Switches Memory Module Transfer 67 2 3 off off memory module transfer to processor memory at powerup. memory module transfers to processor memory if processor memory on on not valid. memory module does not transfer to processor memory. on off Switch Processor Memory Protection 8 Pressed in Processor memory protection disabled. off at top ON (closed) 4 Processor memory protection enabled. on Pressed in at bottom OFF (open) 1 Regardless of this switch setting, outputs are turned off when any of the following occurs: processor detects a major fault an I/O chassis backplane fault occurs you select program or test mode you set a status file bit to reset a local rack If a memory module is not installed and processor memory is valid, the processor's PROC LED 2 indicator blinks, and the processor sets S:11/9 in the major fault status word. Power down the processor chassis and either install the correct memory module or set switch 6 ON. 3 If the processor's keyswitch is set in REMote, the processor enters remote RUN after it powers up and has its memory updated by the memory module. 4 You cannot clear processor memory when this switch is on. 19309 1785-6.5.12 November 1998 Switch Setting Reference 23-5 1771-ASB Remote I/O Adapter or 1771-ALX Extended-Local I/O Adapter Switch Last State 1 Outputs of this I/O chassis remain in their last state when a communication on fault is detected by this I/O adapter. 1 Outputs of this I/O chassis are turned off when a communication off fault is detected by this I/O adapter. Always Switch Off Processor Restart Lockout 2 2 on Processor can restart the I/O chassis after a communication fault. Always You must manually restart the I/O chassis with a switch wired to the off Off 1771-AS or -ASB. Switches Addressing 5 6 Pressed in off off 2-slot at top ON (closed) on off 1-slot 3 Pressed in 1/2-slot off on 3 at bottom OFF (open) on on Not allowed 19308 ATTENTION: If you set this switch to the ON position, when a communication fault is detected, putputs connected to this chassis remain in their last state to allow machine motion to continue. We recommend that you set switch 1 to the OFF position to de-energize outputs wired to this chassis when a fault is detected. Also, if outputs are controlled by inputs in a different rack and a remote I/O rack fault occurs (in the inputs rack), the inputs are left in their last non-faulted state. The outputs may not be properly controlled and potential personnel and machine damage may result. If you want your inputs to be anything other than their last non-faulted state, then you need to program a fault routine. Set this switch to ON if you plan to use I/O rack auto-configuration. The 1771-ASB series A adapter does not support 1/2-slot addressing. 1785-6.5.12 November 1998 23-6 Switch Setting Reference I/O Chassis Configuration Plug Y N 1. Locate the chassis configuration plug (between the first two left-most slots of the chassis). 2. Set the I/O chassis configuration plug. The default setting is N (not using a power supply module in the chassis). USING POWER SUPPLY MODULE IN THE CHASSIS? Y N Y N Important: You cannot power a single I/O chassis with both a power supply module and an external power supply. Set Y when you install Set N when you a power supply module use an external in the chassis. power supply. 17075 1785-6.5.12 November 1998 Switch Setting Reference 23-7 Remote I/O Adapter Module (1771-ASB Series C and D) without Complementary I/O Pressed in at top ON (closed) Pressed in at bottom OFF (open) SW -1 12 34 56 7 8 O N O SW -2 F F 1 234 56 O N O F F First I/O Group Number I/O Rack Number (see below) (see next page) Link Response: ON*for series B emulation OFF*for unrestricted Switch Communication Rate Scan: 12 ON*for all but last 4 slots OFF*for all slots ON OFF 57.6 Kbps OFF OFF 115.2 Kbps OFF ON 230.4 Kbps ON ON Not used First I/O Group 7 8 Number: 0 on on 2 on off 4 off on 6 off off 1785-6.5.12 November 1998 23-8 Switch Setting Reference (1771-ASB Series C and D) I/O Rack Number— without Complementary I/O Rack 1 2 3 4 5 6 01 on on on on on off 02 on on on on off on 03 on on on on off off 04 on on on off on on 05 on on on off on off 06 on on on off off on 07 on on on off off off 10 on on off on on on 11 on on off on on off 12 on on off on off on 13 on on off on off off 14 on on off off on on 15 on on off off on off 16 on on off off off on 17 on on off off off off 20 on off on on on on 21 on off on on on off 22 on off on on off on 23 on off on on off off 24 on off on off on on 25 on off on off on off 26 on off on off off on 27 on off on off off off 1785-6.5.12 November 1998 Switch Setting Reference 23-9 Extended-Local I/O (1771-ALX) Switch SW1 Adapter Module SW-1 1234 567 8 SW-2 Not Used OPEN First I/O Group Number I/O Rack Number Rack: 1 2 3 4 5 6 01 on on on on on off 02 on on on on off on 03 on on on on off off 04 on on on off on on 05 on on on off on off 06 on on on off off on 07 on on on off off off 10 on on off on on on 11 on on off on on off 12 on on off on off on 13 on on off on off off 14 on on off off on on 15 on on off off on off 16 on on off off off on 17 on on off off off off 20 on off on on on on 21 on off on on on off 22 on off on on off on 23 on off on on off off 24 on off on off on on 25 on off on off on off 26 on off on off off on 27 on off on off off off 1785-6.5.12 November 1998 23-10 Switch Setting Reference (1771-ALX) Configuration Plug 1. Lay the module on its right side. The configuration plugs are visible on the lower rear of the module. 2. Set the configuration plug as shown below according to your application. Configuration Plug Do not place a jumper on this set of pins. 17341 If you are using: But Not: Set Configuration Plug: 32-point I/O modules and 1771-IX or 1771-IY on the 2 lower pins any address method 1771-IX and 1771-IY 32-point I/O modules on the 2 upper pins modules and any addressing method 1785-6.5.12 November 1998 Chapter 24 Troubleshooting Using This Chapter For information about troubleshooting: Go to page: General PLC-5 processor and Channel 0 problems 24-2 PLC-5 and Ethernet PLC-5 remote I/O scanner, adapter, 24-3 or DH+ problems Extended-local I/O link problems at the PLC-5/40L or 24-4 -5/60L processor port PLC-5E Ethernet link 24-4 1771-ASB module 24-5 1771-ALX module 24-7 Unexpected PLC-5 operation when entering run mode 24-8 1785-6.5.12 November 1998 24-2 Troubleshooting PLC-5 Processor General Problems Indicator Color Description Probable Cause Recommended Action BATT Red Battery low Battery low Replace battery within 10 days Off Battery is good Normal operation No action required PROC Green Processor is in run mode and Normal operation No action required (steady) fully operational BATT Green Processor memory is being (blinking) transferred to memory module PROG PROC Red Major fault Major fault Check major fault bit in status file R E (blinking) (S:11) for error definition FORCE M RUN Clear fault bit, correct problem, and COMM return to Run mode Red Hardware fault •Processor • Clear memory and (steady) memory has reload program checksum error • Check backplane switch settings •Memory and/or insert correct memory module error module • Power down, reseat processor • Internal and power up; then, clear diagnostics have memory and reload your failed program. Replace memory module with new program; then, if necessary, replace the processor Off Processor is in program load Check power supply or test mode or is not and connections receiving power FORCE Amber SFC, I/O, and/or extended forces Normal operation No action required (steady) enabled Amber SFC, I/O, and/or extended forces (blinking) present but not enabled Off SFC, I/O, and/or extended forces not present COMM Off No transmission on channel 0 Normal operation if channel is not being used Green Transmission on channel 0 Normal operation (blinking) if channel is being used 1785-6.5.12 November 1998 Troubleshooting 24-3 Processor Communication Channel Troubleshooting Indicator Color Channel Mode Description Probable Cause Recommended Action A or B Green Remote I/O Scanner Active Remote I/O link, all Normal operation No action required (steady) adapter modules are present and not faulted Remote I/O Adapter Communicating with scanner DH+ Processor is transmitting or receiving on DH+ link Green Remote I/O Scanner At least one adapter is faulted • Power off at • Restore power to (blinking or has failed remote rack the rack rapidly or • Cable broken • Repair cable slowly) DH+ No other nodes on network Red Remote I/O Scanner Hardware fault Hardware error Turn power off, then on (steady) Remote I/O Adapter DH+ Check that the software configurations match the hardware set-up Replace the processor. Red Remote I/O Scanner All adapters faulted •Cable not • Repair cable (blinking connected or rapidly or broken slowly) • Power off at • Restore power to racks remote racks DH+ Bad communication on DH+ Duplicate Correct station address node detected Off Remote I/O Scanner Channel offline Channel is not Place channel online Remote I/O Adapter being used if needed DH+ 1785-6.5.12 November 1998 24-4 Troubleshooting Extended-Local I/O Troubleshooting Indicator Color Channel Mode Description Probable Cause Recommended Action 2 green Extended local I/O active extended-local I/O link, normal operation no action required (steady) Scanner all adapter modules are present and not faulted PLC-5/40L and -5/60L green at least one adapter is faulted • power off at • restore power to the processors only (blinking or has failed extended-local rack BATT rapidly or I/O rack slowly) • communication • restart adapters using PROG PROC fault the processor restart R lockout pushbutton E FORCE M • repair cable • cable broken RUN COMM red hardware fault hardware error Turn power off, then on. (steady) Check that the software configurations match the hardware set-up. Replace the processor. red Extended local I/O all adapters faulted • cable • repair cable (blinking Scanner disconnected or • replace or repair rapidly or broken terminator slowly) •terminator off • restore power to racks • power off at extended-local racks off channel offline channel is not being Place channel online if used needed Ethernet Status Indicator Indicator Color Description Probable Cause Recommended Action STAT Solid red Critical hardware fault Processor requires Contact your local internal repair Allen-Bradley representative BATT Blinking red Hardware or software fault (detected Fault-code dependent Contact Allen-Bradley’s and reported via a code) Global Technical Support PROG PROC (GTS) R E FORCE Off Ethernet interface is functioning Normal operation Attach the processor to an M properly but it is not attached to an active Ethernet network RUN active Ethernet network COMM Green Ethernet channel 2 is functioning Normal operation No action required ENET properly and has detected that it is connected to an active Ethernet network STAT 1785-6.5.12 November 1998 Troubleshooting 24-5 BATT Ethernet Transmit LED PROG PROC 7KH�3/&���(WKHUQHW�LQWHUIDFH�FRQWDLQV�DQ�(WKHUQHW�7UDQVPLW�/(’� R E M FORCE WKDW�OLJKWV��JUHHQ��EULHIO\�ZKHQ�WKH�(WKHUQHW�SRUW�LV�WUDQVPLWWLQJ�D� RUN COM M SDFNHW��,W�GRHV�QRW�LQGLFDWH�ZKHWKHU�RU�QRW�WKH�(WKHUQHW�SRUW�LV� UHFHLYLQJ�D�SDFNHW� ENET TRANSMIT Remote I/O System Troubleshooting Guide for the 1771-ASB Series C and D Adapter Module ACTIVE ADAPTER FAULT I/O RACK FAULT Indicators Description Probable Cause Recommended Action Active Adapter I/O Fault Rack On Off Off Normal indication; remote adapter is fully operational Off On Off RAM memory fault, watchdog timeout Replace module. On Blink Off Module placement error I/O module in incorrect slot. Place module in correct slot in chassis. Blink in unison Off Incorrect starting I/O group Error in starting I/O group number or I/O Check switch settings. number rack address On On On Module not Incorrect transmission rate setting communicating Off On On Module not Scan switch set for “all but last four slots” Reset scan switch setting. communicating in 1/4 rack Blink Off Off Remote adapter not Processor is in program or test mode Fault should be cleared by I/O scanner. actively controlling I/O Scanner is holding adapter module in fault (scanner to adapter mode communication link is 1 normal) LEDs sequence on/off Module not Another remote I/O adapter with the same Correct the address. from top to bottom communicating address is on the link. Blink alternately Off Adapter module not Processor restart lockout switch on Press reset button to clear lockout feature or 2 3 cycle power; if after repeated attempts actively controlling I/O chassis backplane switch assembly on indicators are still blinking, check: Adapter module in • push button not wired properly to field wiring processor restart lockout arm mode (adapter to scanner • wiring arm not connected to adapter module link is normal) • adapter module was reset by process or/ scanner, then immediately faulted ��,I�D�IDXOW�RFFXUV�DQG�WKH�SURFHVVRU�LV�LQ�WKH�UXQ�PRGH�EXW�LV�DFWXDOO\�RSHUDWLQJ�LQ�WKH�GHSHQGHQW�PRGH��WKH�FKDVVLV�IDXOW�UHVSRQVH PRGH�LV�VHOHFWHG�E\�WKH�ODVW�VWDWH�VZLWFK�RQ�WKH�FKDVVLV�EDFNSODQH� ��£7KH�,�2�FKDVVLV�LV�LQ�IDXOWHG�PRGH�DV�VHOHFWHG�E\�WKH�ODVW�VWDWH�VZLWFK�RQ�WKH�FKDVVLV�EDFNSODQH� ��