VMICPCI-5579 Economical, High Capacity Reflective Memory (A Real-Time Network Product) ® • Real-time network for computers with CompactPCI , PCI, or PMC interfaces • Up to 64 Mbyte of Reflective Memory with network data rate up to 13.4 Mbyte/s • High-speed, easy-to-use fiber-optic network (270 Mbaud serially) • Data written to memory in one node is also written to memory in all nodes on the network • Up to 1,000 m between nodes and up to 256 nodes • Data transferred at 13.4 Mbyte/s without redundant transfer • Data transferred at 6.7 Mbyte/s with redundant transfer • Any node on the network can generate an interrupt in any other node on the network or in all network nodes with a single command • Error detection • Redundant transmission mode for suppressing errors • No processor overhead • No processor involvement in the operation of the network • D32:D16:D8 memory access • Single 3U CompactPCI board with optional 6U front panel • PCI target data bursts supported with 33 Mbyte/s transfer rates • PCI master DMA controller. DMA transfer rates of 132 Mbyte/s maximum and 22 Mbyte/s sustained. node number would be useful in establishing the function of • Configurable endian conversions for multiple CPU architectures on the the node. network LINK ARBITRATION — The VMICPCI-5579 system is INTRODUCTION — The VMICPCI-5579 is a member a fiber-optic daisy chain ring as shown in Figure 1. Each of a high-performance, daisy-chained, fiber-optic network. transfer is passed from node-to-node until it has gone all the Data is transferred by writing to on-board global RAM. The way around the ring and reaches the originating node. Each data is automatically sent to the location in memory on all node retransmits all transfers that it receives except those that Reflective Memory boards on the network. it originated. Nodes are allowed to insert transfers between transfers passing through. PRODUCT OVERVIEW — The Reflective Memory concept provides a very fast and efficient way of sharing data across distributed computer systems. Ordering Options Sep. 26, 2002 800-655579-000 B ABC – D E F VMIC’s VMICPCI-5579 Reflective Memory interface VMICPCI-5579 –0 – allows data to be shared between up to 256 independent A = Memory Options systems (nodes) at rates up to 13.4 Mbyte/s. Each Reflective 0 to 3 = Reserved 4 = 32 Mbyte Memory board may be configured with 32 or 64 Mbyte of 5 = 64 Mbyte on-board RAM. The local RAM provides fast Read access B = Panel Options 0 = 3U Panel times to stored data. Writes are stored in local RAM and 1 = 6U Panel broadcast over a high-speed fiber-optic data path to other C = 0 (Option reserved for future use) Reflective Memory nodes. The transfer of data between Connector Data nodes is software transparent, so no I/O overhead is required. SC Connector Transmit and Receive FIFOs buffer data during peak data AMP 503948-1 (or equivalent) rates to optimize CPU and bus performance to maintain high Cable Specifications data throughput. Fiber-Optic Cable – Multimode; 62.5 Micron core. Transmitters operate at 1,300 nm at 270 Mbaud. Maximum attenuation between nodes is 9 dB. The Reflective Memory also allows interrupts to one or Minimum attenuation between nodes is .5 dB. more nodes by writing to a byte register. Three separate Fiber-Optic Cable Assemblies ABC – D E F user-definable interrupts may be used to synchronize a VMICBL-000-F4 –0 – system process, or used to follow any data. The interrupt A = Connector Type 0 = Ceramic Ferrule SC Connector always follows the data to ensure the reception of the data BC = Cable Lengths before the interrupt is acknowledged. 02 = 5 ft (1.5 m) 12 = 500 ft (152.4 m) 04 = 25 ft (7.6 m) 16 = 1,000 ft (304.8 m) 05 = 50 ft (15.2 m) 19 = 1,500 ft (457.3 m) The VMICPCI-5579 requires no initialization unless 07 = 100 ft (30.4 m) 22 = 2,000 ft (609.7 m) interrupts are being used or endian byte swapping is desired. 08 = 150 ft (45.7 m) 25 = 2,460 ft (750.0 m) 09 = 200 ft (60.9 m) 29 = 3,280 ft (1,000 m) 11 = 350 ft (106.7 m) Each node on the system has a unique identification For Ordering Information, Call: number between 0 and 255. The node number is established 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 E-mail: info@vmic.com Web Address: www.vmic.com during hardware system integration by placement of jumpers Copyright © February 1998 by VMIC on the board. This node number can be read by software by Specifications subject to change without notice. accessing an on-board register. In some applications, this VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 1 VMICPCI-5579 INTERRUPT TRANSFERS — In addition to portion of the system. This optical error rate depends on the transferring data between nodes, the VMICPCI-5579 will length and type of fiber-optic cable. Assuming an optical -12 allow any processor in any node to generate an interrupt on error rate of 10 , the error rate of the VMICPCI-5579 is -10 any other node. These interrupts would generally be used to 1.6 x 10 transfers/transfer. indicate to the receiving node that new data has been sent and is ready for processing. These interrupts are also used to However, the rate of undetectable errors is less than -20 indicate that processing of old data is completed and the 2.56 x 10 transfers/transfer. When a node detects an error, receiving node is ready for new data. the erroneous transfer is removed from the system and a PCI bus interrupt is generated, if enabled. Three interrupts are available. The user may define the function for each interrupt. Any processor can generate an The VMICPCI-5579 can be operated in a redundant interrupt on any other node on the network. In addition, any transfer mode in which each transfer is transmitted twice. In processor on the network can generate an interrupt on all this mode of operation, the first of the two transfers is used nodes on the network. Interrupts are generated by simply unless an error is detected in which case the second transfer writing to a VMICPCI-5579 register. is used. In the event that an error is detected in both transfers, the node removes the transfer from the system. The All data and interrupt command transfers contain the probability of both transfers containing an error is -20 node number of the node that originated the transfer. This 2.56 x 10 , or about one error every 1,470,000 years at information is used primarily so the originating node can maximum data rate. remove the transfer from the network after the transfer has traversed the ring. The node identification is also used by ENDIAN CONVERSIONS — Data lane steering can nodes receiving interrupt commands. When a node receives be configured in a Control Register to allow CPUs of an interrupt command for itself, it places the identification different architectures to communicate. Byte swap, Word number of the originating node in a FIFO. Up to 64 interrupts swap, and Byte-Word swap options are available. can be stacked in the FIFO. During the interrupt service routine, the identification of the interrupting node can be read PROTECTION AGAINST LOST DATA — Data from the FIFO. Twenty-one bits of data are also transmitted received by the node from the fiber-optic cable is error with the interrupt and stored in the interrupt FIFO. checked and placed in a receive FIFO. Arbitration with accesses from the PCI bus then takes place, and the data is PCI INITIATOR/DMA CAPABILITIES — The written to the node’s RAM and to the node’s transmit FIFO. VMICPCI-5579 supports DMA operations. The DMA Data written to the board from the PCI bus is placed directly capability is initiated by a PCI host. After the DMA engine is into RAM and into the transmit FIFO. Data in the transmit initialized by a host, the VMICPCI-5579 will request the PCI FIFO is transmitted by the node over the fiber-optic cable to bus as appropriate and move up to 64 Mbyte as a PCI the next node. initiator. This capability removes the CPU from the responsibility of requesting the PCI bus and moving the data The product is designed to prevent either FIFO from itself. This feature is very useful for moving large blocks of becoming full and overflowing. It is important to note the data. The PCI architecture ensures that the VMICPCI-5579 only way that data can start to accumulate in FIFOs is for data does not monopolize the PCI bus during this process. Large to enter the node at a rate greater than 13.4 Mbyte/s or DMA blocks will automatically be split into smaller bursts on 6.7 Mbyte/s in redundant mode. Since data can enter from the the PCI bus by the DMA engine. The VMICPCI-5579 can be fiber and from the PCI bus, it is possible to exceed these rates. programmed to issue a PCI interrupt at the conclusion of a If the transmit FIFO becomes half-full, a bit in the Status DMA transfer or the host can poll the status of the DMA Register is set. This is an indication to the node’s software process. The status of the DMA can be accessed from the that subsequent writes to the Reflective Memory should be board, if required. Although the DMA engine can do both suspended until the FIFO is less than half-full. If the half-full DMA reads and DMA writes, they cannot occur indication is ignored and the transmit FIFO becomes full, simultaneously. The VMICPCI-5579 can burst data onto the then writes to the Reflective Memory will be acknowledged PCI bus at a maximum rate of 132 Mbyte/s and sustain with a STOP*. No data will be lost. 22 Mbyte/s. If the target operates at a slower rate, the PCI handshaking capabilities will throttle the data rate. NETWORK MONITOR — There is a bit in a Status Register that can be used to verify that data is traversing the ERROR MANAGEMENT — Errors are detected by ring (that is, the ring is not broken). This can also be used to the VMICPCI-5579 with the use of the error detection measure network latency. facilities of the Hot Link chipset and additional parity encoding and checking. The error rate of the VMICPCI-5579 is a function of the rate of errors produced in the optical 2 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859 VMICPCI-5579 VMIC offers single fiber cable assemblies and adapters 3. TCP/IP Protocols - Full support for the that are compatible with the VMICPCI-5579 in length internetworking TCP/IP protocols allows ranging from 1.5 to 1,000 m. These cable assemblies are peer-to-peer communication between applications U.L./NEC-rated OFNP and have a 2.5 mm SC-style without the need to design and implement custom connector on each end. communications protocols. SPECIFICATIONS INTERCONNECTION Memory Size: 32 or 64 Mbyte Cable Requirements: Two fiber-optic cables PCI Transfer Rate: 33 Mbyte/s as a Target, Cable Length: 1,000 m maximum between nodes 22 Mbyte/s as DMA Initiator Configuration: Daisy-chain ring up to 256 nodes TRANSFER SPECIFICATION Power Requirements: 3 A maximum at +5 VDC Transfer Rate: 13.4 Mbyte/s (longword accesses) 2 A maximum at 3.3 VDC without redundant transfer PHYSICAL/ENVIRONMENTAL 6.7 Mbyte/s (longword accesses) with redundant transfer Temperature Range: 0 to 65 ˚C, operating with MEMORY CONFIGURATION forced air cooling. -40 to 85 ˚C, storage. The host system automatically allocates to the Relative Humidity: 20 to 80 percent, noncondensing VMICPCI-5579 a memory space on the CompactPCI bus which is equal to the board memory option. All DATA TRANSFERS memory contained on the VMICPCI-5579 is fully read/write accessible by the PCI host system with the Data written into the Reflective Memory is broadcast to exception of the first 40 (HEX) bytes which have been all nodes on the network without further involvement of replaced with status and control registers. the sending or receiving nodes. Data is transferred from memory locations on the sending nodes to corresponding SOFTWARE DRIVER memory locations on the receiving nodes. ® VxWorks and Windows NT drivers are available. The A functional block diagram of the VMICPCI-5579 is VMIPCI/SW-RFM1 Network and Shared Memory shown in Figure 2. Driver provides an applications program with three convenient methods for exchanging data among hosts TRADEMARKS connected to the same Reflective Memory network: The VMIC logo is a registered trademark of VMIC. 1. Programmed I/O (Peek and Poke) - An applications Windows NT is a registered trademark of Microsoft program can treat the memory on the Reflective Corporation. CompactPCI is a registered trademark of PCI Memory device as ordinary memory in which the Industrial Computer Manufacturers’ Group. Other registered program can use ordinary load and store accesses. trademarks are the property of their respective owners. 2. Direct Memory Access (DMA) - On systems where the performance penalty for individual bus accesses is unacceptably high, the DMA feature is available to transfer data in variable-sized blocks. VMIC • 12090 South Memorial Parkway • Huntsville, Alabama 35803-3308 3 VMICPCI-5579 C 5 P 5 U 7 CompactPCI 9 Chassis with VMICPCI-5579 PCI Chassis with PCI bus VMIPCI-5579 Workstation Figure 1. Network Example Using Reflective Memory System FIBER-OPTIC FIBER-OPTIC CABLE CABLE FO FO REC'D TX HOT LINK HOT LINK RECEIVER TRANSMITTER INTERRUPT LOGIC HOT LINK INTERFACE RX TX CONTROL FIFO FIFO LOGIC CTRL CTRL CS FIFO/RCV CTRL RAM CTRL WR RAM ADDRESS CONTROL PCI PCI bus I/F 64 Mbyte RAM MAXIMUM DATA ENDIAN SWAP BUFFER Figure 2. VMICPCI-5579 Functional Block Diagram 4 For Ordering Information, Call: 1-800-322-3616 or 1-256-880-0444 • FAX (256) 882-0859