No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KAL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 1 of 1 DATE Low Profile type (P/N : ECJHVB1C106M) Individual Specification 18 May, 2005 1. Scope This specification applies to Low Profile type Multilayer Ceramic Chip Capacitor 13 type (EIA 1206), Temp. Char:X5R, Rated voltage DC16V , Nominal Capacitance 10µF. 2. Style and Dimensions Table 1 W T Symbol Dimensions(mm) L1 L 3.2+/-0.2 W 1.6+/-0.2 L T 0.85+/-0.10 L2 L1,L2 0.6+/-0.3 3. Operating Temperature Range Table 2 Temperature Characteristics Operating Temp. Range. Class2 X5R -55 to +85 °C 4. Individual Specification Table 3 Rated Nominal Part Number Temp. Char. Cap. Tolerance Voltage Capacitance ECJHVB1C106M DC 16V X5R 10 µF +/-20 % 5. Explanation of Part Numbers E C J H V B 1 C 1 0 6 M Temp. Char. Nominal Cap. Common Code Cap. Code Tolerance Rated Voltage Code Code Voltage Show in Size Code 1C DC 16V Table 4 Code Size Show in Packaging Style 13type (EIA1206) Table 3 H Low Profile type Code Packaging Style V φ180Reel Paper Taping 4000pcs./reel 6. Temperature Characteristics Table 4 Temp. Char. Capacitance Change rate from Temperature Measurement Reference Code Temperature Range Temperature Temp. Char. Without voltage application -55 to +85 °C B X5R +/-15 % +25 °C 7. Soldering method Flow soldering shall not be applied. Note ; APPROVAL CHECK DESIGN Panasonic Electronic Devices Co., Ltd. Y.Sakaguchi S. Endoh T.Shinriki No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 1 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 1. Information 1- 1.Applicable laws and regulations (1) Any ozone-depleting substances listed in the Montreal Protocol are not used in the manufacturing processes for parts and materials used in this product. (2) PBB and PBDE are intentionally excluded from materials used in this product. (3) All the materials used in this product are registered materials under the Law Concerning Examination and Regu- lation of Manufacture and Handling of Chemical Substances. (4) This product complies with the RoHS, DIRECTIVE 2002/95/EC on the Restriction of the use of certain Hazard- ous Substances in electrical and electronic equipment. (5) This product is exported with export procedures under export related laws and regulations such as the Foreign Exchange and Foreign Trade Law. 1- 2.Limitation in Applications This product was designed and manufactured for general-purpose electronic equipment such as household, office, information & communication equipment. When the following applications, which are required higher reliability and safety because the trouble or malfunction of this product may threaten the lives and/or properties, are examined, separate specifications suitable for the application should be exchanged. ・Aerospace / Aircraft equipment, Warning / Antitheft equipment, Medical equipment, Transport equipment (Motor vehicles, Trains, Ship and Vessel ), Highly public information processing equipment, Others equivalent to the above. 1- 3.Production factory (1) Panasonic Electronic Devices Hokkaido Co., Ltd. (2) Tianjin Matsushita Electronic Components Co., Ltd.(TMCOM) (3) Matsushita Electronic Devices (M) Sdn. Bhd.(MEDEM) 2. Scope 2- 1.This specification applies to Low Profile type Multilayer Ceramic Chip Capacitor 13type (P/N : ECJHVB1C106M) . If there is a difference between this common specification and any individual specifications, priority shall be given to the individual specifications. 2- 2.This product shall be used for general-purpose electronic equipment such as audiovisual, household, office, informa- tion & communication equipment. Unreasonable applications may accelerate performance deterioration or short/open circuits as failure modes affect- ing the life end. Adequate safety shall be ensured especially for product design required a high level of safety with the following con- siderations. 1) Previously examine how a single trouble in this product affects the end product. 2) Design a protection circuit as Failsafe-design to avoid unsafe system resulting from a single trouble with this product. Whenever a doubt about safety arises from this product, immediately inform us for technical consultation without fail, please. 2- 3.This specification is a part of contract documents pertaining to the trade made by and between your company and Matsushita Electric Industrial Co., Ltd. 3. Part Number Code ECJ H VB1C 106 M (1) (2) (3) (4) (5) (6) (7) 3- 1.Common Code (1) ECJ : Multilayer Ceramic Chip Capacitors 3- 2.Size (2), Packaging Styles (3), Temperature Characteristic (4), Rated Voltage (5), Capacitance Tolerance (7) : Shown in Individual Specification. Note ; APPROVAL CHECK DESIGN Panasonic Electronic Devices Co., Ltd. Y.Sakaguchi S.Endoh T.Shinriki No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 2 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 3- 3.Nominal Capacitance (6) The Nominal Capacitance value is expressed in pico farads(pF) and is Symbol (Ex.) Nominal Cap. identified by a three-digit number ; the first two digit 105 1000000pF(1µF) represent significant figures and the last digit specifies the number of 225 2200000pF(2.2µF) zero to follow. 106 10000000pF(10µF) 4. Operating Temperature Range Shown in Individual Specification. 5. Performance The performance of the capacitor and its test condition shall be specified in Table 2. 5- 1.Pretreatment Before test and measurements, the following pretreatment shall be applied when necessary. 5-1-1. Heat Treatment The capacitors shall be kept in a temperature of 150+0/-10°C for 1 hour and then shall be stored in a room tem- perature for 48±4 hours, before initial measurement. 5-1-2. Voltage Treatment D.C. voltage shall be applied for 1 hour in the specified test condition and then shall be stored in a room temperature for 48 +/- 4 hours, before initial measurement. 6. Test Unless otherwise specified, all test and measurements shall be made at a temperature of 15 to 35°C and at a relative humidity of 45 to 75%. If results obtained are doubted a further test should be carried out at a temperature of 20±2℃ and a relative humidity of 60 to 70%. 7. Structure The structure shall be in a monolithic form as shown in Fig. 1. Fig. 1　 Table 1 No. Name ① Dielectric ② Inner electrode ③ Substrate electrode ④ Intermediate electrode ⑤ External electrode . Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 3 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 Table 2 No Contents Performance Test Method 1 Appearance There shall be no defects which affect With a magnifying glass (3 times). the life and use. 2 Dimensions Shown in Individual Specification. With slide calipers and a micrometer. 3 Dielectric Withstand- There shall be no dielectric breakdown Test voltage : 250% of rated voltage ing voltage or damage. Apply a DC voltage of the above value for 1 to 5 seconds. Charge/discharge current shall be within 50mA. Insulation Measuring voltage : Rated voltage 500/C MΩ min. 4 Resistance(I.R.) Measuring voltage time : 60+/-5s (C : Nominal Cap. in µF) Charge/discharge current shall be within 50mA. 5 Capacitance Shall be within the specified tolerance. Measuring Measuring 6 Dissipation Factor 0.15 max. Frequency Voltage (tan δ) 1kHz+/-10% 1.0+/-0.2Vrms For the class2 Capacitors, perform the heat treatment in par. 5-1-1. Our Measurement instrument is shown in the Table 3. 7 Temperature Without Temp. Char. Measure the capacitance at each stage by Coefficient Voltage X5R : Within +/- 15% changing the temperature in the order of step 1 Appli- to 4 shown in the table below. Calculate the cation rate of change regarding the capacitance at stage 3 as the reference. (Unit : °C) Temp. Stage Char. 1 2345 X5R 25+/-2 -55+/-3 25+/-2 85+/-2 25+/-2 8 Adhesion The terminal electrode shall be free Solder the specimen to the testing jig shown in from peeling or signs of peeling. the figure., and apply a 5N force in the arrow direction for 10 seconds. Material : Alumina board (95% min.) or glass epoxy board. Thickness : 1.0mm min. (continue) Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 4 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 Table 2 No Contents Performance Test Method 9 Bending Appear- There shall be no cracks and other After soldering capacitor on the substrate 1mm Strength ance mechanical damage. of bending shall be applied for 5 seconds. Bending speed : 1mm/s (shown in Fig. 3) Capaci- Temp. Change from the value tance Char. before test. X5R Within +/- 12.5% 10 Vibration Appear- There shall be no cracks and other Solder the specimen to the testing jig shown Proof ance mechanical damage. in Fig. 2. Apply a variable vibration of 1.5mm total amplitude in the 10 to 55 to10Hz vibration frequency range swept in 1 min. in 3 mutually Capaci- Shall be within the specified tolerance. tance perpendicular directions for 2 hours each, a total of 6 hours. Shall meet the specified initial value. tan δ 11 Resistance Appear- There shall be no cracks and other Solder both method to Solder ance mechanical damage. Preconditioning : Heat Temperature Heat (See 5.1.1)/Class2 Solder temperature : 270+/-5°C Capaci- Temp. Change from the value tance Char. before test. Dipping period : 3+/-0.5s Preheat condition : X5R Within +/- 7.5% Order Temp.(°C) Period(s) Shall meet the specified initial value. tan δ 1 80 to 100 300 to 360 2 150 to 200 300 to 360 I.R. Shall meet the specified initial value. Use solder H63A(JIS-Z-3282).For the flux, With- There shall be no dielectric breakdown use rosin (JIS-K-5902) ethanol solution of a stand or damage. concentration of about 25% by weight. Use voltage tweezers for the holder to dip the specimen. Recovery : 48+/-4 hours 12 Solderability More than 95% of the soldered area of Solder temperature : 230+/-5°C Dipping period : 4+/-1s both terminal electrodes shall be Dip the specimen in solder so that both covered with fresh solder. terminal electrodes are completely submerged. Use solder H63A(JIS-Z-3282). For the flux use rosin (JIS-K-5902) of ethanol solution of a concentration of about 25% by weight. Use tweezers for the holder to dip the specimen. (continue) Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 5 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 Table 2 No Contents Performance Test Method 13 Temperature Appear- There shall be no cracks and other Solder the specimen to the testing jig shown cycle ance mechanical damage. in Fig. 2. Condition the specimen to each temperature from step 1 to 4 in this order for Capaci- Temp. Change from the value the period shown in the table below. Regard- tance Char. before test. ing this conditioning as one cycle, perform 5 cycles continuously. X5R Within +/- 7.5% Temperature Period Shall meet the specified initial value. tan δ Step (°C) (min.) I.R. Shall meet the specified initial value. Minimum operation 1 30+/-3 With- There shall be no dielectric breakdown temperature +/- 3 stand or damage. 2 Room temperature 3 max. voltage Maximum operation 3 30+/-3 temperature +/-5 4 Room temperature 3 max. For the class2 capacitors, perform the heat treatment in par. 5-1-1. Before the measurement after test, the specimen shall be left to stand at room temperature for the following period : 48+/-4 h 14 Moisture Appear- There shall be no cracks and other For the class2 capacitors, perform the heat Resistance ance mechanical damage. treatment in par. 5-1-1. Solder the specimen to the testing jig shown Capaci- Temp. Change from the value in Fig. 2. tance Char. before test. Test temperature : 40+/-2°C Relative humidity : 90 to 95% X5R Within +/- 12.5% Test period : 500+24/0 h 0.25 max. tan δ Before the measurement after test, the spe- I.R. 50/C MΩ min. cimen shall be left to stand at room tempera- (C : Nominal Cap. in µF) ture for the following period : 48+/-4 h 15 Moisture Appear- There shall be no cracks and other For the class2 capacitors, perform the heat Resistant ance Mechanical damage. treatment in par. 5-1-2. Loading Solder the specimen to the testing jig shown Capaci- Temp. Change from the value in Fig. 2. tance Char. before test. Test temperature : 40+/-2°C Relative humidity : 90 to 95% X5R Within +/- 12.5% Applied voltage : Rated voltage tan δ 0.25 max. (DC Voltage) Charge/discharge current : within 50mA. I.R. 25/C MΩ min. Test period : 500+24/0 h (C : Nominal Cap. in µF) Before the measurement after test, the spe- cimen shall be left to stand at room tempera- ture for the following period : 48+/-4 h (continue) Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 6 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 Table 2 No Contents Performance Test Method 16 High Tem- Appear- There shall be no cracks and other For the class2 capacitors, perform the voltage perature ance mechanical damage. Resistant treatment in par. 5-1-2. Loading Capaci- Temp. Change from the value be- Solder the specimen to the testing jig shown tance Char. fore test. in Fig. 2. Test temperature : X5R Within +/- 12.5% Max. Rated temp. +/-3°C 0.25 max. tan δ Applied voltage : Rated voltage (DC Voltage) Charge/discharge current : within 50mA. I.R. 50/C MΩ min. Test period : 1000+48/0 h (C : Nominal Cap. in µF) Before the measurement after test, the spe- cimen shall be left to stand at room tempera- ture for the following period : 48+/-4 h When uncertainty occurs in the weather resistance characteristic tests (temperature cycle, moisture resistance, moisture resistant loading, high temperature resistant loading), the same tests shall be performed for the capacitor itself. Table 3 Our Standard Measuring Instrument Measuring Instrument 4278A 1kHz/1MHz Capacitance Meter (Agilent Technologies) Measuring Mode Parallel Mode Recommended 16034e Test Fixture (Agilent Technologies) Measuring Jig For High Cap Type, signal voltage may be unable to be applied to depending on conditions of measuring instruments. We would appreciate it if you would confirm whether High Cap Type is under the measurable environment or not by checking that the fixed signal voltage is applied or not. (For example, ALC function is ON, HPA is expanded.) Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-KGL56E SUBJECT PAGE Multilayer Ceramic Chip Capacitors 13type (EIA 1206) 7 of 7 DATE Low Profile type (P/N : ECJHVB1C106M) Common Specification 18 May, 2005 Fig. 2 Testing jig Table 4 Type A B C (EIA) 13type 2.2 5.0 2.0 (1206) Unit : mm Material : Glass epoxy board Thickness : 1.6mm :Copper foil (0.035mm thick) :Solder resist Fig. 3 Testing jig Table 5 Type A B C (EIA) 13type 2.2 5.0 2.0 (1206) Unit : mm Material : Glass epoxy board Thickness : 1.6mm :Copper foil (0.035mm thick) :Solder resist Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 1 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 1. Precautions for Use The Multilayer Ceramic Chip Capacitors (hereafter referred to as “Capacitors”) may fail in a short circuit mode in an ！ open-circuit mode when subjected to severe conditions of electrical, environmental and/or mechanical stress beyond the specified “Rating and specified “Conditions” in the Specifications, resulting in burn out, flaming or glowing in the worst case. The following “Operating Conditions and Circuit Design” and “Precautions for Assembly” shall be taken in your major consideration. If you have a question about the “Precautions for Use”, please contact our engineering section or factory. 2. Operating Conditions and Circuit Design 2- 1.Circuit Design 2-1-1. Operating Temperature Range The specified “Operating Temperature Range” in the Specifications is absolute maximum and minimum temperature rating. So in any case, each of the Capacitors shall be operated within the specified “Operating Temperature Range”. 2-1-2. Design of Voltage application The Capacitors shall not be operated exceeding the specified “Rated Voltage” in the Specification. If voltage ratings are exceeded, the Capacitors could result in failure or damage. In case of application of DC and AC voltages to the Capacitors, the designed peak voltage shall be within the specified “Rated Voltage”. In case of AC of pulse voltage, the peak voltage shall be within the specified “Rated Voltage”. If high frequency voltage or fast rising pulse voltage is applied continuously even within the “Rated Voltage”, contact our engineering section before use. Such continuous application affects the life of the Capacitors. 2-1-3. Charging and Discharging Current The Capacitors shall not be operated beyond the specified “Maximum Charging/Discharging Current Ratings” in the Specifications. Applications to a low impedance circuit such as a ”secondary power circuit” are not recommended for safety. 2-1-4. Temperature Rise by Dielectric Loss of the Capacitors The “Operating Temperature Range” mentioned above shall include a maximum surface temperature rise of 20℃, which is caused by the Dielectric loss of the Capacitor and applied electrical stresses (such as voltage, frequency and wave form etc.). It is recommended to measure and check “Surface Temperature of the Capacitor” in your equipment at room temperature (up to 25℃). 2-1-5. Restriction on Environmental Conditions The Capacitors shall not be operated and / or stored under the following environmental conditions. (1) Environmental conditions (a) To be exposed directly to water or salt water (b) To be dew formation (c) Under conditions of corrosive gases such as hydrogen sulfide, sulfurous acid, chlorine and ammonia (2) Under severe conditions of vibration or impact beyond the specified conditions in the Specifications 2-1-6. DC voltage characteristics The Capacitors (Class 2) employ dielectric ceramics with dielectric constant having voltage dependency, and if applied DC voltage is high, capacitance may broadly change. For the specified capacitance, the following should be confirmed. (1) If capacitance change by applied voltage is within the allowable range, or if its application allows unlimited capacitance change. (2) DC voltage characteristics demonstrate, even if applied voltage is under the rated voltage, capacitance change rate increases with higher voltage (Capacitance down). Accordingly, when the Capacitors are used for circuits with narrow capacitance allowable range such as time constant circuits, we recommend to apply lower voltage upon due consideration on capacitance aging in addition to the above. Note ; APPROVAL CHECK DESIGN Panasonic Electronic Devices Co., Ltd. Y.Sakaguchi S.Endoh T.Shinriki No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 2 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 Capacitance change vs. DC voltage DC voltage (V) 2-1-7. Capacitance aging The ceramic dielectrics of the Capacitors (Class 2) have capacitance aging. Accordingly, when the Capacitors are used for the circuits, which require a narrow capacitance allowable range, such as time constant circuits, pay due consideration to capacitance aging for use. Under Ordinary Temperature Before and After Heat treatment Heat treatment Time (h) Time (h) 2-1-8. Piezoelectricity Dielectrics used for the Capacitors (Class 2) may cause the following Piezoelectricity (or Electrostriction). (1) If the signal of a specific frequency is applied to the Capacitors, electric and acoustic noise may be generated by resonating the characteristic frequency which is determined by the dimensions of the Capacitor. As a measure to prevent this phenomenon, changing the size of the Capacitor is effective to change its resonance frequency. Also there is another measure changing the materials of the Capacitors to the Low-loss type, which has no (or less) piezoelectricity, or to Class1. which has no (or less) piezoelectricity, or to Class1 is also available. (2) Vibration or impact applied to the Capacitors may cause noise because mechanical force is converted to electrical signals (Especially, application to around the amplifier unit) . As a measure to prevent this phenomenon, changing the materials of the Capacitor to the Low-loss type, which has no (or less) piezoelectricity, or to Class1 is also available. (3) Even if a whining sound is generated, there is no problem in product performance and reliability, however, check the worrisome phenomenon which may generate noise in your equipment. As a measure to prevent this phenomenon, changing to the Capacitor different in characteristics, size and shape as shown in the (1), (2) above is effective. As the other measures, changing the mounting direction of the Capacitors to bring under control the resonance with equipment bodies such as printed circuit board, or the Capacitors are fixed with equipment bodies such as printed circuit board by adhesive may be effective. 2- 2.Design of Printed Circuit Board 2-2-1. Selection of Printed Circuit Board When the Capacitors are mounted and soldered on an Aluminum Substrate, the substrate has influences on Capacitor’s reliabilities against “Temperature Cycles” and “Heat shock” because of difference in thermal expansion coefficient between them. It shall be carefully confirmed that the actual board applied does not deteriorate the characteristics of the Capacitors. Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 3 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 2-2-2. Design of Land Pattern (1) Recommended land dimensions are shown below for proper amount of solder to prevent cracking at the time of excessive stress to the Capacitors due to increased amount of solder. { Recommended land dimensions (Ex.) } [ For General Electronic Equipment, High Capacitance, Low ProfileType, 100V･200V series ] Unit in mm SMD Land Type Component Dimension ab c (EIA) LW T 06 (0201) 0.6 0.3 0.3 0.2 to 0.3 0.25 to 0.3 0.2 to 0.3 10 (0402) 1.0 0.5 0.5 0.4 to 0.5 0.4 to 0.5 0.4 to 0.5 11 (0603) 1.6 0.8 0.8 0.8 to 1.0 0.6 to 0.8 0.6 to 0.8 Solder 12 (0805) 2.0 1.25 0.6 to 1.25 0.8 to 1.2 0.8 to 1.0 0.8 to 1.0 b a resist 13 (1206) 3.2 1.6 0.6 to 1.6 1.8 to 2.2 1.0 to 1.2 1.0 to 1.3 23 (1210) 3.2 2.5 1.4 to 2.5 1.8 to 2.2 1.0 to 1.2 1.8 to 2.3 34 (1812) 4.5 3.2 2.5 to 3.2 3.0 to 3.5 1.2 to 1.6 2.3 to 3.0 [ Wide-width Type ] Land SMD Unit in mm Type Component Dimension ａｂ ｃ (EIA) ＬＷ Ｔ 21(0508) 1.25 2.0 0.85 0.5 to 0.7 0.5 to 0.6 1.4 to 1.9 31(0612) 1.6 3.2 0.85 0.8 to 1.0 0.6 to 0.7 2.5 to 3.0 Solder a b resist [ Array Type ] 4 Cap. Array Unit in mm P/2 P c Type Component Dimension ab c P (EIA) LW T 12 0.55 0.5 0.2 0.4 2.0 1.25 0.85 (0805) to 0.75 to 0.6 to 0.3 to 0.6 13 0.9 0.7 0.35 0.7 3.2 1.6 0.85 (1206) to 1.1 to 0.9 to 0.45 to 0.9 SMD Land 2-fold Array Unit in mm c Component Type Dimension ab c P SMD (EIA) LW T 11 0.3 0.45 0.3 0.54 1.37 1.0 0.6 (0504) to 0.4 to 0.55 to 0.4 to 0.74 Land P (2) The size of lands shall be designed to be equal between the right and left sides. If the amount of solder on the right land is different from that on the left land, the component may be cracked by stress to one side of the component since the side with a larger amount of solder solidifies later at the time of cooling. Recommended Amount of Solder (a) Excessive amount (b) Proper amount (c)Insufficient of solder of solder amount ←solder ←solder ←solder ↑ ↑ ↑ PC PC PC Note ; b b a a c c No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 4 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 2-2-3. Applications of Solder Resist Applications of Solder resist are effective to prevent solder bridges and to control amounts of solder on PC boards. (1) Solder resist shall be utilized to equalize the amounts of solder on both sides. (2) If the Capacitors are arranged in succession, solder resist shall be used to divide the pattern in the mixed mounting with a component with lead wires or in the arrangement near a chassis etc. See the table below. NG Examples and Recommended Examples NG Examples Improved Examples by pattern division Mixed mounting The lead wire of Solder resist with a component with a component with lead wires lead wires Sectional view Sectional view Arrangement Chassis Solder resist near chassis Solder (ground solder) Sectional view Sectional view Retrofitting of Soldering iron Lead wire of Solder resist Component with lead Retrofitted wires component Sectional view Sectional view Lateral arrangement Land Portion to be Solder resist excessively soldered 2-2-4. Component Layout The Capacitors / components shall be placed on the PC board so as to have both electrodes subjected to uniform stresses, or to position the component electrodes at right angles to the grid glove or bending line to avoid cracking in the Capacitors caused by the bending of the PC board after or during placing / mounting the Capacitors / components on the PC board. (1) The recommended layout of the Capacitor to minimize mechanical stress caused by warp or bending of a PC board is as below. NG Example Recommended Example Warp of Lay out the Capacitor Circuit board sideways against the stressing direction (2) The following drawing is for your reference since mechanical stress near the dividing/breaking position of a PC board varies depending on the E mounting position of the Capacitors. D (3) The magnitude of mechanical stress applied to Perforation the Capacitors when the circuit board is divided is C in the order of push back < slit < V-groove < perforation. Also take into account the layout of the Capacitors A and the dividing/breaking method. B Slit 2-2-5. Mounting Density and Spaces If components are arranged in too narrow spaces, the Magnitude of stress　A＞B＝C＞D＞E components are affected by Solder bridges and Solder balls. Each space between components should be carefully determined. Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 5 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 3. Precautions for Assembly 3- 1.Storage (1) The Capacitors shall be stored under 5 - 40℃ and 20 - 70%RH, not under severe conditions of high temperature and humidity. (2) If the storage place is humid, dusty, and contains corrosive gasses (hydrogen sulfide, sulfurous acid, hydrogen chloride and ammonia, etc.), the solderability of the terminal electrodes may deteriorate. Also, storage in a place subjected to heating or exposed to direct sunlight causes deformed tapes and reels of taped version and/or components sticking to tapes, which results in troubles at the time of mounting. (3) The storage period shall be within 6 months. Products stored for more than 6 months shall be checked their solderability before use. (4) The Capacitors of high dielectric constant series (Class 2, Characteristic B,X7R,X5R and F,Y5V) change in capacitance with the passage of time, “Capacitance aging”, due to the inherent characteristics of ceramic dielectric materials. The changed capacitance can be recovered by heat treatment to each initial value at the time of shipping. (See 2. Operating Condition and Circuit Design, 2-1-7. Capacitance aging) (5) When the initial capacitance is measured, the Capacitors shall be heat-treated at 150+0/-10℃ for 1 hour and then subjected to ordinary temperature and humidity for 48±4 hours before measuring the initial value. 3- 2.Adhesives for Mounting (1) The amount and viscosity of an adhesive for mounting shall be such that the adhesive shall not flow off on the land during it’s curing. (2) If the amount of adhesive is insufficient for mounting, the Capacitor may fall after or during soldering. (3) If the adhesive is too low in its viscosity, the Capacitors may be out of alignment after or during soldering. (1) Adhesives for mounting can be cured by ultraviolet or infrared radiation. In order to prevent the terminal electrodes of the Capacitors from oxidizing, the curing shall be dune at conditions of 160℃ max., for 2 minutes max. (5) If curing is insufficient, the Capacitor may fall after or during soldering. Also insulation resistance between terminal electrodes may deteriorate due to moisture absorption. In order to prevent these problems, the curing conditions shall be sufficiently examined. 3- 3.Chip Mounting Consideration (1) When mounting the Capacitors/components on a PC board, the capacitor bodies shall be free from excessive impact loads such as mechanical impact or stress in the positioning, pushing force and displacement of vacuum nozzles at the time of mounting. (2) The maintenance and inspections for Chip Mounter must be performed regularly. (3) If the bottom dead center of the vacuum nozzle is too low, the Capacitor is cracked by an excessive force at the time of mounting. The following precautions and recommendations are for your reference in use. (a) Set and adjust the bottom dead center of the vacuum nozzles to the upper surface of the PC board after correcting the warp of the PC board. (b) Set the pushing force of the vacuum nozzle at the time of mounting to 1 to 3 N in static load. (c) For double surface mounting, apply a supporting pin on the rear surface of the PC board to suppress the bending of the PC board in order to minimize the impact of the vacuum nozzles. The typical examples are shown in the table below. (d) Adjust the vacuum nozzles so that their bottom dead center at the time of mounting is not too low. (4) The closing dimensions of positioning chucks shall be controlled and the maintenance, checks and replacement of positioning chucks shall be regularly performed to prevent chipping or cracking of the Capacitors caused by mechanical impact at the time of positioning due to worn positioning chucks. (5) Maximum stroke of the nozzle shall be adjusted so that the maximum bending of PC board does not exceed 0.5mm at 90mm span. The PC board shall be supported by means of adequate supporting pins. Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 6 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 NG Examples Improved Examples by pattern division Crack Single surface mounting The supporting pin must not Supporting be necessarily positioned pin beneath the capacitor. Double surface mounting Separation Crack Supporting of solder pin 3- 4.Selection of Soldering Flux Soldering flux may seriously affect the performance of the Capacitors. The following shall be confirmed before use. (1) Soldering flux having a halogen based content of 0.1 wt. % (converted to chlorine) or below shall be used. Do not use soldering flux with strong acid. (2) When applying water-soluble soldering flux, wash the Capacitors sufficiently because the soldering flux residue on the surface of PC boards may deteriorate the insulation resistance on the Capacitor surface due to insufficient cleaning. 3- 5.Soldering 3-5-1. Flow soldering In flow soldering process, abnormal and large thermal and mechanical stresses, caused by ”Temperature Gradient" between the mounted Capacitors and melted solder in a soldering bath, may be applied directly to the Capacitors, resulting in failures and damages of the Capacitors, So it is essential that soldering process shall be controlled to the following recommended conditions. (1) Application of Soldering flux: The soldering flux shall be applied to the mounted Capacitors thinly and uniformly by foaming method. (1) Preheating: The mounted Capacitors/Components shall be preheated sufficiently so that the “Temperature Gradient” between the Capacitors/Components and the melted solder shall be 150℃ max. (100 to130℃) (3) Immersion into Soldering Bath: The Capacitors shall be immersed into a soldering bath of 240 to 260℃ for 3 to 5 seconds. (4) Gradual Cooling: The Capacitors shall be cooled gradually to room ambient temperature with the cooling temperature rates of 8℃/s max. from 250℃ to 170℃ and 4℃/s max. from 170℃ to 130℃. (5) Flux Cleaning: When the Capacitors are immersed into a cleaning solvent, it shall be confirmed that the surface temperatures of devices do not exceed 100℃. (6) One time of flow soldering under the conditions shown in the figure below [Recommended profile of Flow soldering (Ex)] do not cause any problems. However, fully pay attention to the possible warp and bending of the PC board. Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 7 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 Recommended profile of Flow soldering [Ex.] 〈Allowable temperature difference ∆T〉 Soldering 240 Size Temp. Tol. Gradual cooling to 260℃ 0603 to 1206 ∆T ≦ 150 °C (at ordinary 0508, 0612 ∆T temperature） Temp. (℃) Time 60 to120s 3 to 5s 3-5-2. Reflow soldering In reflow soldering, the mounted Capacitors/Components are generally heated and soldered by a thermal conduction system such as an “Infrared radiation and hot blast soldering system” or a “Vapor Phase Soldering System (VPS)”. Large temperature gradients such as a rapid heating and cooling in the process may cause electrical failures and mechanical damages of the devices. It is essential that the soldering process shall be controlled by the following recommended conditions and precautions. (1) Preheating 1: The mounted Capacitors/Components shall be preheated sufficiently for 60 to 90 seconds so that the surface temperatures of them to be 140 to 160℃. (2) Preheating 2 : After “Preheating 1”, the mounted Capacitors/Components shall be heated to the elevated temperature of 150 to 220℃ for 2 to 5 seconds. (3) Soldering: Heating section:220℃ or above within 20 sec . (4) Gradual cooling: After the soldering, the mounted Capacitors/Components shall be gradually cooled to room ambient temperature for preventing mechanical damages such as cracking of the devices. (1) Flux Cleaning: When the Capacitors are immersed into a cleaning solvent, it shall be confirmed that the surface temperatures of devices do not exceed 100℃. (6) Two times of flow soldering under the conditions shown in the figure below [Recommended profile of Reflow soldering (Ex)] do not cause any problem. However, fully pay attention to the possible warp and bending of the PC board. Recommended profile of Reflow soldering (Ex.) 〈 Allowable temperature difference ∆T〉 240 ③Soldering Size Temp. Tol. to 260℃ 0201 to 1206 ∆T≦ 150 °C 220℃ 0508, 0612, 0504 ∆T 1210 to 1812 ∆T≦ 130 °C ④Gradual Temp. cooling (℃) ②Preheating 2 ①Preheating1 Time 60s min. 20s max. 120s max. Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 8 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 3-5-3. Hand soldering In hand soldering of the Capacitors, large temperature gradient between the preheated Capacitors and the tip of soldering iron may cause electrical failures and mechanical damages such as cracking or breaking of the devices. The soldering shall be carefully controlled and carried out so that the temperature gradient is kept minimum with the following recommended conditions for hand soldering. (1) Condition 1 (with preheating) (a) Soldering : 1.0mm Thread eutectic solder with soldering flux* in the core. φ *Rosin-based and non-activated flux is recommended. (b) Preheating: The Capacitors shall be preheated so that “Temperature Gradient” between the devices and the tip of soldering iron is 150℃ or below. (c) Temperature of Iron tip: 300℃ max. (The required amount of solder shall be melted in advance on the soldering tip.) (d) Gradual Cooling: After soldering, the Capacitors shall be cooled gradually at room ambient temperature. Recommended profile of Hand Soldering [Ex.] 〈Allowable temperature difference ∆T〉 Soldering Size Temp. Tol. 0201 to 1206 Gradual ∆T≦ 150 °C cooling 0508, 0612, 0504 ∆T 1210 to 1812 ∆T≦ 130 °C Preheating 60 to 120 s 3 s max. (2) Condition 2 (without preheating) Modification with a soldering iron is acceptable without preheating if within the conditions specified below. (a) Soldering iron tip shall never directly touch the ceramic dielectrics and terminal electrodes of the Capacitors. (b) The lands are sufficiently preheated with a soldering iron tip before sliding the soldering iron tip to the terminal electrode of the Capacitor for soldering. Conditions of Hand soldering without preheating Condition Chip size 0201 to 0805, 0508, 0504 1206 to 1812 , 0612 Temperature of soldering iron 270 °C Max. 250 °C Max. Wattage 20W Max. Shape of soldering iron tip φ3mm Max. Soldering time with soldering iron 3s Max. 3- 6.Post Soldering Cleaning 3-6-1. Residues of soldering fluxes on the PC board after cleaning with an inappropriate solvent may deteriorate on the electrical characteristics and reliability (particularly, insulation resistance) of the Capacitors. 3-6-2. Inappropriate cleaning conditions (Such as insufficient cleaning, excessive cleaning) may impair the electrical characteristics and reliability of the Capacitors. (1) If cleaning is insufficient : (a) The halogen substance in the residues of the soldering flux may cause the metal of terminal electrodes to corrode. (b) The halogen substance in the residues of the soldering flux on the surface of the Capacitors may deteriorate the insulation resistance. (c) Water-soluble soldering flux may have more remarkable tendencies of (a) and (b) above compared to those of rosin soldering flux. (2) If cleaning is excessive : Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 9 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 (a) Too much output of ultrasonic cleaning may deteriorate the strength of the terminal electrodes or cause cracking in the solder and/or ceramic bodies of the Capacitors due to vibrated PC boards. The following conditions are for Ultrasonic cleaning. Ultrasonic wave output: 20 W/L max. Ultrasonic wave frequency: 40 kHz max. Ultrasonic wave cleaning time: 5 min. max. 3-6-3. Cleaning with contaminated cleaning solvent may cause the same results in case of insufficient cleaning due to the high density of liberated halogen. 3- 7.Process Inspection When the mounted PC boards are inspected with measuring terminal pins, abnormal and excess mechanical stresses shall not be applied to the PC board and mounted components, to prevent failures or damages of the devices. (1) The mounted PC boards shall be supported by some adequate supporting pins setting their bending to 90 mm span 0.5mm max. (2) It shall be confirmed that measuring pins have a right tip shape, are equal in height and are set in the right positions. The following figures are for your reference to avoid the possible bending of PC board. NG Example Recommended Example Bending of PC board Check pin Check pin Supporting Separated pin 3- 8.Protective Coat When the surface of a PC board on which the Capacitors have been mounted is coated with resin to protect against moisture and dust, it shall be confirmed that the protective coat does not have influences on the reliability of the Capacitors in the actual equipment. (1) Coating materials, such as being corrosive and chemically active, shall not be applied to the Capacitors and other components. (2) Coating materials with large thermal expansivity shall not be applied to the Capacitors for preventing failures or damages (such as cracking) of the devices in the curing process. 3- 9.Dividing/Breaking of PC Boards Bending (1) Abnormal and excessive mechanical stresses such as bending or torsion as below, which cause cracking in the Capacitors, on the components on the PC board shall be kept minimum in the dividing/breaking. Torsion (2) Dividing/Breaking of the PC boards shall be done carefully at moderate speed by using a jig or apparatus to prevent the Capacitors on the boards from mechanical damages. (3) Examples of PCB dividing/breaking jig The outline of PC board breaking jig is shown below. As a recommended example, Dividing/Breaking of the PC boards shall be done by holding the position near the jig where is free from bending, and so as to be compressive stress for the components such as the Capacitors on the PC board. And as a NG example, if holding the PC board at any position apart from the jig, tensile stress to the Capacitor may cause cracking in the Capacitors. Outline of Jig Recommended Example NG Example V-groove Load direction PC board Load direction V-groove Load position PC board PC board Chip component Load position V-groove PC board splitting jig Note ; No. CLASSIFICATION SPECIFICATIONS 151S-ECJ-SS009E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 10 of 10 DATE Common Specification ( Precautions for Use) 1 Apr, 2005 3- 10.Mechanical Impact (1) The Capacitors shall be free from any excessive mechanical impact. The Capacitor body, which is made of ceramics, may be damaged or cracked by dropping impact. Crack Never use dropped capacitors because their quality may be already impaired and its failure level of significance may be increased. Particularly, Floor large size capacitors tend to be damaged or cracked more easily. (2) When handling the PC boards on which the Capacitors are mounted, the Capacitors shall not collide with another PC board. Crack When mounted PC boards are handled or stored in a stacked state, impact Mounted PCB caused by colliding between the corner of the PC board and the Capacitor may cause damage or cracking in the Capacitor and deteriorate the withstand voltage and insulation resistance of the Capacitor. 4. Other Various precautions described above are typical ones. For special mounting conditions, please contact us. Precautions for Use above are from The Technical Report EIAJ RCR-2335 Caution Guide Line for Operation of Fixed Multilayer Ceramic Capacitors for Electronic Equipment by Japan Electronics and Information Technology Industries Association (March 2002 issued) Please refer to above technical report for details. Note ; No. CLASSFICATION SPECIFICATIONS 151S-ECJ-SV037E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 1 of 4 DATE Taped and Reeled Packaging Specifications (Low Profile Type) 28 Apr, 2004 1. Scope This specification applies to taped and reeled packing for Multilayer Ceramic Chip Capacitors (Low Profile Type). 2. Applicable Standards EIAJ (Electric Industries Association of Japan) Standard EIAJ RC-1009B JIS (Japanese Industrial Standard) Standard JIS C 0806 3. Packing Specification 3- 1.Structure and Dimensions Paper taping packaging is carried out according the following diagram (1)Carrier tape : Shown in Fig. 4. (2)Reel : Shown in Fig. 5. (3)Packaging : We shall pack suitably in order prevent damage during transportation or storage. 3- 2.Packing Quantity Carrier-Tape Quantity (pcs./reel) Type Thickness of φ180mm Reel (EIA) Capacitor(mm) Material Taping Pitch Packaging Quantity Code 12type (0805) 0.85+/-0.10 Paper Taping 4mm V 4000 0.85+/-0.10 Paper Taping 4mm V 4000 13type (1206) 1.15+/-0.10 Embossed Taping 4mm F 3000 23type (1210) 0.85+/-0.10 Embossed Taping 4mm F 3000 ※ Explanation of Part Numbers (Example) ECJ G V B 1C 105 K Packaging Code 3- 3.Marking on the Reel The following items are described in the side of a reel in English at least. (1)Part Number (2)Quantity (3)Lot Number (4)Place of origin 3- 4.Structure of Taping (1) The direction of winding of taping on the reel shall be in accordance with the following diagram. Fig. 1 Paper Taping Note ; 01 Apr, 2005 Change the company name. Previous : Matsushita Electronic Components Co., Ltd. New : Panasonic Electronic Devices Co., Ltd. APPROVAL CHECK DESIGN Panasonic Electronic Devices Co., Ltd. Y.Sakaguchi S.Endoh T.Shinriki No. CLASSFICATION SPECIFICATIONS 151S-ECJ-SV037E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 2 of 4 DATE Taped and Reeled Packaging Specifications (Low Profile Type) 28 Apr, 2004 Fig. 2 Embossed Taping (2) The specification of the leader and empty portion shall be in accordance with the following diagram. Fig. 2 Leader Part and Taped End 100mm min. 160mm min. 400mm min. 4. Efficiency 4- 1.Breakage strength of the tape : 10N or more. 4- 2.Peel strength of the cover tape (refer to the following figure). (1)Peel angle : 165 to 180 degree from the tape adhesive face. (2)Peel velocity : 300mm per min. (3)Peel strength : 0.1 to 0.7N Fig. 3 Peel strength of the cover tape (a)Paper Taping Note ; No. CLASSFICATION SPECIFICATIONS 151S-ECJ-SV037E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 3 of 4 DATE Taped and Reeled Packaging Specifications (Low Profile Type) 28 Apr, 2004 （ｂ）Embossed Taping 4.3 Barrs on tape There shall be no barrs preventing suction when products are taken out. 4.4 Missing of products The missing of products shall be 0.1% or less per reel and there shall be no continuous missing of products. 4.5 Adherence to the tape Products shall not be stuck to the cover tape or bottom tape. Fig. 5 Carrier Tape Dimension (a)12 and 13 type : 4mm taping pitch for Paper taping. Code Dimension W 8.0 +/- 0.2 F 3.50 +/- 0.05 E 1.75 +/- 0.10 P 4.0 +/- 0.1 1 P 2.00 +/- 0.05 2 P 4.0 +/- 0.1 0 D φ1.5 0 +0.1/-0 t 1.1 max. 1 t 1.4 max. 2 Unit : mm Type(EIA) 12type 13type Code (0805) (1206) A 1.65 +/- 0.20 2.0 +/- 0.2 B 2.4 +/- 0.2 3.6 +/- 0.2 Note ; No. CLASSFICATION SPECIFICATIONS 151S-ECJ-SV037E SUBJECT PAGE Multilayer Ceramic Chip Capacitor 4 of 4 DATE Taped and Reeled Packaging Specifications (Low Profile Type) 28 Apr, 2004 (b) 13 and 23 type: 4mm chip taping pitch for Embossed taping. Code Dimension Ｗ 8.0 +/- 0.2 Ｆ 3.50 +/- 0.05 Ｅ 1.75 +/- 0.10 Ｐ 4.0 +/- 0.1 １ Ｐ 2.00 +/- 0.05 ２ Ｐ 4.0 +/- 0.1 ０ Ｄ φ1.5 ０ 　　+0.1/-0 Ｄ φ1.1+/- 0.1 １ ｔ 0.6 max. １ 13 1.8max. type Type(EIA) 13type 23type ｔ ２ Code (1206) (1210) 23 1.5 max. type A 1.9 +/- 0.2 2.8 +/- 0.2 Unit : mm B 3.5 +/- 0.2 3.5 +/- 0.2 Fig. 5 Reel Dimension (a)φ180mm Reel (Standard Reel) Code Dimension A φ180+0/-3 B φ60 +1/- 0 C 13.0 +/- 0.2 D 21.0 +/- 0.8 E 2.0 +/- 0.5 W 9.0 +/- 0.3 W 11.4 +/- 1.0 1 Unit : mm Note ;