INTEL TR80C186XL20

80C186XL/80C188XL 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS Y Y Low Power, Fully Static Versions of Completely Object Code Compatible 80C186/80C188 with Existing 8086/8088 Software and Has 10 Additional Instructions over Y Operation Modes: 8086/8088 Ð Enhanced Mode Y Ð DRAM Refresh Control Unit Speed Versions Available Ð Power-Save Mode Ð 25 MHz (80C186XL25/80C188XL25) Ð Direct Interface to 80C187 Ð 20 MHz (80C186XL20/80C188XL20) (80C186XL Only) Ð 12 MHz (80C186XL12/80C188XL12) Ð Compatible Mode Y Direct Addressing Capability to Ð NMOS 80186/80188 Pin-for-Pin 1 MByte Memory and 64 Kbyte I/O Replacement for Non-Numerics Y Available in 68-Pin: Applications Ð Plastic Leaded Chip Carrier (PLCC) Y Integrated Feature Set Ð Ceramic Pin Grid Array (PGA) Ð Static, Modular CPU Ð Ceramic Leadless Chip Carrier Ð Clock Generator (JEDEC A Package) Ð 2 Independent DMA Channels Y Available in 80-Pin: Ð Programmable Interrupt Controller Ð Quad Flat Pack (EIAJ) Ð 3 Programmable 16-Bit Timers Ð Shrink Quad Flat Pack (SGFP) Ð Dynamic RAM Refresh Control Unit Ð Programmable Memory and Y Available in Extended Temperature Peripheral Chip Select Logic b a Range ( 40 Cto 85 C) § § Ð Programmable Wait State Generator Ð Local Bus Controller Ð Power-Save Mode Ð System-Level Testing Support (High Impedance Test Mode) The Intel 80C186XL is a Modular Core re-implementation of the 80C186 microprocessor. It offers higher speed and lower power consumption than the standard 80C186 but maintains 100% clock-for-clock functional com- patibility. Packaging and pinout are also identical. 272431-1 *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. June, 2002 Order Number: 272431-005 COPYRIGHT© INTEL CORPORATION, 2002 80C186XL/80C188XL 16-Bit High-Integration Embedded Processors CONTENTS PAGE CONTENTS PAGE INTRODUCTION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 AC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 24 Major Cycle Timings (Read Cycle) ÀÀÀÀÀÀÀÀÀ 24 80C186XL CORE ARCHITECTURE ÀÀÀÀÀÀÀÀ 4 Major Cycle Timings (Write Cycle) ÀÀÀÀÀÀÀÀÀ 26 80C186XL Clock Generator ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 4 Major Cycle Timings (Interrupt Bus Interface Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Acknowledge Cycle) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 27 Software Halt Cycle Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 28 80C186XL PERIPHERAL ARCHITECTURE ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 5 Clock Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 29 Chip-Select/Ready Generation Logic ÀÀÀÀÀÀÀ 5 Ready, Peripheral and Queue Status Timings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 30 DMA Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Reset and Hold/HLDA Timings ÀÀÀÀÀÀÀÀÀÀÀÀ 31 Timer/Counter Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 Interrupt Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 AC TIMING WAVEFORMS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 36 Enhanced Mode Operation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 AC CHARACTERISTICS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 37 Queue-Status Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 6 DRAM Refresh Control Unit ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 EXPLANATION OF THE AC SYMBOLS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 39 Power-Save Control ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 Interface for 80C187 Math Coprocessor DERATING CURVES ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 40 (80C186XL Only) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 80C186XL/80C188XL EXPRESS ÀÀÀÀÀÀÀÀÀ 41 ONCE Test Mode ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 7 80C186XL/80C188XL EXECUTION PACKAGE INFORMATION ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 TIMINGS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 41 Pin Descriptions ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 8 INSTRUCTION SET SUMMARY ÀÀÀÀÀÀÀÀÀÀ 42 80C186XL/80C188XL Pinout Diagrams ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 16 REVISION HISTORY ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 ELECTRICAL SPECIFICATIONS ÀÀÀÀÀÀÀÀÀ 22 ERRATA ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 Absolute Maximum Ratings ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 PRODUCT IDENTIFICATION ÀÀÀÀÀÀÀÀÀÀÀÀÀ 48 DC SPECIFICATIONS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 22 Power Supply Current ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ 23 2 80C186XL/80C188XL NOTE: Pin names in parentheses applies to 80C188XL. Figure 1. 80C186XL/80C188XL Block Diagram 3 272431±2 80C186XL/80C188XL (2a) 272431±3 272431±4 (2b) Note 1: XTAL Frequency L1 Value g 20 MHz 12.0 mH 20% g 25 MHz 8.2 mH 20% g 32 MHz 4.7 mH 20% 40 MHz 3.0 mH g20% LC network is only required when using a third overtone crystal. Figure 2. Oscillator Configurations (see text) The 80C186XL oscillator circuit is designed to be INTRODUCTION used either with a parallel resonant fundamental or third-overtone mode crystal, depending upon the Unless specifically noted, all references to the frequency range of the application. This is used as 80C186XL apply to the 80C188XL. References to the time base for the 80C186XL. pins that differ between the 80C186XL and the 80C188XL are given in parentheses. The output of the oscillator is not directly available outside the 80C186XL. The recommended crystal The following Functional Description describes the configuration is shown in Figure 2b. When used in base architecture of the 80C186XL. The 80C186XL third-overtone mode, the tank circuit is recommend- is a very high integration 16-bit microprocessor. It ed for stable operation. Alternately, the oscillator combines 15±20 of the most common microproces- may be driven from an external source as shown in sor system components onto one chip. The Figure 2a. 80C186XL is object code compatible with the 8086/8088 microprocessors and adds 10 new in- The crystal or clock frequency chosen must be twice struction types to the 8086/8088 instruction set. the required processor operating frequency due to the internal divide by two counter. This counter is The 80C186XL has two major modes of operation, used to drive all internal phase clocks and the exter- Compatible and Enhanced. In Compatible Mode the 80C186XL is completely compatible with NMOS nal CLKOUT signal. CLKOUT is a 50% duty cycle processor clock and can be used to drive other sys- 80186, with the exception of 8087 support. The En- tem components. All AC Timings are referenced to hanced mode adds three new features to the system CLKOUT. design. These are Power-Save control, Dynamic RAM refresh, and an asynchronous Numerics Co- Intel recommends the following values for crystal se- processor interface (80C186XL only). lection parameters. Temperature Range: Application Specific 80C186XL CORE ARCHITECTURE ESR (Equivalent Series Resistance): 60X max C (Shunt Capacitance of Crystal): 7.0 pF max 0 80C186XL Clock Generator C (Load Capacitance): 20 pF g2pF 1 The 80C186XL provides an on-chip clock generator Drive Level: 2 mW max for both internal and external clock generation. The clock generator features a crystal oscillator, a divide- by-two counter, synchronous and asynchronous ready inputs, and reset circuitry. 4 80C186XL/80C188XL spond to bus cycles. An offset map of the 256-byte Bus Interface Unit control register block is shown in Figure 3. The 80C186XL provides a local bus controller to generate the local bus control signals. In addition, it employs a HOLD/HLDA protocol for relinquishing Chip-Select/Ready Generation Logic the local bus to other bus masters. It also provides The 80C186XL contains logic which provides outputs that can be used to enable external buffers programmable chip-select generation for both mem- and to direct the flow of data on and off the local ories and peripherals. In addition, it can be bus. programmed to provide READY (or WAIT state) gen- eration. It can also provide latched address bits A1 The bus controller is responsible for generating 20 and A2. The chip-select lines are active for all mem- bits of address, read and write strobes, bus cycle ory and I/O cycles in their programmed areas, status information and data (for write operations) in- whether they be generated by the CPU or by the formation. It is also responsible for reading data integrated DMA unit. from the local bus during a read operation. Synchro- nous and asynchronous ready input pins are provid- The 80C186XL provides 6 memory chip select out- ed to extend a bus cycle beyond the minimum four puts for 3 address areas; upper memory, lower states (clocks). memory, and midrange memory. One each is provid- ed for upper memory and lower memory, while four The 80C186XL bus controller also generates two are provided for midrange memory. control signals (DEN and DT/R) when interfacing to external transceiver chips. This capability allows the OFFSET addition of transceivers for simple buffering of the multiplexed address/data bus. Relocation Register FEH During RESET the local bus controller will perform the following action: DAH DMA Descriptors Channel 1 # Drive DEN,RD and WR HIGH for one clock cy- D0H cle, then float them. # Drive S0±S2 to the inactive state (all HIGH) and CAH then float. DMA Descriptors Channel 0 # Drive LOCK HIGH and then float. C0H # Float AD0±15 (AD0±8), A16±19 (A9±A19), BHE (RFSH), DT/R. A8H Chip-Select Control Registers # Drive ALE LOW A0H # Drive HLDA LOW. 66H RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ Time 2 Control Registers ERROR and TEST/BUSY pins have internal pullup 60H devices which are active while RES is applied. Ex- 5EH Time 1 Control Registers cessive loading or grounding certain of these pins 58H causes the 80C186XL to enter an alternative mode 56H of operation: Time 0 Control Registers 50H # RD/QSMD low results in Queue Status Mode. # UCS and LCS low results in ONCE Mode. 3EH TEST/BUSY low (and high later) results in En- # Interrupt Controller Registers hanced Mode. 20H Figure 3. Internal Register Map 80C186XL PERIPHERAL ARCHITECTURE The 80C186XL provides a chip select, called UCS, for the top of memory. The top of memory is usually All the 80C186XL integrated peripherals are con- used as the system memory because after reset the trolled by 16-bit registers contained within an inter- 80C186XL begins executing at memory location nal 256-byte control block. The control block may be FFFF0H. mapped into either memory or I/O space. Internal logic will recognize control block addresses and re- 5 80C186XL/80C188XL The 80C186XL provides a chip select for low memo- mum of 8 clocks), one cycle to fetch data and the ry called LCS. The bottom of memory contains the other to store data. interrupt vector table, starting at location 00000H. The 80C186XL provides four MCS lines which are Timer/Counter Unit active within a user-locatable memory block. This The 80C186XL provides three internal 16-bit pro- block can be located within the 80C186XL 1 Mbyte grammable timers. Two of these are highly flexible memory address space exclusive of the areas de- and are connected to four external pins (2 per timer). fined by UCS and LCS. Both the base address and They can be used to count external events, time ex- size of this memory block are programmable. ternal events, generate nonrepetitive waveforms, etc. The third timer is not connected to any external The 80C186XL can generate chip selects for up to pins, and is useful for real-time coding and time de- seven peripheral devices. These chip selects are ac- lay applications. In addition, the third timer can be tive for seven contiguous blocks of 128 bytes above used as a prescaler to the other two, or as a DMA a programmable base address. The base address request source. may be located in either memory or I/O space. The 80C186XL can generate a READY signal inter- Interrupt Control Unit nally for each of the memory or peripheral CS lines. The number of WAIT states to be inserted for each The 80C186XL can receive interrupts from a number peripheral or memory is programmable to provide of sources, both internal and external. The 0±3 wait states for all accesses to the area for 80C186XL has 5 external and 2 internal interrupt which the chip select is active. In addition, the sources (Timer/Couners and DMA). The internal in- 80C186XL may be programmed to either ignore ex- terrupt controller serves to merge these requests on ternal READY for each chip-select range individually a priority basis, for individual service by the CPU. or to factor external READY with the integrated ready generator. Enhanced Mode Operation Upon RESET, the Chip-Select/Ready Logic will per- form the following actions: In Compatible Mode the 80C186XL operates with all # All chip-select outputs will be driven HIGH. the features of the NMOS 80186, with the exception of 8087 support (i.e. no math coprocessing is possi- # Upon leaving RESET, the UCS line will be pro- ble in Compatible Mode). Queue-Status information grammed to provide chip selects to a 1K block is still available for design purposes other than 8087 with the accompanying READY control bits set at support. 011 to insert 3 wait states in conjunction with ex- ternal READY (i.e., UMCS resets to FFFBH). All the Enhanced Mode features are completely # No other chip select or READY control registers masked when in Compatible Mode. A write to any of have any predefined values after RESET. They the Enhanced Mode registers will have no effect, will not become active until the CPU accesses while a read will not return any valid data. their control registers. In Enhanced Mode, the 80C186XL will operate with Power-Save, DRAM refresh, and numerics coproc- DMA Unit essor support (80C186XL only) in addition to all the Compatible Mode features. The 80C186XL DMA controller provides two inde- pendent high-speed DMA channels. Data transfers If connected to a math coprocessor (80C186XL can occur between memory and I/O spaces (e.g., only), this mode will be invoked automatically. With- Memory to I/O) or within the same space (e.g., out an NPX, this mode can be entered by tying the Memory to Memory or I/O to I/O). Data can be RESET output signal from the 80C186XL to the transferred either in bytes (8 bits) or in words (16 TEST/BUSY input. bits) to or from even or odd addresses. NOTE: Queue-Status Mode Only byte transfers are possible on the 80C188XL. The queue-status mode is entered by strapping the RD pin low. RD is sampled at RESET and if LOW, Each DMA channel maintains both a 20-bit source the 80C186XL will reconfigure the ALE and WR pins and destination pointer which can be optionally in- to be QS0 and QS1 respectively. This mode is avail- cremented or decremented after each data transfer able on the 80C186XL in both Compatible and En- (by one or two depending on byte or word transfers). hanced Modes. Each data transfer consumes 2 bus cycles (a mini- 6 80C186XL/80C188XL functions as in compatible mode, and may be pro- DRAM Refresh Control Unit grammed for activity with ready logic and wait states accordingly. As in Compatible Mode, MCS2 will func- The Refresh Control Unit (RCU) automatically gen- tion for one-fourth a programmed block size. erates DRAM refresh bus cycles. The RCU operates only in Enhanced Mode. After a programmable peri- Table 1. MCS Assignments od of time, the RCU generates a memory read re- quest to the BIU. If the address generated during a Compatible refresh bus cycle is within the range of a properly Enhanced Mode Mode programmed chip select, that chip select will be acti- vated when the BIU executes the refresh bus cycle. MCS0 PEREQ Processor Extension Request MCS1 ERROR NPX Error MCS2 MCS2 Mid-Range Chip Select Power-Save Control MCS3 NPS Numeric Processor Select The 80C186XL, when in Enhanced Mode, can enter a power saving state by internally dividing the proc- ONCE Test Mode essor clock frequency by a programmable factor. This divided frequency is also available at the To facilitate testing and inspection of devices when CLKOUT pin. fixed into a target system, the 80C186XL has a test mode available which allows all pins to be placed in All internal logic, including the Refresh Control Unit a high-impedance state. ONCE stands for ``ON Cir- and the timers, have their clocks slowed down by cuit Emulation''. When placed in this mode, the the division factor. To maintain a real time count or a 80C186XL will put all pins in the high-impedance fixed DRAM refresh rate, these peripherals must be state until RESET. re-programmed when entering and leaving the pow- er-save mode. The ONCE mode is selected by tying the UCS and the LCS LOW during RESET. These pins are sam- pled on the low-to-high transition of the RES pin. Interface for 80C187 Math The UCS and the LCS pins have weak internal pull- Coprocessor (80C186XL Only) up resistors similar to the RD and TEST/BUSY pins to guarantee ONCE Mode is not entered inadver- In Enhanced Mode, three of the mid-range memory tently during normal operation. LCS and UCS must chip selects are redefined according to Table 1 for be held low at least one clock after RES goes high use with the 80C187. The fourth chip select, MCS2 to guarantee entrance into ONCE Mode. 7 80C186XL/80C188XL proper operation. Stated simply, missing PACKAGE INFORMATION a setup or hold on an asynchronous pin will result in something minor (i.e., a tim- This section describes the pin functions, pinout and er count will be missed) whereas miss- thermal characteristics for the 80C186XL in the ing a setup or hold on a synchronous pin Quad Flat Pack (QFP), Plastic Leaded Chip Carrier result in system failure (the system will (PLCC), Leadless Chip Carrier (LCC) and the Shrink ``lock up''). Quad Flat Pack (SQFP). For complete package specifications and information, see the Intel Packag- An input pin may also be edge or level ing Outlines and Dimensions Guide (Order Number: sensitive. 231369). Column 4: Output States (for O and I/O types only) The state of an output or I/O pin is de- Pin Descriptions pendent on the operating mode of the Each pin or logical set of pins is described in Table device. There are four modes of opera- 3. There are four columns for each entry in the Pin tion that are different from normal active Description Table. The following sections describe mode: Bus Hold, Reset, Idle Mode, Pow- each column. erdown Mode. This column describes the output pin state in each of these Column 1: Pin Name modes. In this column is a mnemonic that de- scribes the pin function. Negation of the The legend for interpreting the information in the Pin signal name (i.e., RESIN) implies that Descriptions is shown in Table 2. the signal is active low. Column 2: Pin Type As an example, please refer to the table entry for AD7:0. The ``I/O'' signifies that the pins are bidirec- A pin may be either power (P), ground tional (i.e., have both an input and output function). (G), input only (I), output only (O) or in- The ``S'' indicates that, as an input the signal must put/output (I/O). Please note that some be synchronized to CLKOUT for proper operation. pins have more than one function. The ``H(Z)'' indicates that these pins will float while Column 3: Input Type (for I and I/O types only) the processor is in the Hold Acknowledge state. These are two different types of input R(Z) indicates that these pins will float while RESIN pins on the 80C186XL: asynchronous is low. and synchronous. Asynchronous pins require that setup and hold times be met All pins float while the processor is in the ONCE only toguarantee recognition. Synchro- Mode (with the exception of X2). nous input pins require that the setup and hold times be met to guarantee 8 80C186XL/80C188XL Table 2. Pin Description Nomenclature Symbol Description a P Power Pin (apply V voltage) CC G Ground (connect to V ) SS I Input only pin O Output only pin I/O Input/Output pin S(E) Synchronous, edge sensitive S(L) Synchronous, level sensitive A(E) Asynchronous, edge sensitive A(L) Asynchronous, level sensitive H(1) Output driven to V during bus hold CC H(0) Output driven to V during bus hold SS H(Z) Output floats during bus hold H(Q) Output remains active during bus hold H(X) Output retains current state during bus hold R(WH) Output weakly held at V during reset CC R(1) Output driven to V during reset CC R(0) Output driven to V during reset SS R(Z) Output floats during reset R(Q) Output remains active during reset R(X) Output retains current state during reset 9 80C186XL/80C188XL Table 3. Pin Descriptions Pin Pin Input Output Pin Description Name Type Type States a V P System Power: 5 volt power supply. CC V G System Ground. SS RESET O H(0) RESET Output indicates that the CPU is being reset, and can be used as a system reset. It is active HIGH, synchronized R(1) with the processor clock, and lasts an integer number of clock periods corresponding to the length of the RES signal. Reset goes inactive 2 clockout periods after RES goes inactive. When tied to the TEST/BUSY pin, RESET forces the processor into enhanced mode. RESET is not floated during bus hold. X1 I A(E) Crystal Inputs X1 and X2 provide external connections for a fundamental mode or third overtone parallel resonant crystal X2 O H(Q) for the internal oscillator. X1 can connect to an external R(Q) clock instead of a crystal. In this case, minimize the capacitance on X2. The input or oscillator frequency is internally divided by two to generate the clock signal (CLKOUT). CLKOUT O H(Q) Clock Output provides the system with a 50% duty cycle waveform. All device pin timings are specified relative to R(Q) CLKOUT. CLKOUT is active during reset and bus hold. RES I A(L) An active RES causes the processor to immediately terminate its present activity, clear the internal logic, and enter a dormant state. This signal may be asynchronous to the clock. The processor begins fetching instructions approximately 6(/2 clock cycles after RES is returned HIGH. For proper initialization, V must be within specifications CC and the clock signal must be stable for more than 4 clocks with RES held LOW. RES is internally synchronized. This input is provided with a Schmitt-trigger to facilitate power-on RES generation via an RC network. TEST/BUSY I A(E) The TEST pin is sampled during and after reset to determine whether the processor is to enter Compatible or Enhanced (TEST) Mode. Enhanced Mode requires TEST to be HIGH on the rising edge of RES and LOW four CLKOUT cycles later. Any other combination will place the processor in Compatible Mode. During power-up, active RES is required to configure TEST/BUSY as an input. A weak internal pullup ensures a HIGH state when the input is not externally driven. TESTÐIn Compatible Mode this pin is configured to operate as TEST. This pin is examined by the WAIT instruction. If the TEST input is HIGH when WAIT execution begins, instruction execution will suspend. TEST will be resampled every five clocks until it goes LOW, at which time execution will resume. If interrupts are enabled while the processor is waiting for TEST, interrupts will be serviced. BUSY (80C186XL Only)ÐIn Enhanced Mode, this pin is configured to operate as BUSY. The BUSY input is used to notify the 80C186XL of Math Coprocessor activity. Floating point instructions executing in the 80C186XL sample the BUSY pin to determine when the Math Coprocessor is ready to accept a new command. BUSY is active HIGH. NOTE: Pin names in parentheses apply to the 80C188XL. 10 80C186XL/80C188XL Table 3. Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States TMR IN 0 I A(L) Timer Inputs are used either as clock or control signals, depending upon the programmed timer mode. These TMR IN 1 A(E) inputs are active HIGH (or LOW-to-HIGH transitions are counted) and internally synchronized. Timer Inputs must be tied HIGH when not being used as clock or retrigger inputs. TMR OUT 0 O H(Q) Timer outputs are used to provide single pulse or continuous waveform generation, depending upon the TMR OUT 1 R(1) timer mode selected. These outputs are not floated during a bus hold. DRQ0 I A(L) DMA Request is asserted HIGH by an external device when it is ready for DMA Channel 0 or 1 to perform a DRQ1 transfer. These signals are level-triggered and internally synchronized. NMI I A(E) The Non-Maskable Interrupt input causes a Type 2 interrupt. An NMI transition from LOW to HIGH is latched and synchronized internally, and initiates the interrupt at the next instruction boundary. NMI must be asserted for at least one CLKOUT period. The Non- Maskable Interrupt cannot be avoided by programming. INT0 I A(E) Maskable Interrupt Requests can be requested by activating one of these pins. When configured as inputs, INT1/SELECT A(L) these pins are active HIGH. Interrupt Requests are INT2/INTA0 I/O A(E) H(1) synchronized internally. INT2 and INT3 may be INT3/INTA1/IRQ A(L) R(Z) configured to provide active-LOW interrupt- acknowledge output signals. All interrupt inputs may be configured to be either edge- or level-triggered. To ensure recognition, all interrupt requests must remain active until the interrupt is acknowledged. When Slave Mode is selected, the function of these pins changes (see Interrupt Controller section of this data sheet). A19/S6 O H(Z) Address Bus Outputs and Bus Cycle Status (3±6) indicate the four most significant address bits during T . A18/S5 R(Z) 1 These signals are active HIGH. A17/S4 A16/S3 During T ,T ,T and T , the S6 pin is LOW to indicate 2 3 W 4 a CPU-initiated bus cycle or HIGH to indicate a DMA- (A8±A15) initiated or refresh bus cycle. During the same T-states, S3, S4 and S5 are always LOW. On the 80C188XL, A15±A8 provide valid address information for the entire bus cycle. AD0±AD15 I/O S(L) H(Z) Address/Data Bus signals constitute the time multiplexed memory or I/O address (T ) and data (T , (AD0±AD7) R(Z) 1 2 T ,T and T ) bus. The bus is active HIGH. For the 3 W 4 80C186XL, A is analogous to BHE for the lower byte of 0 the data bus, pins D through D . It is LOW during T 7 0 1 when a byte is to be transferred onto the lower portion of the bus in memory or I/O operations. NOTE: Pin names in parentheses apply to the 80C188XL. 11 80C186XL/80C188XL Table 3. Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States BHE O H(Z) The BHE (Bus High Enable) signal is analogous to A0 in that it is used to enable data on to the most significant half of the data bus, (RFSH) R(Z) pins D15±D8. BHE will be LOW during T when the upper byte is 1 transferred and will remain LOW through T and T . BHE does not 3 W need to be latched. On the 80C188XL, RFSH is asserted LOW to indicate a refresh bus cycle. In Enhanced Mode, BHE (RFSH) will also be used to signify DRAM refresh cycles. A refresh cycle is indicated by both BHE (RFSH) and A0 being HIGH. 80C186XL BHE and A0 Encodings BHE A0 Function Value Value 0 0 Word Transfer 0 1 Byte Transfer on upper half of data bus (D15±D8) 1 0 Byte Transfer on lower half of data bus (D ±D ) 7 0 1 1 Refresh ALE/QS0 O H(0) Address Latch Enable/Queue Status 0 is provided by the processor to latch the address. ALE is active HIGH, with addresses guaranteed R(0) valid on the trailing edge. WR/QS1 O H(Z) Write Strobe/Queue Status 1 indicates that the data on the bus is to be written into a memory or an I/O device. It is active LOW. When R(Z) the processor is in Queue Status Mode, the ALE/QS0 and WR/QS1 pins provide information about processor/instruction queue interaction. QS1 QS0 Queue Operation 0 0 No queue operation 0 1 First opcode byte fetched from the queue 1 1 Subsequent byte fetched from the queue 1 0 Empty the queue RD/QSMD O H(Z) Read Strobe is an active LOW signal which indicates that the processor is performing a memory or I/O read cycle. It is guaranteed R(1) not to go LOW before the A/D bus is floated. An internal pull-up ensures that RD/QSMD is HIGH during RESET. Following RESET the pin is sampled to determine whether the processor is to provide ALE, RD, and WR, or queue status information. To enable Queue Status Mode, RD must be connected to GND. ARDY I A(L) Asynchronous Ready informs the processor that the addressed memory space or I/O device will complete a data transfer. The S(L) ARDY pin accepts a rising edge that is asynchronous to CLKOUT and is active HIGH. The falling edge of ARDY must be synchronized to the processor clock. Connecting ARDY HIGH will always assert the ready condition to the CPU. If this line is unused, it should be tied LOW to yield control to the SRDY pin. NOTE: Pin names in parentheses apply to the 80C188XL. 12 80C186XL/80C188XL Table 3. Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States SRDY I S(L) Ð Synchronous Ready informs the processor that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active-HIGH input synchronized to CLKOUT. The use of SRDY allows a relaxed system timing over ARDY. This is accomplished by elimination of the one-half clock cycle required to internally synchonize the ARDY input signal. Connecting SRDY high will always assert the ready condition to the CPU. If this line is unused, it should be tied LOW to yield control to the ARDY pin. LOCK O Ð H(Z) LOCK output indicates that other system bus masters are not to gain control of the system bus. LOCK is active LOW. The LOCK R(Z) signal is requested by the LOCK prefix instruction and is activated at the beginning of the first data cycle associated with the instruction immediately following the LOCK prefix. It remains active until the completion of that instruction. No instruction prefetching will occur while LOCK is asserted. S0 O Ð H(Z) Bus cycle status S0±S2 are encoded to provide bus-transaction information: S1 R(1) S2 Bus Cycle Status Information S2 S1 S0 Bus Cycle Initiated 0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 0 1 0 Write I/O 0 1 1 Halt 1 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 1 1 1 Passive (no bus cycle) S2 may be used as a logical M/IO indicator, and S1 as a DT/R indicator. HOLD I A(L) Ð HOLD indicates that another bus master is requesting the local bus. The HOLD input is active HIGH. The processor generates HLDA HLDA O Ð H(1) (HIGH) in response to a HOLD request. Simultaneous with the R(0) issuance of HLDA, the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor will lower HLDA. When the processor needs to run another bus cycle, it will again drive the local bus and control lines. In Enhanced Mode, HLDA will go low when a DRAM refresh cycle is pending in the processor and an external bus master has control of the bus. It will be up to the external master to relinquish the bus by lowering HOLD so that the processor may execute the refresh cycle. NOTE: Pin names in parentheses apply to the 80C188XL. 13 80C186XL/80C188XL Table 3. Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States UCS I/O A(L) H(1) Upper Memory Chip Select is an active LOW output whenever a memory reference is made to the defined R(WH) upper portion (1K±256K block) of memory. The address range activating UCS is software programmable. UCS and LCS are sampled upon the rising edge of RES. If both pins are held low, the processor will enter ONCE Mode. In ONCE Mode all pins assume a high impedance state and remain so until a subsequent RESET. UCS has a weak internal pullup that is active during RESET to ensure that the processor does not enter ONCE Mode inadvertently. LCS I/O A(L) H(1) Lower Memory Chip Select is active LOW whenever a memory reference is made to the defined lower portion R(WH) (1K±256K) of memory. The address range activating LCS is software programmable. UCS and LCS are sampled upon the rising edge of RES. If both pins are held low, the processor will enter ONCE Mode. In ONCE Mode all pins assume a high impedance state and remain so until a subsequent RESET. LCS has a weak internal pullup that is active only during RESET to ensure that the processor does not enter ONCE mode inadvertently. MCS0/PEREQ I/O A(L) H(1) Mid-Range Memory Chip Select signals are active LOW when a memory reference is made to the defined mid- MCS1/ERROR R(WH) range portion of memory (8K±512K). The address MCS2 O H(1) ranges activating MCS0±3 are software programmable. MCS3/NPS R(1) On the 80C186XL, in Enhanced Mode, MCS0 becomes a PEREQ input (Processor Extension Request). When connected to the Math Coprocessor, this input is used to signal the 80C186XL when to make numeric data transfers to and from the coprocessor. MCS3 becomes NPS (Numeric Processor Select) which may only be activated by communication to the 80C187. MCS1 becomes ERROR in Enhanced Mode and is used to signal numerics coprocessor errors. PCS0 O H(1) Peripheral Chip Select signals 0±4 are active LOW when a reference is made to the defined peripheral PCS1 R(1) area (64 Kbyte I/O or 1 MByte memory space). The PCS2 address ranges activating PCS0±4 are software PCS3 programmable. PCS4 PCS5/A1 O H(1)/H(X) Peripheral Chip Select 5 or Latched A1 may be programmed to provide a sixth peripheral chip select, or R(1) to provide an internally latched A1 signal. The address range activating PCS5 is software-programmable. PCS5/A1 does not float during bus HOLD. When programmed to provide latched A1, this pin will retain the previously latched value during HOLD. NOTE: Pin names in parentheses apply to the 80C188XL. 14 80C186XL/80C188XL Table 3. Pin Descriptions (Continued) Pin Pin Input Output Pin Description Name Type Type States PCS6/A2 O Ð H(1)/H(X) Peripheral Chip Select 6 or Latched A2 may be programmed to provide a seventh peripheral chip select, or to provide an R(1) internally latched A2 signal. The address range activating PCS6 is software-programmable. PCS6/A2 does not float during bus HOLD. When programmed to provide latched A2, this pin will retain the previously latched value during HOLD. DT/R O Ð H(Z) Data Transmit/Receive controls the direction of data flow through an external data bus transceiver. When LOW, data is R(Z) transferred to the procesor. When HIGH the processor places write data on the data bus. DEN O Ð H(Z) Data Enable is provided as a data bus transceiver output enable. DEN is active LOW during each memory and I/O R(1,Z) access (including 80C187 access). DEN is HIGH whenever DT/R changes state. During RESET, DEN is driven HIGH for one clock, then floated. N.C. Ð Ð Ð Not connected. To maintain compatibility with future products, do not connect to these pins. NOTE: Pin names in parentheses apply to the 80C188XL. 15 80C186XL/80C188XL Ceramic Leadless Chip Carrier (JEDEC Type A) Contacts Facing Up Contacts Facing Down 272431±5 Ceramic Pin Grid Array Pins Facing Up Pins Facing Down 272431±6 NOTE: XXXXXXXXC indicates the Intel FPO number. Figure 4. 80C186XL/80C188XL Pinout Diagrams 16 80C186XL/80C188XL Shrink Quad Flat Pack 272431±22 NOTE: XXXXXXXXC indicates the Intel FPO number. Figure 4. 80C186XL/80C188XL Pinout Diagrams (Continued) 17 80C186XL/80C188XL Plastic Leaded Chip Carrier Contacts Facing Up Contacts Facing Down 272431±7 80-Pin Quad Flat Pack (EIAJ) Contacts Contacts Facing Up Facing Down 272431±8 NOTE: XXXXXXXXA indicates the Intel FPO number. Figure 4. 80C186XL/80C288XL Pinout Diagrams (Continued) 18 80C186XL/80C188XL Table 4. LCC/PLCC Pin Functions with Location AD Bus Bus Control Processor Control I/O AD0 17 ALE/QS0 61 RES 24 UCS 34 AD1 15 BHE (RFSH)64 RESET 57 LCS 33 AD2 13 S0 52 X1 59 AD3 11 S1 53 X2 58 MCS0/PEREQ 38 AD4 8 S2 54 CLKOUT 56 MCS1/ERROR 37 AD5 6 RD/QSMD 62 TEST/BUSY 47 MCS2 36 AD6 4 WR/QS1 63 NMI 46 MCS3/NPS 35 AD7 2 ARDY 55 INT0 45 AD8 (A8) 16 SRDY 49 INT1/SELECT 44 PCS0 25 AD9 (A9) 14 DEN 39 INT2/INTA0 42 PCS1 27 AD10 (A10) 12 DT/R 40 INT3/INTA1 41 PCS2 28 AD11 (A11) 10 LOCK 48 PCS3 29 AD12 (A12) 7 HOLD 50 PCS4 30 Power and Ground AD13 (A13) 5 HLDA 51 PCS5/A1 31 AD14 (A14) 3 V 9 PCS6/A2 32 CC AD15 (A15) 1 V 43 CC A16/S3 68 V 26 TMR IN 0 20 SS A17/S4 67 V 60 TMR IN 1 21 SS A18/S5 66 TMR OUT 0 22 A19/S6 65 TMR OUT 1 23 DRQ0 18 DRQ1 19 NOTE: Pin names in parentheses apply to the 80C188XL. Table 5. LCC/PGA/PLCC Pin Locations with Pin Names 1 AD15 (A15) 18 DRQ0 35 MCS3/NPS 52 S0 2 AD7 19 DRQ1 36 MCS2 53 S1 3 AD14 (A14) 20 TMR IN 0 37 MCS1/ERROR 54 S2 4 AD6 21 TMR IN 1 38 MCS0/PEREQ 55 ARDY 5 AD13 (A13) 22 TMR OUT 0 39 DEN 56 CLKOUT 6 AD5 23 TMR OUT 1 40 DT/R 57 RESET 7 AD12 (A12) 24 RES 41 INT3/INTA1 58 X2 8 AD4 25 PCS0 42 INT2/INTA0 59 X1 9V 26 V 43 V 60 V CC SS CC SS 10 AD11 (A11) 27 PCS1 44 INT1/SELECT 61 ALE/QS0 11 AD3 28 PCS2 45 INT0 62 RD/QSMD 12 AD10 (A10) 29 PCS3 46 NMI 63 WR/QS1 13 AD2 30 PCS4 47 TEST/BUSY 64 BHE (RFSH) 14 AD9 (A9) 31 PCS5/A1 48 LOCK 65 A19/S2 15 AD1 32 PCS6/A2 49 SRDY 66 A18/S3 16 AD8 (A8) 33 LCS 50 HOLD 67 A17/S4 17 AD0 34 UCS 51 HLDA 68 A16/S3 NOTE: Pin names in parentheses apply to the 80C188XL. 19 80C186XL/80C188XL Table 6. QFP Pin Functions with Location AD Bus Bus Control Processor Control I/O AD0 64 ALE/QS0 10 RES 55 UCS 45 AD1 66 BHE (RFSH)7 RESET 18 LCS 46 AD2 68 S0 23 X1 16 AD3 70 S1 22 X2 17 MCS0/PEREQ 39 AD4 74 S2 21 CLKOUT 19 MCS1/ERROR 40 AD5 76 RD/QSMD 9 TEST/BUSY 29 MCS2 41 AD6 78 WR/QS1 8 NMI 30 MCS3/NPS 42 AD7 80 ARDY 20 INT0 31 AD8 (A8) 65 SRDY 27 INT1/SELECT 32 PCS0 54 AD9 (A9) 67 DEN 38 INT2/INTA0 35 PCS1 52 AD10 (A10) 69 DT/R 37 INT3/INTA1 36 PCS2 51 AD11 (A11) 71 LOCK 28 PCS3 50 AD12 (A12) 75 HOLD 26 PCS4 49 Power and Ground AD13 (A13) 77 HLDA 25 PCS5/A1 48 AD14 (A14) 79 V 33 PCS6/A2 47 CC AD15 (A15) 1 V 34 CC No Connection A16/S3 3 V 72 TMR IN 0 59 CC A17/S4 4 N.C. 2 V 73 TMR IN 1 58 CC A18/S5 5 N.C. 11 V 12 TMR OUT 0 57 SS A19/S6 6 N.C. 14 V 13 TMR OUT 1 56 SS N.C. 15 V 53 SS N.C. 24 DRQ0 61 N.C. 43 DRQ1 60 N.C. 44 N.C. 62 N.C. 63 NOTE: Pin names in parentheses apply to the 80C188XL. Table 7. QFP Pin Locations with Pin Names 1 AD15 (A15) 21 S2 41 MCS2 61 DRQ0 2 N.C. 22 S1 42 MCS3/NPS 62 N.C. 3 A16/S3 23 S0 43 N.C. 63 N.C. 4 A17/S4 24 N.C. 44 N.C. 64 AD0 5 A18/S5 25 HLDA 45 UCS 65 AD8 (A8) 6 A19/S6 26 HOLD 46 LCS 66 AD1 7 BHE/(RFSH) 27 SRDY 47 PCS6/A2 67 AD9 (A9) 8WR/QS1 28 LOCK 48 PCS5/A1 68 AD2 9RD/QSMD 29 TEST/BUSY 49 PCS4 69 AD10 (A10) 10 ALE/QS0 30 NMI 50 PCS3 70 AD3 11 N.C. 31 INT0 51 PCS2 71 AD11 (A11) 12 V 32 INT1/SELECT 52 PCS1 72 V SS CC 13 V 33 V 53 V 73 V SS CC SS CC 14 N.C. 34 V 54 PCS0 74 AD4 CC 15 N.C. 35 INT2/INTA0 55 RES 75 AD12 (A12) 16 X1 36 INT3/INTA1 56 TMR OUT 1 76 AD5 17 X2 37 DT/R 57 TMR OUT 0 77 AD13 (A13) 18 RESET 38 DEN 58 TMR IN 1 78 AD6 19 CLKOUT 39 MCS0/PEREQ 59 TMR IN 0 79 AD14 (A14) 20 ARDY 40 MCS1/ERROR 60 DRQ1 80 AD7 NOTE: Pin names in parentheses apply to the 80C188XL. 20 80C186XL/80C188XL Table 8. SQFP Pin Functions with Location AD Bus Bus Control Processor Control I/O AD0 1 ALE/QS0 29 RES 73 UCS 62 AD1 3 BHE (RFSH)26 RESET 34 LCS 63 AD2 6 S0 40 X1 32 AD3 8 S1 39 X2 33 MCS0/PEREQ 57 AD4 12 S2 38 CLKOUT 36 MCS1/ERROR 58 AD5 14 RD/QSMD 28 TEST/BUSY 46 MCS2 59 AD6 16 WR/QS1 27 NMI 47 MCS3/NPS 60 AD7 18 ARDY 37 INT0 48 AD8 (A8) 2 SRDY 44 INT1/SELECT 49 PCS0 71 AD9 (A9) 5 DEN 56 INT2/INTA0 52 PCS1 69 AD10 (A10) 7 DT/R 54 INT3/INTA1 53 PCS2 68 AD11 (A11) 9 LOCK 45 PCS3 67 AD12 (A12) 13 HOLD 43 PCS4 66 Power and Ground AD13 (A13) 15 HLDA 42 PCS5/A1 65 AD14 (A14) 17 V 10 PCS6/A2 64 CC AD15 (A15) 19 V 11 CC No Connection A16/S3 21 V 20 TMR IN 0 77 CC A17/S4 22 N.C. 4 V 50 TMR IN 1 76 CC A18/S5 23 N.C. 25 V 51 TMR OUT 0 75 CC A19/S6 24 N.C. 35 V 61 TMR OUT 1 74 CC N.C. 55 V 30 SS N.C. 72 V 31 DRQ0 79 SS V 41 DRQ1 78 SS V 70 SS V 80 SS NOTE: Pin names in parentheses apply to the 80C188XL. Table 9. SQFP Pin Locations with Pin Names 1 AD0 21 A16/S3 41 V 61 V SS CC 2 AD8 (A8) 22 A17/S4 42 HLDA 62 UCS 3 AD1 23 A18/S5 43 HOLD 63 LCS 4 N.C. 24 A19/S6 44 SRDY 64 PCS6/A2 5 AD9 (A9) 25 N.C. 45 LOCK 65 PCS5/A1 6 AD2 26 BHE (RFSH) 46 TEST/BUSY 66 PCS4 7 AD10 (A10) 27 WR/QS1 47 NMI 67 PCS3 8 AD3 28 RD/QSMD 48 INT0 68 PCS2 9 AD11 (A11) 29 ALE/QS0 49 INT1/SELECT 69 PCS1 10 V 30 V 50 V 70 V CC SS CC SS 11 V 31 V 51 V 71 PCS0 CC SS CC 12 AD4 32 X1 52 INT2/INTA0 72 N.C. 13 AD12 (A12) 33 X2 53 INT3/INTA1 73 RES 14 AD5 34 RESET 54 DT/R 74 TMR OUT 1 15 AD13 (A13) 35 N.C. 55 N.C. 75 TMR OUT 0 16 AD6 36 CLKOUT 56 DEN 76 TMR IN 1 17 AD14 (A14) 37 ARDY 57 MCS0/PEREQ 77 TMR IN 0 18 AD7 38 S2 58 MCS1/ERROR 78 DRQ1 19 AD15 (A15) 39 S1 59 MCS2 79 DRQ0 20 V 40 S0 60 MCS3/NPS 80 V CC SS NOTE: Pin names in parentheses apply to the 80C188XL. 21 80C186XL/80C188XL ELECTRICAL SPECIFICATIONS NOTICE: This data sheet contains preliminary infor- mation on new products in production. The specifica- tions are subject to change without notice. Verify with your local Intel Sales office that you have the latest Absolute Maximum Ratings* data sheet before finalizing a design. a Ambient Temperature under Bias ÀÀÀÀ0 Cto 70 C § § *WARNING: Stressing the device beyond the ``Absolute b a Storage Temperature ÀÀÀÀÀÀÀÀÀÀ 65 Cto 150 C § § Maximum Ratings'' may cause permanent damage. These are stress ratings only. Operation beyond the Voltage on Any Pin with ``Operating Conditions'' is not recommended and ex- b a Respect to Ground ÀÀÀÀÀÀÀÀÀÀÀÀ 1.0V to 7.0V tended exposure beyond the ``Operating Conditions'' Package Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1W may affect device reliability. Not to exceed the maximum allowable die tempera- ture based on thermal resistance of the package. NOTICE: The specifications are subject to change without notice. e a e g DC SPECIFICATIONS T 0§Cto 70§C, V 5V 10% A CC Symbol Parameter Min Max Units Test Conditions b b V Input Low Voltage 0.5 0.2 V 0.3 V IL CC (Except X1) b V Clock Input Low 0.5 0.6 V IL1 Voltage (X1) a a V Input High Voltage 0.2 V 0.9 V 0.5 V IH CC CC (All except X1 and RES) a V Input High Voltage (RES) 3.0 V 0.5 V IH1 CC a V Clock Input High 3.9 V 0.5 V IH2 CC Voltage (X1) e V Output Low Voltage 0.45 V I 2.5 mA (S0, 1, 2) OL OL e I 2.0 mA (others) OL (4) eb @ V Output High Voltage 2.4 V VI 2.4 mA 2.4V OH CC OH (4) b eb @ b V 0.5 V VI 200 mA V 0.5 CC CC OH CC @ I Power Supply Current 100 mA 25 MHz, 0 C § CC (3) e V 5.5V CC @ 90 mA 20 MHz, 0 C § (3) e V 5.5V CC @ 62.5 mA 12 MHz, 0 C § (3) e V 5.5V CC @ 100 mA DC 0§C e V 5.5V CC @ g I Input Leakage Current 10 mA 0.5 MHz, LI s s 0.45V V V IN CC @ I Output Leakage Current g10 mA 0.5 MHz, LO s s (1) 0.45V V V OUT CC e V Clock Output Low 0.45 V I 4.0 mA CLO CLO 22 80C186XL/80C188XL e a e DC SPECIFICATIONS (Continued) T 0 Cto 70 C, V 5V g10% § § A CC Symbol Parameter Min Max Units Test Conditions b eb V Clock Output High V 0.5 V I 500 mA CHO CC CHO (2) @ C Input Capacitance 10 pF 1 MHz IN @ (2) C Output or I/O Capacitance 20 pF 1 MHz IO NOTES: 1. Pins being floated during HOLD or by invoking the ONCE Mode. e a 2. Characterization conditions are a) Frequency 1 MHz; b) Unmeasured pins at GND; c) V at 5.0V or 0.45V. This IN parameter is not tested. 3. Current is measured with the device in RESET with X1 and X2 driven and all other non-power pins open. 4. RD/QSMD, UCS, LCS, MCS0/PEREQ, MCS1/ERROR and TEST/BUSY pins have internal pullup devices. Loading some of these pins above I eb200 mA can cause the processor to go into alternative modes of operation. See the section on OH Local Bus Controller and Reset for details. Power Supply Current Current is linearly proportional to clock frequency and is measured with the device in RESET with X1 and X2 driven and all other non-power pins open. e c Maximum current is given by I 5mA freq. CC a (MHz) I . QL I is the quiescent leakage current when the clock QL is static. I is typically less than 100 mA. QL 272431±9 Figure 5. I vs Frequency CC 23 80C186XL/80C188XL AC SPECIFICATIONS MAJOR CYCLE TIMINGS (READ CYCLE) e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) T Data in Setup (A/D) 8 10 15 ns DVCL T Data in Hold (A/D) 3 3 3 ns CLDX 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) T Status Active Delay 3 20 3 25 3 35 ns CHSV T Status Inactive Delay 3 20 3 25 3 35 ns CLSH T Address Valid Delay 3 20 3 27 3 36 ns CLAV T Address Hold 0 0 0 ns CLAX T Data Valid Delay 3 20 3 27 3 36 ns CLDV T Status Hold Time 10 10 10 ns CHDX T ALE Active Delay 20 20 25 ns CHLH b b b T ALE Width T 15 T 15 T 15 ns LHLL CLCL CLCL CLCL T ALE Inactive Delay 20 20 25 ns CHLL b b b T Address Valid to ALE Low T 10 T 10 T 15 ns Equal AVLL CLCH CLCH CLCH Loading b b b T Address Hold from ALE T 8T 10 T 15 ns Equal LLAX CHCL CHCL CHCL Inactive Loading T Address Valid to Clock High 0 0 0 ns AVCH T Address Float Delay T 20 T 20 T 25 ns CLAZ CLAX CLAX CLAX T Chip-Select Active Delay 3 20 3 25 3 33 ns CLCSV b b b T Chip-Select Hold from T 10 T 10 T 10 ns Equal CXCSX CLCH CLCH CLCH Command Inactive Loading T Chip-Select Inactive Delay 3 17 3 20 3 30 ns CHCSX T DEN Inactive to DT/R Low 0 0 0 ns Equal DXDL Loading T Control Active Delay 1 3 17 3 22 3 37 ns CVCTV T DEN Inactive Delay 3 17 3 22 3 37 ns CVDEX T Control Active Delay 2 3 20 3 22 3 37 ns CHCTV T LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns CLLV 24 80C186XL/80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (READ CYCLE) (Continued) e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL TIMING RESPONSES (Read Cycle) T Address Float 0 0 0 ns AZRL to RD Active T RD Active Delay 3 20 3 27 3 37 ns CLRL b b b T RD Pulse Width 2T 15 2T 20 2T 25 ns RLRH CLCL CLCL CLCL T RD Inactive Delay 3 20 3 27 3 37 ns CLRH b b b T RD Inactive T 14 T 14 T 14 ns Equal RHLH CLCH CLCH CLCH to ALE High Loading b b b T RD Inactive to T 15 T 15 T 15 ns Equal RHAV CLCL CLCL CLCL Address Active Loading 25 80C186XL/80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (WRITE CYCLE) e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) T Status Active Delay 3 20 3 25 3 35 ns CHSV T Status Inactive Delay 3 20 3 25 3 35 ns CLSH T Address Valid Delay 3 20 3 27 3 36 ns CLAV T Address Hold 0 0 0 ns CLAX T Data Valid Delay 3 20 3 27 3 36 ns CLDV T Status Hold Time 10 10 10 ns CHDX T ALE Active Delay 20 20 25 ns CHLH b b b T ALE Width T 15 T 15 T 15 ns LHLL CLCL CLCL CLCL T ALE Inactive Delay 20 20 25 ns CHLL b b b T Address Valid to ALE Low T 10 T 10 T 15 ns Equal AVLL CLCH CLCH CLCH Loading b b b T Address Hold from ALE T 10 T 10 T 15 ns Equal LLAX CHCL CHCL CHCL Inactive Loading T Address Valid to Clock High 0 0 0 ns AVCH T Data Hold Time 3 3 3 ns CLDOX T Control Active Delay 1 3 20 3 25 3 37 ns CVCTV T Control Inactive Delay 3 17 3 25 3 37 ns CVCTX T Chip-Select Active Delay 3 20 3 25 3 33 ns CLCSV b b b T Chip-Select Hold from T 10 T 10 T 10 ns Equal CXCSX CLCH CLCH CLCH Command Inactive Loading T Chip-Select Inactive Delay 3 17 3 20 3 30 ns CHCSX T DEN Inactive to DT/R Low 0 0 0 ns Equal DXDL Loading T LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns CLLV 80C186XL TIMING RESPONSES (Write Cycle) b b b T WR Pulse Width 2T 15 2T 20 2T 25 ns WLWH CLCL CLCL CLCL b b b T WR Inactive to ALE High T 14 T 14 T 14 ns Equal WHLH CLCH CLCH CLCH Loading b b b T Data Hold after WR T 10 T 15 T 20 ns Equal WHDX CLCL CLCL CLCL Loading b b b T WR Inactive to DEN Inactive T 10 T 10 T 10 ns Equal WHDEX CLCH CLCH CLCH Loading 26 80C186XL/80C188XL AC SPECIFICATIONS (Continued) MAJOR CYCLE TIMINGS (INTERRUPT ACKNOWLEDGE CYCLE) e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) T Data in Setup (A/D) 8 10 15 ns DVCL T Data in Hold (A/D) 3 3 3 ns CLDX 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) T Status Active Delay 3 20 3 25 3 35 ns CHSV T Status Inactive Delay 3 20 3 25 3 35 ns CLSH T Address Valid Delay 3 20 3 27 3 36 ns CLAV T Address Valid to Clock High 0 0 0 ns AVCH T Address Hold 0 0 0 ns CLAX T Data Valid Delay 3 20 3 27 3 36 ns CLDV T Status Hold Time 10 10 10 ns CHDX T ALE Active Delay 20 20 25 ns CHLH b b b T ALE Width T 15 T 15 T 15 ns LHLL CLCL CLCL CLCL T ALE Inactive Delay 20 20 25 ns CHLL b b b T Address Valid to ALE Low T 10 T 10 T 15 ns Equal AVLL CLCH CLCH CLCH Loading b b b T Address Hold to ALE T 10 T 10 T 15 ns Equal LLAX CHCL CHCL CHCL Inactive Loading T Address Float Delay T 20 T 20 T 25 ns CLAZ CLAX CLAX CLAX T Control Active Delay 1 3 17 3 25 3 37 ns CVCTV T Control Inactive Delay 3 17 3 25 3 37 ns CVCTX T DEN Inactive to DT/R Low 0 0 0 ns Equal DXDL Loading T Control Active Delay 2 3 20 3 22 3 37 ns CHCTV T DEN Inactive Delay 3 17 3 22 3 37 ns CVDEX (Non-Write Cycles) T LOCK Valid/Invalid Delay 3 17 3 22 3 37 ns CLLV 27 80C186XL/80C188XL AC SPECIFICATIONS (Continued) SOFTWARE HALT CYCLE TIMINGS e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL GENERAL TIMING REQUIREMENTS (Listed More Than Once) T Status Active Delay 3 20 3 25 3 35 ns CHSV T Status Inactive Delay 3 20 3 25 3 35 ns CLSH T Address Valid Delay 3 20 3 27 3 36 ns CLAV T ALE Active Delay 20 20 25 ns CHLH b b b T ALE Width T 15 T 15 T 15 ns LHLL CLCL CLCL CLCL T ALE Inactive Delay 20 20 25 ns CHLL T DEN Inactive to DT/R Low 0 0 0 ns Equal DXDL Loading T Control Active Delay 2 3 20 3 22 3 37 ns CHCTV 28 80C186XL/80C188XL AC SPECIFICATIONS (Continued) CLOCK TIMINGS e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max (1) 80C186XL CLKIN REQUIREMENTS % % % T CLKIN Period 20 25 40 ns CKIN % % % (2) T CLKIN Low Time 8 10 16 ns 1.5V CLCK % % % (2) T CLKIN High Time 8 10 16 ns 1.5V CHCK T CLKIN Fall Time 5 5 5 ns 3.5 to 1.0V CKHL T CLKIN Rise Time 5 5 5 ns 1.0 to 3.5V CKLH 80C186XL CLKOUT TIMING T CLKIN to 17 17 21 ns CICO CLKOUT Skew % % T CLKOUT Period 40 50 80 ns CLCL (3) b b b e T CLKOUT 0.5 T 5 0.5 T 5 0.5 T 5ns C 100 pF CLCH CLCL CLCL CLCL L Low Time (4) b b b e T CLKOUT 0.5 T 5 0.5 T 5 0.5 T 5ns C 100 pF CHCL CLCL CLCL CLCL L High Time T CLKOUT 6 8 10 ns 1.0 to 3.5V CH1CH2 Rise Time T CLKOUT 6 8 10 ns 3.5 to 1.0V CL2CL1 Fall Time NOTES: 1. External clock applied to X1 and X2 not connected. 2. T and T (CLKIN Low and High times) should not have a duration less than 40% of T . CLCK CHCK CKIN 3. Tested under worst case conditions: V e 5.5V. T e 70 C. § CC A 4. Tested under worst case conditions: V e 4.5V. T e 0 C. § CC A 29 80C186XL/80C188XL AC SPECIFICATIONS (Continued) READY, PERIPHERAL AND QUEUE STATUS TIMINGS e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL READY AND PERIPHERAL TIMING REQUIREMENTS (Listed More Than Once) T Synchronous Ready (SRDY) 8 10 15 ns SRYCL (1) Transition Setup Time (1) T SRDY Transition Hold Time 810 15 ns CLSRY T ARDY Resolution Transition 8 10 15 ns ARYCH (2) Setup Time (1) T ARDY Active Hold Time 810 15 ns CLARX T ARDY Inactive Holding Time 8 10 15 ns ARYCHL T Asynchronous Ready 10 15 25 ns ARYLCL (1) (ARDY) Setup Time T INTx, NMI, TEST/BUSY, 8 10 15 ns INVCH (2) TMR IN Setup Time (2) T DRQ0, DRQ1 Setup Time 810 15 ns INVCL 80C186XL PERIPHERAL AND QUEUE STATUS TIMING RESPONSES T Timer Output Delay 17 22 33 ns CLTMV T Queue Status Delay 22 27 32 ns CHQSV NOTES: 1. To guarantee proper operation. 2. To guarantee recognition at clock edge. 30 80C186XL/80C188XL AC SPECIFICATIONS (Continued) RESET AND HOLD/HLDA TIMINGS e a e T 0 Cto 70 C, V 5V g10% § § A CC All timings are measured at 1.5V and 50 pF loading on CLKOUT unless otherwise noted. e All output test conditions are with C 50 pF. L e e e b For AC tests, input V 0.45V and V 2.4V except at X1 where V V 0.5V. IL IH IH CC Values Test Symbol Parameter 80C186XL25 80C186XL20 80C186XL12 Unit Conditions Min Max Min Max Min Max 80C186XL RESET AND HOLD/HLDA TIMING REQUIREMENTS T RES Setup 15 15 15 ns RESIN (1) T HOLD Setup 810 15 ns HVCL 80C186XL GENERAL TIMING RESPONSES (Listed More Than Once) T Address Float Delay T 20 T 20 T 25 ns CLAZ CLAX CLAX CLAX T Address Valid Delay 3 20 3 22 3 36 ns CLAV 80C186XL RESET AND HOLD/HLDA TIMING RESPONSES T Reset Delay 17 22 33 ns CLRO T HLDA Valid Delay 3 17 3 22 3 33 ns CLHAV T Command Lines Float Delay 22 25 33 ns CHCZ T Command Lines Valid Delay 20 26 36 ns CHCV (after Float) NOTE: 1. To guarantee recognition at next clock. 31 80C186XL/80C188XL AC SPECIFICATIONS (Continued) 272431±10 NOTES: 1. Status inactive in state preceding T . 4 2. If latched A and A are selected instead of PCS5 and PCS6, only T is applicable. 1 2 CLCSV 3. For write cycle followed by read cycle. 4. T of next bus cycle. 1 5. Changes in T-state preceding next bus cycle if followed by write. Pin names in parentheses apply to the 80C188XL. Figure 6. Read Cycle Waveforms 32 80C186XL/80C188XL AC SPECIFICATIONS (Continued) 272431±11 NOTES: 1. Status inactive in state preceding T . 4 2. If latched A and A are selected instead of PCS5 and PCS6, only T is applicable. 1 2 CLCSV 3. For write cycle followed by read cycle. 4. T of next bus cycle. 1 5. Changes in T-state preceding next bus cycle if followed by read, INTA, or halt. Pin names in parentheses apply to the 80C188XL. Figure 7. Write Cycle Waveforms 33 80C186XL/80C188XL AC SPECIFICATIONS (Continued) 272431±12 NOTES: 1. Status inactive in state preceding T . 4 2. The data hold time lasts only until INTA goes inactive, even if the INTA transition occurs prior to T (min). CLDX 3. INTA occurs one clock later in Slave Mode. 4. For write cycle followed by interrupt acknowledge cycle. 5. LOCK is active upon T of the first interrupt acknowledge cycle and inactive upon T of the second interrupt acknowl- 1 2 edge cycle. 6. Changes in T-state preceding next bus cycle if followed by write. Pin names in parentheses apply to the 80C188XL. Figure 8. Interrupt Acknowledge Cycle Waveforms 34 80C186XL/80C188XL AC SPECIFICATIONS (Continued) 272431±13 NOTE: 1. For write cycle followed by halt cycle. Pin names in parentheses apply to the 80C188XL. Figure 9. Software Halt Cycle Waveforms 35 80C186XL/80C188XL WAVEFORMS 272431±14 Figure 10. Clock Waveforms 272431±15 Figure 11. Reset Waveforms 272431±16 Figure 12. Synchronous Ready (SRDY) Waveforms 36 80C186XL/80C188XL AC CHARACTERISTICS 272431±23 Figure 13. Asynchronous Ready (ARDY) Waveforms 272431±17 Figure 14. Peripheral and Queue Status Waveforms 37 80C186XL/80C188XL AC CHARACTERISTICS (Continued) 272431±24 Figure 15. HOLDA/HLDA Waveforms (Entering Hold) 272431±18 Figure 16. HOLD/HLDA Waveforms (Leaving Hold) 38 80C186XL/80C188XL EXPLANATION OF THE AC SYMBOLS Each timing symbol has from 5 to 7 characters. The first character is always a `T' (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address ARY: Asynchronous Ready Input C: Clock Output CK: Clock Input CS: Chip Select CT: Control (DT/R, DEN, ... ) D: Data Input DE: DEN H: Logic Level High OUT: Input (DRQ0, TIM0, . . . ) L: Logic Level Low or ALE O: Output QS: Queue Status (QS1, QS2) R: RD Signal, RESET Signal S: Status (S0,S1,S2) SRY: Synchronous Ready Input V: Valid W: WR Signal X: No Longer a Valid Logic Level Z: Float Examples: T Ð Time from Clock low to Address valid CLAV T Ð Time from Clock high to ALE high CHLH T Ð Time from Clock low to Chip Select valid CLCSV 39 80C186XL/80C188XL DERATING CURVES Typical Output Delay Capacitive Derating 272431±19 Figure 17. Capacitive Derating Curve Typical Rise and Fall Times for TTL Voltage Levels 272431±20 Figure 18. TTL Level Rise and Fall Times for Output Buffers Typical Rise and Fall Times for CMOS Voltage Levels 272431±21 Figure 19. CMOS Level Rise and Fall Times for Output Buffers 40 80C186XL/80C188XL 80C186XL/80C188XL EXPRESS 80C186XL/80C188XL EXECUTION TIMINGS The Intel EXPRESS system offers enhancements to the operational specifications of the 80C186XL mi- A determination of program execution timing must croprocessor. EXPRESS products are designed to consider the bus cycles necessary to prefetch in- meet the needs of those applications whose operat- structions as well as the number of execution unit ing requirements exceed commercial standards. cycles necessary to execute instructions. The fol- lowing instruction timings represent the minimum ex- The 80C186XL EXPRESS program includes an ex- ecution time in clock cycles for each instruction. The tended temperature range. With the commercial timings given are based on the following assump- standard temperature range, operational character- tions: istics are guaranteed over the temperature range of # The opcode, along with any data or displacement a 0§Cto 70§C. With the extended temperature range required for execution of a particular instruction, option, operational characteristics are guaranteed has been prefetched and resides in the queue at b a over the range of 40§Cto 85§C. the time it is needed. # No wait states or bus HOLDs occur. Package types and EXPRESS versions are identified by a one or two-letter prefix to the part number. The # All word-data is located on even-address bound- prefixes are listed in Table 10. All AC and DC specifi- aries (80C186XL only). cations not mentioned in this section are the same for both commercial and EXPRESS parts. All jumps and calls include the time required to fetch the opcode of the next instruction at the destination Table 10. Prefix Identification address. Package Temperature Prefix All instructions which involve memory accesses can Type Range require one or two additional clocks above the mini- mum timings shown due to the asynchronous hand- A PGA Commercial shake between the bus interface unit (BIU) and exe- N PLCC Commercial cution unit. R LCC Commercial With a 16-bit BIU, the 80C186XL has sufficient bus S QFP Commercial performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) SB SQFP Commercial most of the time. Therefore, actual program execu- TA PGA Extended tion time will not be substantially greater than that derived from adding the instruction timings shown. TN PLCC Extended TR LCC Extended The 80C188XL 8-bit BIU is limited in its performance relative to the execution unit. A sufficient number of TS QFP Extended prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time. Therefore, actual program execution time will be substantially greater than that derived from adding the instruction timings shown. 41 80C186XL/80C188XL INSTRUCTION SET SUMMARY 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER e MOV Move: Register to Register/Memory 1000100w modreg r/m 2/12 2/12* Register/memory to register 1000101w modreg r/m 2/9 2/9* e Immediate to register/memory 1100011w mod000 r/m data data if w 1 12/13 12/13 8/16-bit e Immediate to register 1011w reg data data if w 1 3/4 3/4 8/16-bit Memory to accumulator 1010000w addr-low addr-high 8 8* Accumulator to memory 1010001w addr-low addr-high 9 9* Register/memory to segment register 10001110 mod0reg r/m 2/9 2/13 Segment register to register/memory 10001100 mod0reg r/m 2/11 2/15 PUSH e Push: Memory 11111111 mod110 r/m 16 20 Register 01010 reg 10 14 Segment register 000reg110 9 13 Immediate 011010s0 data data if se010 14 PUSHA e Push All 01100000 36 68 e POP Pop: Memory 10001111 mod000 r/m 20 24 Register 01011 reg 10 14 i Segment register 000reg111 (reg 01) 8 12 e POPA PopAll 01100001 51 83 e XCHG Exchange: Register/memory with register 1000011w modreg r/m 4/17 4/17* Register with accumulator 10010 reg 3 3 e IN Input from: Fixed port 1110010w port 10 10* Variable port 1110110w 8 8* OUT e Output to: Fixed port 1110011w port 9 9* Variable port 1110111w 7 7* e XLAT Translate byte to AL 11010111 11 15 e LEA Load EA to register 10001101 modreg r/m 6 6 e i LDS Load pointer to DS 11000101 modreg r/m (mod 11) 18 26 e i LES Load pointer to ES 11000100 modreg r/m (mod 11) 18 26 e LAHF Load AH with flags 10011111 2 2 e SAHF Store AH into flags 10011110 3 3 e PUSHF Push flags 10011100 9 13 e POPF Pop flags 10011101 8 12 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. 42 80C186XL/80C188XL INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles DATA TRANSFER (Continued) e SEGMENT Segment Override: CS 00101110 2 2 SS 00110110 2 2 DS 00111110 2 2 ES 00100110 2 2 ARITHMETIC e ADD Add: Reg/memory with register to either 000000dw modreg r/m 3/10 3/10* e Immediate to register/memory 100000sw mod000 r/m data data if s w 01 4/16 4/16* Immediate to accumulator 0000010w data data if we1 3/4 3/4 8/16-bit e ADC Add with carry: Reg/memory with register to either 000100dw modreg r/m 3/10 3/10* Immediate to register/memory 100000sw mod010 r/m data data if s we01 4/16 4/16* e Immediate to accumulator 0001010w data data if w 1 3/4 3/4 8/16-bit e INC Increment: Register/memory 1111111w mod000 r/m 3/15 3/15* Register 01000 reg 3 3 e SUB Subtract: Reg/memory and register to either 001010dw modreg r/m 3/10 3/10* Immediate from register/memory 100000sw mod101 r/m data data if s we01 4/16 4/16* e Immediate from accumulator 0010110w data data if w 1 3/4 3/4 8/16-bit SBB e Subtract with borrow: Reg/memory and register to either 000110dw modreg r/m 3/10 3/10* e Immediate from register/memory 100000sw mod011 r/m data data if s w 01 4/16 4/16* Immediate from accumulator 0001110w data data if we1 3/4 3/4* 8/16-bit e DEC Decrement Register/memory 1111111w mod001 r/m 3/15 3/15* Register 01001 reg 3 3 e CMP Compare: Register/memory with register 0011101w modreg r/m 3/10 3/10* Register with register/memory 0011100w modreg r/m 3/10 3/10* e Immediate with register/memory 100000sw mod111 r/m data data if s w 01 3/10 3/10* e Immediate with accumulator 0011110w data data if w 1 3/4 3/4 8/16-bit e NEG Change sign register/memory 1111011w mod011 r/m 3/10 3/10* e AAA ASCII adjust for add 00110111 8 8 e DAA Decimal adjust for add 00100111 4 4 e AAS ASCII adjust for subtract 00111111 7 7 DAS e Decimal adjust for subtract 00101111 4 4 MUL e Multiply (unsigned): 1111011w mod100 r/m Register-Byte 26±28 26±28 Register-Word 35±37 35±37 Memory-Byte 32±34 32±34 Memory-Word 41±43 41±43* Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. 43 80C186XL/80C188XL INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles ARITHMETIC (Continued) IMUL e Integer multiply (signed): 1111011w mod101 r/m Register-Byte 25±28 25±28 Register-Word 34±37 34±37 Memory-Byte 31±34 32±34 Memory-Word 40±43 40±43* IMUL e Integer Immediate multiply 011010s1 modreg r/m data data if se0 22±25/ 22±25/ (signed) 29±32 29±32 e DIV Divide (unsigned): 1111011w mod110 r/m Register-Byte 29 29 Register-Word 38 38 Memory-Byte 35 35 Memory-Word 44 44* e IDIV Integer divide (signed): 1111011w mod111 r/m Register-Byte 44±52 44-52 Register-Word 53±61 53±61 Memory-Byte 50±58 50±58 Memory-Word 59±67 59±67* e AAM ASCII adjust for multiply 11010100 00001010 19 19 e AAD ASCII adjust for divide 11010101 00001010 15 15 e CBW Convert byte to word 10011000 2 2 e CWD Convert word to double word 10011001 4 4 LOGIC Shift/Rotate Instructions: Register/Memory by 1 1101000w modTTTr/m 2/15 2/15 Register/Memory by CL 1101001w modTTTr/m 5an/17an5an/17an Register/Memory by Count 1100000w modTTTr/m count 5an/17an5an/17an TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL/SAL 101 SHR 111 SAR e AND And: Reg/memory and register to either 001000dw modreg r/m 3/10 3/10* e Immediate to register/memory 1000000w mod100 r/m data data if w 1 4/16 4/16* e Immediate to accumulator 0010010w data data if w 1 3/4 3/4* 8/16-bit e TEST And function to flags, no result: Register/memory and register 1000010w modreg r/m 3/10 3/10* e Immediate data and register/memory 1111011w mod000 r/m data data if w 1 4/10 4/10* Immediate data and accumulator 1010100w data data if we1 3/4 3/4 8/16-bit OReOr: Reg/memory and register to either 000010dw modreg r/m 3/10 3/10* Immediate to register/memory 1000000w mod001 r/m data data if we1 4/16 4/16* Immediate to accumulator 0000110w data data if we1 3/4 3/4* 8/16-bit Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. 44 80C186XL/80C188XL INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles LOGIC (Continued) XOR e Exclusive or: Reg/memory and register to either 001100dw modreg r/m 3/10 3/10* Immediate to register/memory 1000000w mod110 r/m data data if we1 4/16 4/16* Immediate to accumulator 0011010w data data if we1 3/4 3/4 8/16-bit NOT e Invert register/memory 1111011w mod010 r/m 3/10 3/10* STRING MANIPULATION e MOVS Move byte/word 1010010w 14 14* e CMPS Compare byte/word 1010011w 22 22* e SCAS Scan byte/word 1010111w 15 15* e LODS Load byte/wd to AL/AX 1010110w 12 12* e STOS Store byte/wd from AL/AX 1010101w 10 10* e INS Input byte/wd from DX port 0110110w 14 14 e OUTS Output byte/wd to DX port 0110111w 14 14 Repeated by count in CX (REP/REPE/REPZ/REPNE/REPNZ) e a a MOVS Move string 11110010 1010010w 8 8n 8 8n* e a a CMPS Compare string 1111001z 1010011w 5 22n 5 22n* SCAS e Scan string 1111001z 1010111w 5a15n 5a15n* LODS e Load string 11110010 1010110w 6a11n 6a11n* STOS e Store string 11110010 1010101w 6a9n 6a9n* INS e Input string 11110010 0110110w 8a8n 8a8n* OUTS e Output string 11110010 0110111w 8a8n 8a8n* CONTROL TRANSFER CALL e Call: Direct within segment 11101000 disp-low disp-high 15 19 Register/memory 11111111 mod010 r/m 13/19 17/27 indirect within segment Direct intersegment 10011010 segment offset 23 31 segment selector i Indirect intersegment 11111111 mod011 r/m (mod 11) 38 54 e JMP Unconditional jump: Short/long 11101011 disp-low 14 14 Direct within segment 11101001 disp-low disp-high 14 14 Register/memory 11111111 mod100 r/m 11/17 11/21 indirect within segment Direct intersegment 11101010 segment offset 14 14 segment selector i Indirect intersegment 11111111 mod101 r/m (mod 11) 26 34 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. 45 80C186XL/80C188XL INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles CONTROL TRANSFER (Continued) RET e Return from CALL: Within segment 11000011 16 20 Within seg adding immed to SP 11000010 data-low data-high 18 22 Intersegment 11001011 22 30 Intersegment adding immediate to SP 11001010 data-low data-high 25 33 e JE/JZ Jump on equal/zero 01110100 disp 4/13 4/13 JMP not taken/JMP e JL/JNGE Jump on less/not greater or equal 01111100 disp 4/13 4/13 taken e JLE/JNG Jump on less or equal/not greater 01111110 disp 4/13 4/13 e JB/JNAE Jump on below/not above or equal 01110010 disp 4/13 4/13 e JBE/JNA Jump on below or equal/not above 01110110 disp 4/13 4/13 e JP/JPE Jump on parity/parity even 01111010 disp 4/13 4/13 e JO Jump on overflow 01110 000 disp 4/13 4/13 e JS Jump on sign 01111000 disp 4/13 4/13 e JNE/JNZ Jump on not equal/not zero 01110101 disp 4/13 4/13 e JNL/JGE Jump on not less/greater or equal 01111101 disp 4/13 4/13 e JNLE/JG Jump on not less or equal/greater 01111111 disp 4/13 4/13 e JNB/JAE Jump on not below/above or equal 01110011 disp 4/13 4/13 e JNBE/JA Jump on not below or equal/above 01110111 disp 4/13 4/13 e JNP/JPO Jump on not par/par odd 01111011 disp 4/13 4/13 e JNO Jump on not overflow 01110001 disp 4/13 4/13 e JNS Jump on not sign 01111001 disp 4/13 4/13 e JCXZ Jump on CX zero 11100011 disp 5/15 5/15 e LOOP Loop CX times 11100010 disp 6/16 6/16 LOOP not taken/LOOP e LOOPZ/LOOPE Loop while zero/equal 11100001 disp 6/16 6/16 taken e LOOPNZ/LOOPNE Loop while not zero/equal 11100000 disp 6/16 6/16 e ENTER Enter Procedure 11001000 data-low data-high L e L 0 15 19 L e 1 25 29 l a b a b L 1 22 16(n 1) 26 20(n 1) e LEAVE Leave Procedure 11001001 8 8 e INT Interrupt: Type specified 11001101 type 47 47 Type 3 11001100 45 45 if INT. taken/ if INT. not INTO e Interrupt on overflow 11001110 48/4 48/4 taken e IRET Interrupt return 11001111 28 28 e BOUND Detect value out of range 01100010 modreg r/m 33±35 33±35 Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. 46 80C186XL/80C188XL INSTRUCTION SET SUMMARY (Continued) 80C186XL 80C188XL Function Format Clock Clock Comments Cycles Cycles PROCESSOR CONTROL CLC e Clear carry 11111000 2 2 CMC e Complement carry 11110101 2 2 STC e Set carry 11111001 2 2 CLD e Clear direction 11111100 2 2 e STD Set direction 11111101 2 2 e CLI Clear interrupt 11111010 2 2 e STI Set interrupt 11111011 2 2 e HLT Halt 11110100 2 2 e e WAIT Wait 10011011 6 6 if TEST 0 e LOCK Bus lock prefix 11110000 2 2 e NOP No Operation 10010000 3 3 (TTT LLL are opcode to processor extension) Shaded areas indicate instructions not available in 8086/8088 microsystems. NOTE: *Clock cycles shown for byte transfers. For word operations, add 4 clock cycles for all memory transfers. The Effective Address (EA) of the memory operand reg is assigned according to the following: is computed according to the mod and r/m fields: e Segment if mod 11 then r/m is treated as a REG field e e if mod 00 then DISP 0*, disp-low and disp- reg Register high are absent 00 ES e e if mod 01 then DISP disp-low sign-ex- 01 CS tended to 16-bits, disp-high is absent 10 SS e e if mod 10 then DISP disp-high: disp-low 11 DS e e a a if r/m 000 then EA (BX) (SI) DISP e e a a if r/m 001 then EA (BX) (DI) DISP REG is assigned according to the following table: e e a a if r/m 010 then EA (BP) (SI) DISP e e e e a a 16-Bit (w 1) 8-Bit (w 0) if r/m 011 then EA (BP) (DI) DISP e e a if r/m 100 then EA (SI) DISP 000 AX 000 AL e e a if r/m 101 then EA (DI) DISP 001 CX 001 CL e e a if r/m 110 then EA (BP) DISP* 010 DX 010 DL e e a if r/m 111 then EA (BX) DISP 011 BX 011 BL 100 SP 100 AH DISP follows 2nd byte of instruction (before data if 101 BP 101 CH required) 110 SI 110 DH e e e *except if mod 00 and r/m 110 then EA 111 DI 111 BH disp-high: disp-low. The physical addresses of all operands addressed EA calculation time is 4 clock cycles for all modes, by the BP register are computed using the SS seg- and is included in the execution times given whenev- ment register. The physical addresses of the desti- er appropriate. nation operands of the string primitive operations (those addressed by the DI register) are computed Segment Override Prefix using the ES segment, which may not be overridden. 0 0 1 reg 1 1 0 47 80C186XL/80C188XL 1. An internal condition with the interrupt controller REVISION HISTORY can cause no acknowledge cycle on the INTA1 line in response to INT1. This errata only occurs This data sheet replaces the following data sheets: when Interrupt 1 is configured in cascade mode # 272031-002 80C186XL and a higher priority interrupt exists. This errata # 270975-002 80C188XL will not occur consistently, it is dependent on in- # 272309-001 SB80C186XL terrupt timing. # 272310-001 SB80C188XL The C step 80C186XL/80C188XL has no known er- rata. The C step can be identified by the presence of ERRATA a ``C'' or ``D'' alpha character next to the FPO num- ber. The FPO number location is shown in Figure 4. An A or B step 80C186XL/80C188XL has the follow- ing errata. The A or B step 80C186XL/80C188XL can be identified by the presence of an ``A'' or ``B'' PRODUCT IDENTIFICATION alpha character, respectively, next to the FPO num- ber. The FPO number location is shown in Figure 4. Intel 80C186XL devices are marked with a 9-charac- ter alphanumeric Intel FPO number underneath the product number. This data sheet (272431-001) is valid for devices with an ``A'', ``B'', ``C'', or ``D'' as the ninth character in the FPO number, as illustrated in Figure 4. 48