® ® Intel Pentium M Processor Datasheet April 2004 Order Number: 252612-003 Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products. Information contained herein supersedes previously published specifications on these devices from Intel. Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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HE INTEL® PENTIUM® M PROCESSOR MAY CONTAIN DESIGN DEFECTS OR ERRORS KNOWN AS ERRATA WHICH MAY CAUSE THE PRODUCT TO DEVIATE FROM T PUBLISHED SPECIFICATIONS. CURRENT CHARACTERIZED ERRATA ARE AVAILABLE ON REQUEST. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800- 548-4725 or by visiting Intel’s Website at http://www.intel.com Copyright © Intel Corporation 2000, 2001, 2002, 2003, 2004. Intel, Intel logo, Pentium, and Intel SpeedStep, and Intel Centrino are registered trademarks or trademarks of Intel Corporation and its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners. ® ® 2 Intel Pentium M Processor Datasheet Contents 1 Introduction ......................................................................................................................7 1.1 Terminology ...........................................................................................................8 1.2 References.............................................................................................................9 2 Low Power Features ......................................................................................................11 2.1 Clock Control and Low Power States...................................................................11 2.1.1 Normal State ...........................................................................................11 2.1.2 AutoHALT Powerdown State...................................................................11 2.1.3 HALT/Grant Snoop State ........................................................................12 2.1.4 Sleep State..............................................................................................12 2.1.5 Deep Sleep State....................................................................................13 2.1.6 Deeper Sleep State.................................................................................13 ® 2.2 Enhanced Intel SpeedStep Technology.............................................................13 2.3 Processor System Bus Low Power Enhancements .............................................14 2.4 Processor Power Status Indicator (PSI#) Signal..................................................15 3 Electrical Specifications................................................................................................17 3.1 System Bus and GTLREF....................................................................................17 3.2 Power and Ground Pins.......................................................................................17 3.3 Decoupling Guidelines .........................................................................................17 3.3.1 VCC Decoupling......................................................................................18 3.3.2 System Bus AGTL+ Decoupling..............................................................18 3.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking ........................18 3.4 Voltage Identification............................................................................................18 3.5 Catastrophic Thermal Protection..........................................................................20 3.6 Signal Terminations and Unused Pins.................................................................20 3.7 System Bus Signal Groups..................................................................................20 3.8 CMOS Signals .....................................................................................................21 3.9 Maximum Ratings ................................................................................................22 3.10 Processor DC Specifications................................................................................22 4 Package Mechanical Specifications and Pin Information ..........................................39 4.1 Processor Pin-Out and Pin List............................................................................47 4.2 Alphabetical Signals Reference ...........................................................................62 5 Thermal Specifications and Design Considerations ..................................................69 5.1 Thermal Specifications.........................................................................................71 5.1.1 Thermal Diode.........................................................................................71 5.1.2 Intel Thermal Monitor ..............................................................................72 6 Debug Tools Specifications ..........................................................................................75 6.1 Logic Analyzer Interface (LAI)..............................................................................75 6.1.1 Mechanical Considerations.....................................................................75 6.1.2 Electrical Considerations.........................................................................75 ® ® Intel Pentium M Processor Datasheet 3 Figures 1 Clock Control States................................................................................................................... 11 2 Illustration of Active State VCC Static and Ripple Tolerances (Highest Frequency Mode)........28 3 Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode) ....................... 30 4 Micro-FCPGA Package Top and Bottom Isometric Views ......................................................... 39 5 Micro-FCPGA Package - Top and Side Views ........................................................................... 40 6 Micro-FCPGA Package - Bottom View.......................................................................................41 7 Intel Pentium M Processor Die Offset ........................................................................................ 41 8 Micro-FCBGA Package Top and Bottom Isometric Views ......................................................... 43 9 Micro-FCBGA Package Top and Side Views ............................................................................. 44 10 Micro-FCBGA Package Bottom View .........................................................................................46 11 The Coordinates of the Processor Pins as Viewed From the Top of the Package..................... 48 ® ® 4 Intel Pentium M Processor Datasheet Tables 1 References ...................................................................................................................................9 2 Voltage Identification Definition ..................................................................................................19 3 System Bus Pin Groups..............................................................................................................21 4 Processor DC Absolute Maximum Ratings.................................................................................22 5 Voltage and Current Specifications ............................................................................................23 6 Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Active State) ....27 7 Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Deep Sleep State) ..........................................................................................................................................29 8 Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Active State) ....31 9 Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Deep Sleep State) ..........................................................................................................................................32 10 Voltage Tolerances for Low Voltage Intel Pentium M Processors (Active State) .......................33 11 Voltage Tolerances for Low Voltage Intel Pentium M Processors (Deep Sleep State) ..............34 12 Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Active State)...............35 13 Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Deep Sleep State)......36 14 System Bus Differential BCLK Specifications.............................................................................37 15 AGTL+ Signal Group DC Specifications.....................................................................................37 16 CMOS Signal Group DC Specifications......................................................................................38 17 Open Drain Signal Group DC Specifications..............................................................................38 18 Micro-FCPGA Package Dimensions...........................................................................................42 19 Micro-FCBGA Package Dimensions...........................................................................................45 20 Pin Listing by Pin Name..............................................................................................................49 21 Pin Listing by Pin Number ..........................................................................................................55 22 Signal Description.......................................................................................................................62 23 Power Specifications for the Intel Pentium M Processor............................................................70 24 Thermal Diode Interface .............................................................................................................71 25 Thermal Diode Specifications.....................................................................................................71 ® ® Intel Pentium M Processor Datasheet 5 Revision History Document Revision Description Date Number 252612 001 Initial release of datasheet March 2003 Updates include: • Added specifications for Intel Pentium M Processor 1.7 GHz, Low 252612 002 June 2003 Voltage Pentium M processor 1.2 GHz, and Ultra Low Voltage Pentium M processor 1 GHz in Table 5 and Table 23 Updates include: • Added specifications for Intel Pentium M Processor Low Voltage 252612 003 1.30 GHz, and Intel Pentium M Processor Ultra Low Voltage 1.10 March 2004 GHz in Table 5 and Table 23 • Updated DINV[3:0]# and BPM[3]# pin direction ® ® 6 Intel Pentium M Processor Datasheet Introduction 1 Introduction ® ® This document provides electrical, mechanical, and thermal specifications for the Intel Pentium M processor. The Intel Pentium M processor is offered at the following core frequencies: • 1.30 GHz • 1.40 GHz • 1.50 GHz • 1.60 GHz • 1.70 GHz The Low Voltage Intel Pentium M processor is offerred at the following core frequencies: • 1.10 GHz • 1.20 GHz • 1.30 GHz The Ultra Low Voltage Intel Pentium M processor is offered at the following core frequencies: • 900 MHz • 1.00 GHz • 1.10 GHz Key features of the Intel Pentium M processor incldue: ® • Supports Intel Architecture with Dynamic Execution • High performance, low-power core • On-die, primary 32-kB instruction cache and 32-kB write-back data cache • On-die, 1-MB second level cache with Advanced Transfer Cache Architecture • Advanced Branch Prediction and Data Prefetch Logic • Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in multimedia applications including 3D graphics, video decoding/encoding, and speech recognition. • 400-MHz, Source-Synchronous processor system bus to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). ® • Advanced Power Management features including Enhanced Intel SpeedStep technology • Micro-FCPGA and Micro-FCBGA packaging technologies • Manufactured on Intel’s advanced 0.13 micron process technology with copper interconnect. ™ • Support for MMX technology • Internet Streaming SIMD instructions and full compatibility with IA-32 software. ® ® Intel Pentium M Processor Datasheet 7 Introduction • Micro-op Fusion and Advanced Stack Management that reduce the number of micro-ops handled by the processor. • Advanced branch prediction architecture that significantly reduces the number of mispredicted branches. • Double-precision floating-point instructions enhance performance for applications that require greater range and precision, including scientific and engineering applications and advanced 3D geometry techniques, such as ray tracing. Note: The term AGTL+ has been used for Assisted Gunning Transceiver Logic technology on other Intel products. The Intel Pentium M processor is offered in two packages: a socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and a surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is referred to as the mPGA479M socket. 1.1 Terminology A “#” symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the “#” symbol implies that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level). “System Bus” refers to the interface between the processor and system core logic (also known as the chipset components). ® ® 8 Intel Pentium M Processor Datasheet Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Also, please note that “platform design guides,” when used throughout this document, ® ® refers to the following documents: Intel 855PM MHz Chipset Platform Design Guide and Intel 855GM Chipset Platform Design Guide. Table 1. References Document Order Number ® Intel 855PM Chipset Platform Design Guide http://developer.intel.com ® Intel 855PM Chipset Datasheet http://developer.intel.com ® Intel 855PM Chipset Specification Update http://developer.intel.com ® Intel 855GM Chipset Platform Design Guide http://developer.intel.com ® Intel 855GM Chipset Datasheet http://developer.intel.com ® Intel 855GM Chipset Specification Update http://developer.intel.com ® ® Intel Pentium M Processor Specification Update http://developer.intel.com  Intel Architecture Software Developer's Manual http://developer.intel.com Volume I: Basic Architecture Volume II: Instruction Set Reference Volume III: System Programming Guide ITP700 Debug Port Design Guide http://developer.intel.com NOTE: Contact your Intel representative for the latest revision and order number of this document. ® ® Intel Pentium M Processor Datasheet 9 Introduction This page intentionally left blank. ® ® 10 IIntel Pentium M Processor Datasheet Low Power Features 2 Low Power Features 2.1 Clock Control and Low Power States The Intel Pentium M processor supports the AutoHALT, Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep states for optimal power management. See Figure 1 for a visual representation of the processor low-power states. Figure 1. Clock Control States SLP# asserted STPCLK# asserted Stop Normal Sleep STPCLK# de-asserted Grant SLP# de-asserted STPCLK# halt asserted DPSLP# DPSLP# snoop break HLT snoop de-asserted asserted serviced STPCLK# instruction occurs de-asserted core voltage raised snoop HALT/ occurs Deeper Deep Auto Halt Grant Sleep Sleep Snoop snoop serviced core voltage lowered V0001-04 Halt break - A20M#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt 2.1.1 Normal State This is the normal operating state for the processor. 2.1.2 AutoHALT Powerdown State AutoHALT is a low-power state entered when the processor executes the HALT instruction. The processor transitions to the Normal state upon the occurrence of SMI#, INIT#, LINT[1:0] (NMI, INTR), or PSB interrupt message. RESET# will cause the processor to immediately initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the AutoHALT Powerdown state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for more information. The system can generate a STPCLK# while the processor is in the AutoHALT Powerdown state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state. ® ® Intel Pentium M Processor Datasheet 11 Low Power Features While in AutoHALT Powerdown state, the processor will process bus snoops. Stop-Grant State When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks after the response phase of the processor-issued Stop-Grant Acknowledge special bus cycle. Since the AGTL+ signal pins receive power from the system bus, these pins should not be driven (allowing the level to return to V ) for minimum power drawn by the termination resistors in this CCP state. In addition, all other input pins on the system bus should be driven to the inactive state. RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal. When re-entering the Stop-Grant state from the Sleep state, STPCLK# should be deasserted ten or more bus clocks after the de-assertion of SLP#. A transition to the HALT/Grant Snoop state will occur when the processor detects a snoop on the system bus (see Section 2.1.3). A transition to the Sleep state (see Section 2.1.4) will occur with the assertion of the SLP# signal. While in the Stop-Grant state, SMI#, INIT# and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal state. Only one occurrence of each event will be recognized upon return to the Normal state. While in Stop-Grant state, the processor will process snoops on the system bus and it will latch interrupts delivered on the system bus. The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# will be asserted if there is any pending interrupt latched within the processor. Pending interrupts that are blocked by the EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to system logic that it should return the processor to the Normal state 2.1.3 HALT/Grant Snoop State The processor will respond to snoop or interrupt transactions on the system bus while in Stop-Grant state or in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters the HALT/Grant Snoop state. The processor will stay in this state until the snoop on the system bus has been serviced (whether by the processor or another agent on the system bus) or the interrupt has been latched. After the snoop is serviced or the interrupt is latched, the processor will return to the Stop-Grant state or AutoHALT Power Down state, as appropriate. 2.1.4 Sleep State The Sleep state is a low power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is in the Stop-Grant state. SLP# assertions while the processor is not in the Stop-Grant state are out of specification and may result in unapproved operation. Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will cause unpredictable behavior. In the Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions or assertions of signals (with the exception of SLP#, DPSLP# or RESET#) are allowed on the system bus while the processor is in Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. ® ® 12 Intel Pentium M Processor Datasheet Low Power Features If RESET# is driven active while the processor is in the Sleep state, and held active as specified in the RESET# pin specification, then the processor will reset itself, ignoring the transition through Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the processor correctly executes the Reset sequence. While in the Sleep state, the processor is capable of entering an even lower power state, the Deep Sleep state by asserting the DPSLP# pin. (See Section 2.1.5.) While the processor is in the Sleep state, the SLP# pin must be deasserted if another asynchronous system bus event needs to occur. 2.1.5 Deep Sleep State Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings on Intel 855PM and Intel 855GM chipset-based platforms are as follows: • Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds. • Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6 BCLK periods later. To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL stabilization) must occur before the processor can be considered to be in the Sleep state. Once in the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state. While in Deep Sleep state, the processor is incapable of responding to snoop transactions or latching interrupt signals. No transitions of signals are allowed on the system bus while the processor is in Deep Sleep state. Any transition on an input signal before the processor has returned to Stop-Grant state will result in unpredictable behavior. 2.1.6 Deeper Sleep State The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer to the platform design guides for details. ® 2.2 Enhanced Intel SpeedStep Technology ® The Intel Pentium M processor features Enhanced Intel SpeedStep technology. Unlike previous implementations of Intel SpeedStep technology, this technology enables the processor to switch between multiple frequency and voltage points instead of two. This will enable superior performance with optimal power savings. Switching between states is software controlled unlike previous implementations where the GHI# pin is used to toggle between two states. The following are the key features of Enhanced Intel SpeedStep technology: • Multiple voltage/frequency operating points provide optimal performance at the lowest power. • Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model Specific Registers) thus eliminating chipset dependency. ® ® Intel Pentium M Processor Datasheet 13 Low Power Features — If the target frequency is higher than the current frequency, Vcc is ramped up by placing a new value on the VID pins and the PLL then locks to the new frequency. — If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the Vcc is changed through the VID pin mechanism. — Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until its completion. • The processor controls voltage ramp rates internally to ensure glitch free transitions. • Low transition latency and large number of transitions possible per second. — Processor core (including L2 cache) is unavailable for up to 10 µs during the frequency transition — The bus protocol (BNR# mechanism) is used to block snooping • No bus master arbiter disable required prior to transition and no processor cache flush necessary. • Improved Intel Thermal Monitor mode. — When the on-die thermal sensor indicates that the die temperature is too high, the processor can automatically perform a transition to a lower frequency/voltage specified in a software programmable MSR. — The processor waits for a fixed time period. If the die temperature is down to acceptable levels, an up transition to the previous frequency/voltage point occurs. — An interrupt is generated for the up and down Intel Thermal Monitor transitions enabling better system level thermal management. 2.3 Processor System Bus Low Power Enhancements The Intel Pentium M processor incorporates the following processor system bus low power enhancements: • Dynamic FSB power down • BPRI# control for address and control input buffers • Dynamic on-die termination disabling • Low VCCP (I/O termination voltage) The Intel Pentium M processor incorporates the DPWR# signal that controls the Data Bus input buffers on the processor. The DPWR# signal disables the buffers when not used and activates them only when data bus activity occurs, resulting in significant power savings with no performance impact. BPRI# control also allows the processor address and control input buffers to be turned off when the BPRI# signal is inactive. The On Die Termination on the processor PSB buffers is disabled when the signals are driven low, resulting in additional power savings. The low I/O termination voltage is on a dedicated voltage plane independent of the core voltage, enabling low I/ O switching power at all times. ® ® 14 Intel Pentium M Processor Datasheet Low Power Features 2.4 Processor Power Status Indicator (PSI#) Signal The Intel Pentium M processor incorporates the PSI# signal that is asserted when the processor is in a low power (Deep Sleep or Deeper Sleep) state. This signal is asserted upon Deep Sleep entry and deasserted upon exit. PSI# can be used to improve the light load efficiency of the voltage regulator, resulting in platform power savings and extended battery life. PSI# can also be used to simplify voltage regulator designs since it removes the need for integrated 100 µs timers required to mask the PWRGOOD signal during Deeper Sleep transitions. It also reduces PWRGOOD monitoring requirements in the Deeper Sleep state. ® ® Intel Pentium M Processor Datasheet 15 Low Power Features This page intentionally left blank. ® ® 16 IIntel Pentium M Processor Datasheet Electrical Specifications 3 Electrical Specifications 3.1 System Bus and GTLREF The Intel Pentium M processor system bus signals use Advanced Gunning Transceiver Logic (AGTL+) signalling technology, a variant of GTL+ signalling technology with low power enhancements. This signalling technology provides improved noise margins and reduced ringing through low-voltage swings and controlled edge rates. The termination voltage level for the Intel Pentium M processor AGTL+ signals is VCCP = 1.05 V (nominal). Due to speed improvements to data and address bus, signal integrity and platform design methods have become more critical than with previous processor families. Design guidelines for the Intel Pentium M processor system bus are detailed in the platform design guides. The AGTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board. Termination resistors are provided on the processor silicon and are terminated to its I/O voltage (VCCP). The Intel 855PM and Intel 855GM chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the system board for most AGTL+ signals. Refer to the platform design guides for board level termination resistor requirements. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the system bus, including trace lengths, is highly recommended when designing a system. 3.2 Power and Ground Pins For clean on-chip power distribution, the Intel Pentium M processor has a large number of V CC (power) and V (ground) inputs. All power pins must be connected to V power planes while all SS CC V pins must be connected to system ground planes. Use of multiple power and ground planes is SS recommended to reduce I*R drop. Please refer to the platform design guides for more details. The processor V pins must be supplied the voltage determined by the VID (Voltage ID) pins. CC 3.3 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large average current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be taken in the board design to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component. For further information and design guidelines, refer to the platform design guides. ® ® Intel Pentium M Processor Datasheet 17 Electrical Specifications 3.3.1 V Decoupling CC Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR) and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the large current swings when the part is powering on, or entering/exiting low-power states, must be provided by the voltage regulator solution. For more details on decoupling recommendations, please refer to the platform design guides. It is strongly recommended that the layout and decoupling recommendations in the design guides be followed. 3.3.2 System Bus AGTL+ Decoupling Intel Pentium M processors integrate signal termination on the die as well as incorporate high frequency decoupling capacitance on the processor package. Decoupling must also be provided by the system motherboard for proper AGTL+ bus operation. For more information, refer to the platform design guides. 3.3.3 System Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the system bus interface speed as well as the core frequency of the processor. As in previous generation processors, the Intel Pentium M processor core frequency is a multiple of the BCLK[1:0] frequency. In regards to processor clocking, the Intel Pentium M processor uses a differential clocking implementation. 3.4 Voltage Identification The Intel Pentium M processor uses six voltage identification pins, VID[5:0], to support automatic selection of power supply voltages. The VID pins for the Intel Pentium M processor are CMOS outputs driven by the processor VID circuitry. Table 2 specifies the voltage level corresponding to the state of VID[5:0]. A “1” in this refers to a high-voltage level and a “0” refers to low-voltage level. ® ® 18 Intel Pentium M Processor Datasheet Electrical Specifications Table 2. Voltage Identification Definition VID V VID V CC CC V V 5 4 3 2 1 0 5 4 321 0 00 0 0 0 0 1 0 0 0 0 0 1.196 1.708 00 0 0 1 0 1 0 0 0 1 0 1.164 1.676 00 0 0 1 1 1 0 0 0 1 1 1.148 1.660 00 0 1 0 0 1 0 0 1 0 0 1.132 1.644 00 0 1 0 1 1 0 01 01 1.116 1.628 00 0 1 1 0 1 0 0 1 1 0 1.100 1.612 00 0 1 1 1 1 0 0 1 1 1 1.084 1.596 00 1 0 0 0 1 0 1 0 0 0 1.068 1.580 00 1 0 0 1 1 0 1 0 0 1 1.052 1.564 00 1 0 1 0 1 0 1 0 1 0 1.036 1.548 00 1 0 1 1 1 0 1 0 1 1 1.020 1.532 00 1 1 0 0 1 0 1 1 0 0 1.004 1.516 00 1 1 0 1 1 0 1 1 0 1 0.988 1.500 00 1 1 1 0 1 0 1 1 1 0 0.972 1.484 00 1 1 1 1 1 0 1 1 1 1 0.956 1.468 01 0 0 0 0 1 1 0 0 0 0 0.940 1.452 01 0 0 0 1 1 1 0 0 0 1 0.924 1.436 01 0 0 1 0 1 1 0 0 1 0 0.908 1.420 01 0 0 1 1 1 1 0 0 1 1 0.892 1.404 01 0 1 0 0 1 1 0 1 0 0 0.876 1.388 01 0 1 0 1 1 1 0 1 0 1 0.860 1.372 01 0 1 1 0 1 1 0 1 1 0 0.844 1.356 0 1 0 1 1 1 1.340 1 1 0 1 1 1 0.828 0 1 1 0 0 0 1.324 1 1 1 0 0 0 0.812 0 1 1 0 0 1 1.308 1 1 1 0 0 1 0.796 0 1 1 0 1 0 1.292 1 1 1 0 1 0 0.780 0 1 1 0 1 1 1.276 1 1 1 0 1 1 0.764 0 1 1 1 0 0 1.260 1 1 1 1 0 0 0.748 0 1 1 1 0 1 1.244 1 1 1 1 0 1 0.732 0 1 1 1 1 0 1.228 1 1 1 1 1 0 0.716 0 1 1 1 1 1 1.212 1 1 1 1 1 1 0.700 ® ® Intel Pentium M Processor Datasheet 19 Electrical Specifications 3.5 Catastrophic Thermal Protection The Intel Pentium M processor supports the THERMTRIP# signal for catastrophic thermal protection. An external thermal sensor should also be used to protect the processor and the system against excessive temperatures. Even with the activation of THERMTRIP#, that halts all processor internal clocks and activity, leakage current can be high enough such that the processor cannot be protected in all conditions without the removal of power to the processor. If the external thermal sensor detects a catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP# signal is asserted, the VCC supply to the processor must be turned off within 500 ms to prevent permanent silicon damage due to thermal runaway. 3.6 Signal Terminations and Unused Pins All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V , V , or CC SS to any other signal (including each other) can result in component malfunction or incompatibility with future Intel Pentium M processors. See Section 4.2 for a pin listing of the processor and the location of all RSVD pins. For reliable operation, always connect unused inputs or bidirectional signals to an appropriate signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is provided on the processor silicon. Unused active high inputs should be connected through a resistor to ground (V ). Unused outputs can be left unconnected. SS For details on signal terminations, please refer to the platform design guides. TAP signal termination requirements are also discussed in ITP700 Debug Port Design Guide. The TEST1, TEST2, and TEST3 pins must be left unconnected but should have a stuffing option connection to V separately using 1-kΩ, pull-down resistors. SS 3.7 System Bus Signal Groups To simplify the following discussion, the system bus signals have been combined into groups by buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when driving. Table 3 identifies which signals are common clock, source synchronous, and asynchronous. Common clock signals which are dependent upon the crossing of the rising edge of BCLK0 and the falling edge of BCLK1. Source synchronous signals are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. ® ® 20 Intel Pentium M Processor Datasheet Electrical Specifications Table 3. System Bus Pin Groups Signal Group Type Signals Synchronous BPRI#, DEFER#, DPWR#, PREQ#, RESET#, RS[2:0]#, AGTL+ Common Clock Input to BCLK[1:0] TRDY# 1 Synchronous ADS#, BNR#, BPM[3:0]# , BR0#, DBSY#, DRDY#, HIT#, AGTL+ Common Clock I/O 1 to BCLK[1:0] HITM#, LOCK#, PRDY# Signals Associated Strobe REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]# Synchronous AGTL+ Source Synchronous I/O to associated D[15:0]#, DINV0# DSTBP0#, DSTBN0# strobe D[31:16]#, DINV1# DSTBP1#, DSTBN1# D[47:32]#, DINV2# DSTBP2#, DSTBN2# D[63:48]#, DINV3# DSTBP3#, DSTBN3# Synchronous AGTL+ Strobes ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# to BCLK[1:0] A20M#, DPSLP#, IGNNE#, INIT#, LINT0/INTR, LINT1/ CMOS Input Asynchronous NMI, PWRGOOD, SMI#, SLP#, STPCLK# Open Drain Output Asynchronous FERR#, IERR#, PROCHOT#, THERMTRIP# CMOS Output Asynchronous PSI#, VID[5:0] Synchronous CMOS Input TCK, TDI, TMS, TRST# to TCK Synchronous Open Drain Output TDO to TCK System Bus Clock Clock BCLK[1:0], ITP_CLK[1:0] 2 COMP[3:0], DBR# , GTLREF, RSVD, TEST3, TEST2, Power/Other TEST1, THERMDA, THERMDC, V , V [3:0], V CC CCA CCP, V [1:0], V , V V CCQ CC_SENSE SS, SS_SENSE NOTES: 1. BPM[2:0]# and PRDY# are AGTL+ output only signals. 2. In processor systems where there is no debug port implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects 3.8 CMOS Signals CMOS input signals are shown in Table 3. Legacy output FERR#, IERR# and other non-AGTL+ signals (THERMTRIP# and PROCHOT#) utilize Open Drain output buffers. All of the CMOS signals are required to be asserted for at least three BCLKs in order for the chipset to recognize them. See Section 3.10 for the DC specifications of the CMOS signal groups. ® ® Intel Pentium M Processor Datasheet 21 Electrical Specifications 3.9 Maximum Ratings Table 4 lists the processor’s maximum environmental stress ratings. The processor should not receive a clock while subjected to these conditions. Functional operating parameters are listed in the DC tables. Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor includes protective circuitry to resist damage from Electro Static Discharge (ESD), system designers must always take precautions to avoid high static voltages or electric fields. Table 4. Processor DC Absolute Maximum Ratings Symbol Parameter Min Max UnitNotes Processor storage TSTORAGE –40 85 °C 2 temperature Any processor supply V -0.3 1.75 V 1 CC voltage with respect to V SS AGTL+ buffer DC input V -0.1 1.75 V 1, 2 inAGTL+ voltage with respect to V SS CMOS buffer DC input V -0.1 1.75 V 1, 2 inAsynch_CMOS voltage with respect to V SS NOTES: 1. This rating applies to any processor pin. 2. Contact Intel for storage requirements in excess of one year. 3.10 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless noted otherwise. See Table 15 for the pin signal definitions and signal pin assignments. Most of the signals on the processor system bus are in the AGTL+ signal group and the DC specifications for these signals are also listed. DC specifications for the CMOS group are listed in Table 16. Table 5 through Table 16 list the DC specifications for the Intel Pentium M processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. The Highest Frequency (HFM) and Lowest Frequency Modes (LFM) refer to the highest and lowest core operating frequencies supported on the processor. Active Mode load line specifications apply in all states except in the Deep Sleep and Deeper Sleep states. V is the default CC,BOOT voltage driven by the voltage regulator at power up in order to set the VID values. Unless specified otherwise, all specifications for the Intel Pentium M processor are at Tjunction = 100°C. Care should be taken to read all notes associated with each parameter. ® ® 22 Intel Pentium M Processor Datasheet Electrical Specifications Table 5. Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Notes Intel Pentium M processor 1.70 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: 1.70 GHz 1.484 V CC17 V1, 2 1.40 GHz 1.308 1.20 GHz 1.228 1.00 GHz 1.116 800 MHz 1.004 600 MHz 0.956 Intel Pentium M processor 1.60 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: 1.60 GHz V 1.484 CC16 V1, 2 1.40 GHz 1.420 1.20 GHz 1.276 1.00 GHz 1.164 800 MHz 1.036 600 MHz 0.956 Intel Pentium M processor 1.50 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: 1.50 GHz 1.484 V CC15 1.40 GHz 1.452 V1, 2 1.20 GHz 1.356 1.00 GHz 1.228 800 MHz 1.116 600 MHz 0.956 Intel Pentium M processor 1.40 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: V CC14 1.40 GHz 1.484 V1, 2 1.20 GHz 1.436 1.00 GHz 1.308 800 MHz 1.180 600 MHz 0.956 Intel Pentium M processor 1.30 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: V CC13 1.30 GHz 1.388 V1, 2 1.20 GHz 1.356 1.00 GHz 1.292 800 MHz 1.260 600 MHz 0.956 ® ® Intel Pentium M Processor Datasheet 23 Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Low Voltage Intel Pentium M processor 1.30 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: 1.30 GHz 1.180 V V1,2 CCLV13 1.20 GHz 1.164 1.10 GHz 1.100 1.00 GHz 1.020 900 MHz 1.004 800 MHz 0.988 600 MHz 0.956 Low Voltage Intel Pentium M processor 1.20 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: V 1.180 V1,2 CCLV12 1.20 GHz 1.164 1.10 GHz 1.100 1.00 GHz 1.020 900 MHz 1.004 800 MHz 0.956 600 MHz Low Voltage Intel Pentium M processor 1.10 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: V C CLV11 1.180 V1, 2 1.10 GHz 1.164 1.00 GHz 1.100 900 MHz 1.020 800 MHz 0.956 600 MHz Ultra Low Voltage Intel Pentium M processor 1.10 GHz Core V for Enhanced Intel CC SpeedStep technology operating points: V CCULV11 1.004 1.10 GHz 0.988 1.00 GHz 0.972 900 MHz 0.956 800 MHz 0.844 600 MHz Ultra Low Voltage Intel Pentium M processor 1.00 GHz Core V for Enhanced Intel CC SpeedStep technology operating V points: V1, 2 CCULV10 1.004 1.00 GHz 0.988 900 MHz 0.972 800 MHz 0.844 600 MHz ® ® 24 Intel Pentium M Processor Datasheet Electrical Specifications Symbol Parameter Min Typ Max Unit Notes Ultra Low Voltage Intel Pentium M processor 900 MHz Core V for Enhanced Intel CC SpeedStep technology operating V CCULV9 points: V1, 2 1.004 900 MHz 0.988 800 MHz 0.844 600 MHz Default V Voltage for initial CC V 1.14 1.20 1.26 V 2 CC,BOOT power up V AGTL+ Termination Voltage 0.997 1.05 1.102 V 2 CCP V PLL Supply Voltage 1.71 1.8 1.89 V 2 CCA V Transient Deeper Sleep voltage 0.695 0.748 0.795 V 2 CCDPRSLP,TR V Static Deeper Sleep voltage 0.705 0.748 0.785 V 2 CCDPRSLP,ST I for Intel Pentium M processors CC I CCDES Recommended Design Target 25 A 5 I for Intel Pentium M processors CC by Frequency/Voltage: 600 MHz & 0.844 V 5 600 MHz & 0.956 V 6.8 900 MHz & 1.004 V 9 1.00 GHz & 1.004 V 9 1.10 GHz & 1.004 V 9 I A3 CC 1.10 GHz & 1.180 V 12 1.20 GHz & 1.180 V 12 1.30 GHz & 1.180 V 12.5 1.30 GHz & 1.388 V 19 1.40 GHz & 1.484 V 18 1.50 GHz & 1.484 V 21 1.60 GHz & 1.484 V 21 1.70 GHz & 1.484 V 21 I Auto-Halt & Stop-Grant at: CC 0.844 V (ULV Pentium M) 1.8 0.956 V I AH, 3.3 A4 1.004 V (ULV Pentium M) I 2.7 SGNT 1.180 V 4.7 1.388 V (Pentium M 1.30 GHz) 9.4 1.484 V 8.6 I Sleep at: CC 0.844 V (ULV Pentium M) 1.7 0.956 V 3.3 I A4 SLP 1.004 V (ULV Pentium M) 2.6 1.180 V 4.6 1.388 V (Pentium M 1.30 GHz) 9.2 1.484 V 8.4 I Deep Sleep at: CC 0.844 V (ULV Pentium M) 1.6 0.956 V 3.1 I A4 DSLP 1.004 V (ULV Pentium M) 2.3 1.180 V 4.2 1.388 V (Pentium M 1.30 GHz) 8.8 1.484 V 7.8 I I Deeper Sleep 1.8 A 4 DPRSLP CC ® ® Intel Pentium M Processor Datasheet 25 Electrical Specifications Symbol Parameter Min Typ Max Unit Notes I Deeper Sleep (ULV Intel CC I 1.2 A 4 DPRSLPULV Pentium M only) V power supply current slew CC dI 0.5 A/ns 6, 7 CC/DT rate I I for V supply 120 mA CCA CC CCA I I for V supply 2.5 A CCP CC CCP NOTES: 1. The typical values shown are the VID encoded voltages. Static and Ripple tolerances (for minimum and maximum voltages) are defined in the load line tables i.e. Table 6 through Table 13. 2. The voltage specifications are assumed to be measured at a via on the motherboard’s opposite side of the processor’s socket (or BGA) ball with a 100-MHz bandwidth oscilloscope, 1.5-pF maximum probe capacitance, and 1-Mohm minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe. 3. Specified at V (nominal) under maximum signal loading conditions. CC,STATIC 4. Specified at the VID voltage. 5. The I (max) specification comprehends future processor HFM frequencies. Platforms should be CCDES designed to this specification. 6. Based on simulations and averaged over the duration of any change in current. Specified by design/ characterization at nominal V . Not 100% tested. CC 7. Measured at the bulk capacitors on the motherboard. ® ® 26 Intel Pentium M Processor Datasheet Electrical Specifications Table 6. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Active State) Highest Frequency Mode: VID = 1.484 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 0% Offset = 0% Mode STATIC Ripple STATIC Ripple I , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0 1.484 1.462 1.506 1.452 1.516 0.0 0.956 0.942 0.970 0.932 0.980 0.9 1.481 1.459 1.503 1.449 1.513 0.4 0.955 0.941 0.969 0.931 0.979 1.9 1.478 1.456 1.501 1.446 1.511 0.7 0.954 0.940 0.968 0.930 0.978 2.8 1.476 1.453 1.498 1.443 1.508 1.1 0.953 0.938 0.967 0.928 0.977 3.7 1.473 1.451 1.495 1.441 1.505 1.4 0.952 0.937 0.966 0.927 0.976 4.6 1.470 1.448 1.492 1.438 1.502 1.8 0.951 0.936 0.965 0.926 0.975 5.6 1.467 1.445 1.490 1.435 1.500 2.1 0.950 0.935 0.964 0.925 0.974 6.5 1.465 1.442 1.487 1.432 1.497 2.5 0.948 0.934 0.963 0.924 0.973 7.4 1.462 1.440 1.484 1.430 1.494 2.9 0.947 0.933 0.962 0.923 0.972 8.3 1.459 1.437 1.481 1.427 1.491 3.2 0.946 0.932 0.961 0.922 0.971 9.3 1.456 1.434 1.478 1.424 1.488 3.6 0.945 0.931 0.960 0.921 0.970 10.2 1.453 1.431 1.476 1.421 1.486 3.9 0.944 0.930 0.959 0.920 0.969 11.1 1.451 1.428 1.473 1.418 1.483 4.3 0.943 0.929 0.957 0.919 0.967 12.0 1.448 1.426 1.470 1.416 1.480 4.7 0.942 0.928 0.956 0.918 0.966 13.0 1.445 1.423 1.467 1.413 1.477 5.0 0.941 0.927 0.955 0.917 0.965 13.9 1.442 1.420 1.465 1.410 1.475 5.4 0.940 0.926 0.954 0.916 0.964 14.8 1.440 1.417 1.462 1.407 1.472 5.7 0.939 0.924 0.953 0.914 0.963 15.7 1.437 1.415 1.459 1.405 1.469 6.1 0.938 0.923 0.952 0.913 0.962 16.7 1.434 1.412 1.456 1.402 1.466 6.4 0.937 0.922 0.951 0.912 0.961 17.6 1.431 1.409 1.453 1.399 1.463 6.8 0.936 0.921 0.950 0.911 0.960 18.5 1.428 1.406 1.451 1.396 1.461 19.4 1.426 1.403 1.448 1.393 1.458 20.4 1.423 1.401 1.445 1.391 1.455 21.3 1.420 1.398 1.442 1.388 1.452 22.2 1.417 1.395 1.440 1.385 1.450 23.1 1.415 1.392 1.437 1.382 1.447 24.1 1.412 1.390 1.434 1.380 1.444 25.0 1.409 1.387 1.431 1.377 1.441 ® ® Intel Pentium M Processor Datasheet 27 ACTIVE Electrical Specifications Figure 2. Illustration of Active State V Static and Ripple Tolerances (Highest Frequency CC Mode) Highest-Frequency Mode (VID = 1.484V): Active 1.540 1.520 1.500 1.484 1.480 1.460 1.440 1.420 1.400 1.380 1.360 0 5 10 15 20 25 Icc, A STATIC Static Min Static Max Ripple Min Ripple Max ® ® 28 Intel Pentium M Processor Datasheet Vcc, V Electrical Specifications Table 7. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.484 V (Deep Sleep State) Highest Frequency Mode: VID = 1.484 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% Offset = 1.2% Mode STATIC Ripple STATIC Ripple I , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0.0 1.466 1.444 1.488 1.434 1.498 0.0 0.945 0.930 0.959 0.920 0.969 0.5 1.465 1.442 1.487 1.432 1.497 0.2 0.944 0.930 0.958 0.920 0.968 1.0 1.463 1.441 1.485 1.431 1.495 0.4 0.943 0.929 0.958 0.919 0.968 1.6 1.462 1.439 1.484 1.429 1.494 0.6 0.943 0.928 0.957 0.918 0.967 2.1 1.460 1.438 1.482 1.428 1.492 0.8 0.942 0.928 0.956 0.918 0.966 2.6 1.458 1.436 1.481 1.426 1.491 1.0 0.941 0.927 0.956 0.917 0.966 3.1 1.457 1.435 1.479 1.425 1.489 1.2 0.941 0.926 0.955 0.916 0.965 3.6 1.455 1.433 1.478 1.423 1.488 1.4 0.940 0.926 0.955 0.916 0.965 4.2 1.454 1.431 1.476 1.421 1.486 1.7 0.940 0.925 0.954 0.915 0.964 4.7 1.452 1.430 1.474 1.420 1.484 1.9 0.939 0.925 0.953 0.915 0.963 5.2 1.451 1.428 1.473 1.418 1.483 2.1 0.938 0.924 0.953 0.914 0.963 5.7 1.449 1.427 1.471 1.417 1.481 2.3 0.938 0.923 0.952 0.913 0.962 6.2 1.447 1.425 1.470 1.415 1.480 2.5 0.937 0.923 0.951 0.913 0.961 6.8 1.446 1.424 1.468 1.414 1.478 2.7 0.936 0.922 0.951 0.912 0.961 7.3 1.444 1.422 1.467 1.412 1.477 2.9 0.936 0.922 0.950 0.912 0.960 7.8 1.443 1.421 1.465 1.411 1.475 3.1 0.936 0.921 0.950 0.911 0.960 ® ® Intel Pentium M Processor Datasheet 29 Deep Sleep Electrical Specifications Figure 3. Illustration of Deep Sleep State Voltage Tolerances (Lowest Frequency Mode) Low est-Frequency Mode (VID = 0.956V): Deep Sleep 0.980 0.970 0.960 0.950 0.940 0.94 5 0.930 0.920 0.910 0.900 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Icc, A STAT IC Static M in Static Max Ripple M in Ripple M ax ® ® 30 Intel Pentium M Processor Datasheet Vcc, V Electrical Specifications Table 8. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Active State) Highest Frequency Mode: VID = 1.388 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 0% Offset = 0% Mode STATIC Ripple STATIC Ripple V , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0 1.388 1.367 1.409 1.357 1.419 0.0 0.956 0.942 0.970 0.932 0.980 0.9 1.385 1.364 1.406 1.354 1.416 0.4 0.955 0.941 0.969 0.931 0.979 1.9 1.382 1.362 1.403 1.352 1.413 0.7 0.954 0.940 0.968 0.930 0.978 2.8 1.380 1.359 1.400 1.349 1.410 1.1 0.953 0.938 0.967 0.928 0.977 3.7 1.377 1.356 1.398 1.346 1.408 1.4 0.952 0.937 0.966 0.927 0.976 4.6 1.374 1.353 1.395 1.343 1.405 1.8 0.951 0.936 0.965 0.926 0.975 5.6 1.371 1.351 1.392 1.341 1.402 2.1 0.950 0.935 0.964 0.925 0.974 6.5 1.369 1.348 1.389 1.338 1.399 2.5 0.948 0.934 0.963 0.924 0.973 7.4 1.366 1.345 1.387 1.335 1.397 2.9 0.947 0.933 0.962 0.923 0.972 8.3 1.363 1.342 1.384 1.332 1.394 3.2 0.946 0.932 0.961 0.922 0.971 9.3 1.360 1.339 1.381 1.329 1.391 3.6 0.945 0.931 0.960 0.921 0.970 10.2 1.357 1.337 1.378 1.327 1.388 3.9 0.944 0.930 0.959 0.920 0.969 11.1 1.355 1.334 1.375 1.324 1.385 4.3 0.943 0.929 0.957 0.919 0.967 12.0 1.352 1.331 1.373 1.321 1.383 4.7 0.942 0.928 0.956 0.918 0.966 13.0 1.349 1.328 1.370 1.318 1.380 5.0 0.941 0.927 0.955 0.917 0.965 13.9 1.346 1.326 1.367 1.316 1.377 5.4 0.940 0.926 0.954 0.916 0.964 14.8 1.344 1.323 1.364 1.313 1.374 5.7 0.939 0.924 0.953 0.914 0.963 15.7 1.341 1.320 1.362 1.310 1.372 6.1 0.938 0.923 0.952 0.913 0.962 16.7 1.338 1.317 1.359 1.307 1.369 6.4 0.937 0.922 0.951 0.912 0.961 17.6 1.335 1.314 1.356 1.304 1.366 6.8 0.936 0.921 0.950 0.911 0.960 18.5 1.332 1.312 1.353 1.302 1.363 19.4 1.330 1.309 1.350 1.299 1.360 20.4 1.327 1.306 1.348 1.296 1.358 21.3 1.324 1.303 1.345 1.293 1.355 22.2 1.321 1.301 1.342 1.291 1.352 23.1 1.319 1.298 1.339 1.288 1.349 24.1 1.316 1.295 1.337 1.285 1.347 25.0 1.313 1.292 1.334 1.282 1.344 ® ® Intel Pentium M Processor Datasheet 31 ACTIVE Electrical Specifications Table 9. Voltage Tolerances for Intel Pentium M Processors with HFM VID = 1.388 V (Deep Sleep State) Highest Frequency Mode: VID =1.388 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% Offset = 1.2% Mode STATIC Ripple STATIC Ripple I , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0.0 1.371 1.351 1.392 1.341 1.402 0.0 0.945 0.930 0.959 0.920 0.969 0.6 1.370 1.349 1.390 1.339 1.400 0.2 0.944 0.930 0.958 0.920 0.968 1.2 1.368 1.347 1.389 1.337 1.399 0.4 0.943 0.929 0.958 0.919 0.968 1.8 1.366 1.345 1.387 1.335 1.397 0.6 0.943 0.928 0.957 0.918 0.967 2.3 1.364 1.343 1.385 1.333 1.395 0.8 0.942 0.928 0.956 0.918 0.966 2.9 1.363 1.342 1.383 1.332 1.393 1.0 0.941 0.927 0.956 0.917 0.966 3.5 1.361 1.340 1.382 1.330 1.392 1.2 0.941 0.926 0.955 0.916 0.965 4.1 1.359 1.338 1.380 1.328 1.390 1.4 0.940 0.926 0.955 0.916 0.965 4.7 1.357 1.336 1.378 1.326 1.388 1.7 0.940 0.925 0.954 0.915 0.964 5.3 1.356 1.335 1.376 1.325 1.386 1.9 0.939 0.925 0.953 0.915 0.963 5.9 1.354 1.333 1.375 1.323 1.385 2.1 0.938 0.924 0.953 0.914 0.963 6.5 1.352 1.331 1.373 1.321 1.383 2.3 0.938 0.923 0.952 0.913 0.962 7.0 1.350 1.329 1.371 1.319 1.381 2.5 0.937 0.923 0.951 0.913 0.961 7.6 1.348 1.328 1.369 1.318 1.379 2.7 0.936 0.922 0.951 0.912 0.961 8.2 1.347 1.326 1.368 1.316 1.378 2.9 0.936 0.922 0.950 0.912 0.960 8.8 1.345 1.324 1.366 1.314 1.376 3.1 0.936 0.921 0.950 0.911 0.960 ® ® 32 Intel Pentium M Processor Datasheet Deep Sleep Electrical Specifications Table 10. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Active State) Highest Frequency Mode: VID = 1.180 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 0% Offset = 0% Mode STATIC Ripple STATIC Ripple V , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0 1.180 1.162 1.198 1.152 1.208 0.0 0.956 0.942 0.970 0.932 0.980 0.4 1.179 1.161 1.196 1.151 1.206 0.4 0.955 0.941 0.969 0.931 0.979 0.9 1.177 1.160 1.195 1.150 1.205 0.7 0.954 0.940 0.968 0.930 0.978 1.3 1.176 1.158 1.194 1.148 1.204 1.1 0.953 0.938 0.967 0.928 0.977 1.8 1.175 1.157 1.192 1.147 1.202 1.4 0.952 0.937 0.966 0.927 0.976 2.2 1.173 1.156 1.191 1.146 1.201 1.8 0.951 0.936 0.965 0.926 0.975 2.7 1.172 1.154 1.190 1.144 1.200 2.1 0.950 0.935 0.964 0.925 0.974 3.1 1.171 1.153 1.188 1.143 1.198 2.5 0.948 0.934 0.963 0.924 0.973 3.6 1.169 1.152 1.187 1.142 1.197 2.9 0.947 0.933 0.962 0.923 0.972 4.0 1.168 1.150 1.186 1.140 1.196 3.2 0.946 0.932 0.961 0.922 0.971 4.4 1.167 1.149 1.184 1.139 1.194 3.6 0.945 0.931 0.960 0.921 0.970 4.9 1.165 1.148 1.183 1.138 1.193 3.9 0.944 0.930 0.959 0.920 0.969 5.3 1.164 1.146 1.182 1.136 1.192 4.3 0.943 0.929 0.957 0.919 0.967 5.8 1.163 1.145 1.180 1.135 1.190 4.7 0.942 0.928 0.956 0.918 0.966 6.2 1.161 1.144 1.179 1.134 1.189 5.0 0.941 0.927 0.955 0.917 0.965 6.7 1.160 1.142 1.178 1.132 1.188 5.4 0.940 0.926 0.954 0.916 0.964 7.1 1.159 1.141 1.176 1.131 1.186 5.7 0.939 0.924 0.953 0.914 0.963 7.6 1.157 1.140 1.175 1.130 1.185 6.1 0.938 0.923 0.952 0.913 0.962 8.0 1.156 1.138 1.174 1.128 1.184 6.4 0.937 0.922 0.951 0.912 0.961 8.4 1.155 1.137 1.172 1.127 1.182 6.8 0.936 0.921 0.950 0.911 0.960 8.9 1.153 1.136 1.171 1.126 1.181 9.3 1.152 1.134 1.170 1.124 1.180 9.8 1.151 1.133 1.168 1.123 1.178 10.2 1.149 1.132 1.167 1.122 1.177 10.7 1.148 1.130 1.166 1.120 1.176 11.1 1.147 1.129 1.164 1.119 1.174 11.6 1.145 1.128 1.163 1.118 1.173 12.0 1.144 1.126 1.162 1.116 1.172 ® ® Intel Pentium M Processor Datasheet 33 ACTIVE Electrical Specifications Table 11. Voltage Tolerances for Low Voltage Intel Pentium M Processors (Deep Sleep State) Highest Frequency Mode: VID = 1.180 V, Lowest Frequency Mode: VID = 0.956 V, Offset = 1.2% Offset = 1.2% Mode STATIC Ripple STATIC Ripple I , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0.0 1.166 1.148 1.184 1.138 1.194 0.0 0.945 0.930 0.959 0.920 0.969 0.3 1.165 1.147 1.183 1.137 1.193 0.2 0.944 0.930 0.958 0.920 0.968 0.6 1.164 1.146 1.182 1.136 1.192 0.4 0.943 0.929 0.958 0.919 0.968 0.8 1.163 1.146 1.181 1.136 1.191 0.6 0.943 0.928 0.957 0.918 0.967 1.1 1.162 1.145 1.180 1.135 1.190 0.8 0.942 0.928 0.956 0.918 0.966 1.4 1.162 1.144 1.179 1.134 1.189 1.0 0.941 0.927 0.956 0.917 0.966 1.7 1.161 1.143 1.179 1.133 1.189 1.2 0.941 0.926 0.955 0.916 0.965 2.0 1.160 1.142 1.178 1.132 1.188 1.4 0.940 0.926 0.955 0.916 0.965 2.2 1.159 1.141 1.177 1.131 1.187 1.7 0.940 0.925 0.954 0.915 0.964 2.5 1.158 1.141 1.176 1.131 1.186 1.9 0.939 0.925 0.953 0.915 0.963 2.8 1.157 1.140 1.175 1.130 1.185 2.1 0.938 0.924 0.953 0.914 0.963 3.1 1.157 1.139 1.174 1.129 1.184 2.3 0.938 0.923 0.952 0.913 0.962 3.4 1.156 1.138 1.173 1.128 1.183 2.5 0.937 0.923 0.951 0.913 0.961 3.6 1.155 1.137 1.173 1.127 1.183 2.7 0.936 0.922 0.951 0.912 0.961 3.9 1.154 1.136 1.172 1.126 1.182 2.9 0.936 0.922 0.950 0.912 0.960 4.2 1.153 1.136 1.171 1.126 1.181 3.1 0.936 0.921 0.950 0.911 0.960 ® ® 34 Intel Pentium M Processor Datasheet Deep Sleep Electrical Specifications Table 12. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Active State) Highest Frequency Mode: VID = 1.004 V, Lowest Frequency Mode: VID = 0.844 V, Offset = 0% Offset = 0% Mode STATIC Ripple STATIC Ripple V , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0 1.004 0.989 1.019 0.979 1.029 0.0 0.844 0.831 0.857 0.821 0.867 0.3 1.003 0.988 1.018 0.978 1.028 0.3 0.843 0.831 0.856 0.821 0.866 0.7 1.002 0.987 1.017 0.977 1.027 0.5 0.842 0.830 0.855 0.820 0.865 1.0 1.001 0.986 1.016 0.976 1.026 0.8 0.842 0.829 0.854 0.819 0.864 1.3 1.000 0.985 1.015 0.975 1.025 1.1 0.841 0.828 0.854 0.818 0.864 1.7 0.999 0.984 1.014 0.974 1.024 1.3 0.840 0.827 0.853 0.817 0.863 2.0 0.998 0.983 1.013 0.973 1.023 1.6 0.839 0.827 0.852 0.817 0.862 2.3 0.997 0.982 1.012 0.972 1.022 1.8 0.838 0.826 0.851 0.816 0.861 2.7 0.996 0.981 1.011 0.971 1.021 2.1 0.838 0.825 0.850 0.815 0.860 3.0 0.995 0.980 1.010 0.970 1.020 2.4 0.837 0.824 0.850 0.814 0.860 3.3 0.994 0.979 1.009 0.969 1.019 2.6 0.836 0.823 0.849 0.813 0.859 3.7 0.993 0.978 1.008 0.968 1.018 2.9 0.835 0.823 0.848 0.813 0.858 4.0 0.992 0.977 1.007 0.967 1.017 3.2 0.835 0.822 0.847 0.812 0.857 4.3 0.991 0.976 1.006 0.966 1.016 3.4 0.834 0.821 0.846 0.811 0.856 4.7 0.990 0.975 1.005 0.965 1.015 3.7 0.833 0.820 0.846 0.810 0.856 5.0 0.989 0.974 1.004 0.964 1.014 3.9 0.832 0.820 0.845 0.810 0.855 5.3 0.988 0.973 1.003 0.963 1.013 4.2 0.831 0.819 0.844 0.809 0.854 5.7 0.987 0.972 1.002 0.962 1.012 4.5 0.831 0.818 0.843 0.808 0.853 6.0 0.986 0.971 1.001 0.961 1.011 4.7 0.830 0.817 0.842 0.807 0.852 6.3 0.985 0.970 1.000 0.960 1.010 5.0 0.829 0.816 0.842 0.806 0.852 6.7 0.984 0.969 0.999 0.959 1.009 7.0 0.983 0.968 0.998 0.958 1.008 7.3 0.982 0.967 0.997 0.957 1.007 7.7 0.981 0.966 0.996 0.956 1.006 8.0 0.980 0.965 0.995 0.955 1.005 8.3 0.979 0.964 0.994 0.954 1.004 8.7 0.978 0.963 0.993 0.953 1.003 9.0 0.977 0.962 0.992 0.952 1.002 ® ® Intel Pentium M Processor Datasheet 35 ACTIVE Electrical Specifications Table 13. Voltage Tolerances for Ultra Low Voltage Intel Pentium M Processors (Deep Sleep State) Highest Frequency Mode: VID = 1.004 V, Lowest Frequency Mode: VID = 0.844 V, Offset = 1.2% Offset = 1.2% Mode STATIC Ripple STATIC Ripple I , A V , V I , A V , V CC CC CC CC Min Max Min Max Min Max Min Max 0.0 0.992 0.977 1.007 0.967 1.017 0.0 0.834 0.821 0.847 0.811 0.857 0.2 0.992 0.976 1.007 0.966 1.017 0.1 0.834 0.821 0.846 0.811 0.856 0.3 0.991 0.976 1.006 0.966 1.016 0.2 0.833 0.821 0.846 0.811 0.856 0.5 0.991 0.976 1.006 0.966 1.016 0.3 0.833 0.820 0.846 0.810 0.856 0.6 0.990 0.975 1.005 0.965 1.015 0.4 0.833 0.820 0.845 0.810 0.855 0.8 0.990 0.975 1.005 0.965 1.015 0.5 0.832 0.820 0.845 0.810 0.855 0.9 0.989 0.974 1.004 0.964 1.014 0.6 0.832 0.819 0.845 0.809 0.855 1.1 0.989 0.974 1.004 0.964 1.014 0.7 0.832 0.819 0.844 0.809 0.854 1.2 0.988 0.973 1.003 0.963 1.013 0.9 0.831 0.819 0.844 0.809 0.854 1.4 0.988 0.973 1.003 0.963 1.013 1.0 0.831 0.818 0.844 0.808 0.854 1.5 0.987 0.972 1.002 0.962 1.012 1.1 0.831 0.818 0.843 0.808 0.853 1.7 0.987 0.972 1.002 0.962 1.012 1.2 0.830 0.818 0.843 0.808 0.853 1.8 0.986 0.971 1.002 0.961 1.012 1.3 0.830 0.817 0.843 0.807 0.853 2.0 0.986 0.971 1.001 0.961 1.011 1.4 0.830 0.817 0.842 0.807 0.852 2.1 0.986 0.970 1.001 0.960 1.011 1.5 0.829 0.817 0.842 0.807 0.852 2.3 0.985 0.970 1.000 0.960 1.010 1.6 0.829 0.816 0.842 0.806 0.852 ® ® 36 Intel Pentium M Processor Datasheet Deep Sleep Electrical Specifications Table 14. System Bus Differential BCLK Specifications 1 Symbol Parameter Min Typ Max Unit Notes V Input Low Voltage 0 V L V Input High Voltage 0.660 0.710 0.850 V H V Crossing Voltage 0.25 0.35 0.55 V 2 CROSS Range of Crossing Points N/A N/A 0.140 V 6 ΔV CROSS V Threshold Region V -0.100 V +0.100 V 3 TH CROSS CROSS ILI Input Leakage Current ± 100 µA 4 Cpad Pad Capacitance 1.8 2.3 2.75 pF 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of BCLK1. 3. Threshold Region is defined as a region entered about the crossing voltage in which the differential receiver switches. It includes input threshold hysteresis. 4. For Vin between 0 V and V . H 5. Cpad includes die capacitance only. No package parasitics are included. 6. ΔV is defined as the total variation of all crossing voltages as defined in note 2. CROSS Table 15. AGTL+ Signal Group DC Specifications 1 Symbol Parameter Min Typ Max Unit Notes VCCP I/O Voltage 0.997 1.05 1.102 V 2/3 VCCP - 2/3 VCCP + GTLREF Reference Voltage 2/3 VCCP V5 2% 2% VIH Input High Voltage GTLREF+0.1 VCCP+0.1 V 3,5 VIL Input Low Voltage -0.1 GTLREF-0.1 V 2 VOH Output High Voltage VCCP 5 R Termination Resistance 47 55 63 Ω 6 TT RON Buffer On Resistance 17.7 24.7 32.9 W 4 ILI Input Leakage Current ± 100 µA 7 Cpad Pad Capacitance 1.8 2.3 2.75 pF 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value. 3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. 4. This is the pull down driver resistance. Measured at 0.31*VCCP. R (min) = 0.38*R R (typ) = 0.45*R ON TT, ON TT, R (max) = 0.52*R ON TT. 5. GTLREF should be generated from VCCP with a 1% tolerance resistor divider. The VCCP referred to in these specifications is the instantaneous VCCP. 6. R is the on-die termination resistance measured at V of the AGTL+ output driver. Measured at TT OL 0.31*VCCP. R is connected to VCCP on die. TT 7. Specified with on die R and R are turned off. TT ON 8. Cpad includes die capacitance only. No package parasitics are included. ® ® Intel Pentium M Processor Datasheet 37 Electrical Specifications . Table 16. CMOS Signal Group DC Specifications 1 Symbol Parameter Min Typ Max Unit Notes VCCP I/O Voltage 0.997 1.05 1.102 V Input Low Voltage VIL -0.1 0.3*VCCP V 2 CMOS VIH Input High Voltage 0.7*VCCP VCCP+0.1 V 2 VOL Output Low Voltage -0.1 0 0.1*VCCP V 2 VOH Output High Voltage 0.9*VCCP VCCP VCCP+0.1 V 2 IOL Output Low Current 1.49 4.08 mA 3 IOH Output High Current 1.49 4.08 mA 4 I Leakage Current ± 100 µA 5 LI Cpad Pad Capacitance 1.0 2.3 3.0 pF 6 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VCCP referred to in these specifications refers to instantaneous VCCP. 3. Measured at 0.1*VCCP. 4. Measured at 0.9*VCCP. 5. For Vin between 0V and VCCP. Measured when the driver is tristated. 6. Cpad includes die capacitance only. No package parasitics are included. Table 17. Open Drain Signal Group DC Specifications 1 Symbol Parameter Min Typ Max Unit Notes VOH Output High Voltage VCCP V 3 VOL Output Low Voltage 0 0.20 V IOL Output Low Current 16 50 mA 2 I Leakage Current ± 200 µA 4 LO Cpad Pad Capacitance 1.7 2.3 3.0 pF 5 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Measured at 0.2 V 3. V is determined by value of the external pullup resistor to VCCP. Please refer to the design guide for OH details. 4. For Vin between 0 V and V . OH 5. Cpad includes die capacitance only. No package parasitics are included. ® ® 38 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information 4 Package Mechanical Specifications and Pin Information The Intel Pentium M processor is available in 478-pin, Micro-FCPGA and 479-ball, Micro- FCBGA packages. The Low Voltage and Ultra Low Voltage Intel Pentium M processors are available only in the Micro-FCBGA package. Different views of the Micro-FCPGA package are shown in Figure 4 through Figure 6. Package dimensions are shown in Table 18. Different views of the Micro-FCBGA package are shown in Figure 8 through Figure 10. Package dimensions are shown in Table 19. The Intel Pentium M Processor Die Offset is illustrated in Figure 7. The Micro-FCBGA may have capacitors placed in the area surrounding the die. Because the die- side capacitors are electrically conductive, and only slightly shorter than the die height, care should be taken to avoid contacting the capacitors with electrically conductive materials. Doing so may short the capacitors, and possibly damage the device or render it inactive. The use of an insulating material between the capacitors and any thermal solution is recommended to prevent capacitor shorting. Figure 4. Micro-FCPGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA DIE LABEL TOP VIEW BOTTOM VIEW NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details. ® ® Intel Pentium M Processor Datasheet 39 Package Mechanical Specifications and Pin Information Figure 5. Micro-FCPGA Package - Top and Side Views 0. 0. 0.286 286 286 SU SUBST BSTR RA AT TE E KEEPO KEEPOU UT T Z ZO ON NE E 7 ( 7 (K K 1 1)) D DO O N NO O T T C CO ON NT T AC ACT T PA PA C CKAG KAG E E 8 pl 8 plac aces es IN INS SIID DE E T TH HIS IS L LIIN NE E 5 ( 5 (K K)) A A 4 pl 4 plac aces es 1. 1.25 M 25 MA A X X (A (A3 3) ) D1 D1 35 ( 35 (D D)) Ø Ø 0. 0.3 3 2 2 ( (B B) ) 478 pl 478 plac aces es E1 E1 A2 A2 2. 2.03 03 ± ± 0. 0.08 08 35 ( 35 (E E)) (A (A 1 1) ) P P IIN N A A1 1 CO CORN RN E ER R NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details. ® ® 40 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Figure 6. Micro-FCPGA Package - Bottom View 14 (K3) AF AE AD AC AB AA Y W V U T R P 14 (K3) N M L K J H G F E D C B A 1 3 5 7 9 11 13 15 17 19 21 23 25 25X 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26 (e) 25X 1.2 7 (e ) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 18 for details. Figure 7. Intel Pentium M Processor Die Offset (G ) D1 (F) E1 ® ® Intel Pentium M Processor Datasheet 41 Package Mechanical Specifications and Pin Information Table 18. Micro-FCPGA Package Dimensions Symbol Parameter Min Max Unit A Overall height, top of die to package seating plane 1.88 2.02 mm Overall height, top of die to PCB surface, including - socket (Refer to Note 1) 4.74 5.16 mm A1 Pin length 1.95 2.11 mm A2 Die height 0.82 mm A3 Pin-side capacitor height - 1.25 mm B Pin diameter 0.28 0.36 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.9 35.1 mm D1 Die length 10.56 mm E1 Die width 7.84 mm F To Package Substrate Center 17.5 mm G Die Offset from Package Center 1.133 mm e Pin pitch 1.27 mm K Package edge keep-out 5 mm K1 Package corner keep-out 7 mm K3 Pin-side capacitor boundary 14 mm - Pin tip radial true position <=0.254 mm N Pin count 478 each Pdie Allowable pressure on the die for thermal solution - 689 kPa W Package weight 4.5 g Package Surface Flatness 0.286 mm NOTE: Overall height with socket is based on design dimensions of the Micro-FCPGA package with no thermal solution attached. Values are based on design specifications and tolerances. This dimension is subject to change based on socket design, OEM motherboard design or OEM SMT process. ® ® 42 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Figure 8. Micro-FCBGA Package Top and Bottom Isometric Views PACKAGE KEEPOUT CAPACITOR AREA DIE LABEL TOP VIEW BOTTOM VIEW ® ® Intel Pentium M Processor Datasheet 43 Package Mechanical Specifications and Pin Information Figure 9. Micro-FCBGA Package Top and Side Views SUBSTRATE KEEPOUT ZONE 7 (K1) DO NOT CONTACT PACKAGE 8 places 0.20 INSIDE THIS LINE 5 (K) A 4 places A2 D1 35 (D) Ø 0.78 (b) 479 places E1 K2 35 (E) PIN A1 CORNER NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details. ® ® 44 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 19. Micro-FCBGA Package Dimensions Symbol Parameter Min Max Unit A Overall height, as delivered (Refer to Note 1) 2.60 2.85 mm A2 Die height 0.82 mm b Ball diameter 0.78 mm D Package substrate length 34.9 35.1 mm E Package substrate width 34.9 35.1 mm D1 Die length 10.56 mm E1 Die width 7.84 mm F To Package Substrate Center 17.5 mm G Die Offset from Package Center 1.133 mm e Ball pitch 1.27 mm K Package edge keep-out 5 mm K1 Package corner keep-out 7 mm K2 Die-side capacitor height - 0.7 mm S Package edge to first ball center 1.625 mm N Ball count 479 each - Solder ball coplanarity 0.2 mm Pdie Allowable pressure on the die for thermal solution - 689 kPa W Package weight 4.5 g NOTE: Overall height as delivered. Values are based on design specifications and tolerances. This dimension is subject to change based on OEM motherboard design or OEM SMT process. ® ® Intel Pentium M Processor Datasheet 45 Package Mechanical Specifications and Pin Information Figure 10. Micro-FCBGA Package Bottom View 1.625 (S) 4 places AF AE AD AC 1.625 (S) AB 4 places AA Y W V U T R P N M L K J H G F E D C B A 1 3 13 15 17 5 7 9 11 19 21 23 25 25X 1.27 2 4 6 8 10 12 14 16 18 20 22 24 26 (e) 25X 1.27 (e) NOTE: All dimensions in millimeters. Values shown for reference only. Refer to Table 19 for details. ® ® 46 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information 4.1 Processor Pin-Out and Pin List Figure 11 on the next page shows the top view pinout of the Intel Pentium M processor. The pin list arranged in two different formats is shown in Table 19 and Table 20. ® ® Intel Pentium M Processor Datasheet 47 Package Mechanical Specifications and Pin Information Figure 11. The Coordinates of the Processor Pins as Viewed From the Top of the Package 123456 789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 A A ITP_CLK THER ITP_CLK VSS IGNNE# IERR# VSS SLP# DBR# VSS BPM[2]# PRDY# VSS TDO TCK VSS VSS D[0]# VSS D[6]# D[2]# VSS D[4]# D[1]# VSS [1] [0] MDC B B BPM PROC THER VCCA[1] RSVD VSS SMI# INIT# VSS DPSLP# VSS PREQ# RESET# VSS TRST# BCLK1 BCLK0 VSS VSS D[7]# D[3]# VSS D[13]# D[9]# VSS D[5]# [1]# HOT# MDA C C STP BPM BPM THERM DSTBP DSTBN A20M# RSVD VSS VSS TEST1 VSS VSS TMS TDI VSS RSVD VSS TEST3 VSS DPWR# D[8]# VSS VSS D[15]# D[12]# CLK# [0]# [3]# TRIP# [0]# [0]# D D DINV LINT0 VSS FERR# LINT1 VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC VSS D[10]# VSS [0]# E E PWR PSI# VID[0] VCC VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VCC D[14]# D[11]# VSS RSVD VSS VSS GOOD F F VSS VID[1] VID[2] VSS VSS VCC VSS VCC VSS VCCP VSS VCCP VSS VCCP VSS VCCP VSS VCC VSS VCC VSS VSS D[21]# VCCA[0] VCC TEST2 G G RSVD VSS VID[3] VID[4] VCC VSS VCC VSS VSS D[22]# D[17]# VSS H H RS[0]# DRDY# VSS VID[5] VSS VCC VSS VCC D[16]# D[20]# VSS D[29]# J J DINV VSS LOCK# BPRI# VSS VCC VSS VCC VSS D[23]# VSS D[25]# [1]# K K This page intentionally left blank. DSTBN RS[1]# VSS HIT# HITM# VSS VCCP VSS VCC VSS D[31]# VSS [1]# L L DEFER# VCCP DSTBP BNR# RS[2]# VSS VSS VCCP VSS D[18]# VSS D[26]# [1]# M M VSS DBSY# TRDY# VSS VSS VCCP VSS VCCP D[24]# VSS D[28]# D[19]# N N VCCA[2] ADS# VSS BR0# VCCP VSS VCCP VSS VSS D[27]# D[30]# VSS TOP VIEW P P REQ REQ COMP COMP VSS A[3]# VSS VCCP VSS VCCP VCCQ[0] VSS [3]# [1]# [0] [1] R R REQ VSS A[6]# VSS VCCP VSS VCCP VSS D[39]# D[37]# VSS D[38]# [0]# T T REQ REQ DINV VSS A[9]# VSS VCCP VSS VCCP VSS D[34]# VSS [4]# [2]# [2]# U U ADSTB A[13]# VSS A[4]# VCC VSS VCCP VSS D[35]# VSS D[43]# D[41]# [0]# V V VSS A[7]# A[5]# VSS VSS VCC VSS VCC D[36]# D[42]# VSS D[44]# W W DSTBP DSTBN VCC A[8]# A[10]# VSS VCCQ[1] VCC VSS VSS VSS VSS [2]# [2]# Y Y A[12]# VSS A[15]# VSS VCC VSS VCC D[45]# VSS D[47]# D[32]# A[11]# AA AA VSS VSS A[16]# A[14]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS D[40]# D[33]# VSS D[46]# AB AB COMP COMP VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[50]# D[48]# VSS A[24]# VSS [3] [2] AC AC VSS A[20]# A[18]# VSS A[25]# A[19]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC D[51]# VSS D[52]# D[49]# VSS D[53]# VCCA[3] RSVD AD AD DINV VSS A[23]# A[21]# VSS A[28]# VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS VCC VSS D[60]# VSS D[54]# D[57]# VSS GTLREF A[26]# [3]# AE AE DSTBN DSTBP ADSTB VCC A[30]# A[27]# VSS A[22]# VSS VSS VCC VSS VCC VSS VCC VSS VCC VCC VSS VCC VSS D[59]# D[55]# VSS VSS VSS [3]# [3]# [1]# SENSE AF AF VSS A[31]# VSS A[29]# A[17]# VSS RSVD VCC VSS VCC VSS VCC vss VCC VSS VCC VSS VCC VSS D[58]# VSS D[62]# D[56]# VSS D[61]# D[63]# SENSE A[31]# 1234 56789 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin B2 is depopulated on the Micro-FCPGA package VSS VCC Other ® ® 48 IIntel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Name Direction Number Type Table 20. Pin Listing by Pin Name BPM[0]# C8 Common Clock Output BPM[1]# B8 Common Clock Output Pin Signal Buffer Pin Name Direction Number Type BPM[2]# A9 Common Clock Output A[3]# P4 Source Synch Input/Output BPM[3]# C9 Common Clock Input/Output A[4]# U4 Source Synch Input/Output BPRI# J3 Common Clock Input A[5]# V3 Source Synch Input/Output BR0# N4 Common Clock Input/Output A[6]# R3 Source Synch Input/Output COMP[0] P25 Power/Other Input/Output A[7]# V2 Source Synch Input/Output COMP[1] P26 Power/Other Input/Output A[8]# W1 Source Synch Input/Output COMP[2] AB2 Power/Other Input/Output A[9]# T4 Source Synch Input/Output COMP[3] AB1 Power/Other Input/Output A[10]# W2 Source Synch Input/Output D[0]# A19 Source Synch Input/Output A[11]# Y4 Source Synch Input/Output D[1]# A25 Source Synch Input/Output A[12]# Y1 Source Synch Input/Output D[2]# A22 Source Synch Input/Output A[13]# U1 Source Synch Input/Output D[3]# B21 Source Synch Input/Output A[14]# AA3 Source Synch Input/Output D[4]# A24 Source Synch Input/Output A[15]# Y3 Source Synch Input/Output D[5]# B26 Source Synch Input/Output A[16]# AA2 Source Synch Input/Output D[6]# A21 Source Synch Input/Output A[17]# AF4 Source Synch Input/Output D[7]# B20 Source Synch Input/Output A[18]# AC4 Source Synch Input/Output D[8]# C20 Source Synch Input/Output A[19]# AC7 Source Synch Input/Output D[9]# B24 Source Synch Input/Output A[20]# AC3 Source Synch Input/Output D[10]# D24 Source Synch Input/Output A[21]# AD3 Source Synch Input/Output D[11]# E24 Source Synch Input/Output A[22]# AE4 Source Synch Input/Output D[12]# C26 Source Synch Input/Output A[23]# AD2 Source Synch Input/Output D[13]# B23 Source Synch Input/Output A[24]# AB4 Source Synch Input/Output D[14]# E23 Source Synch Input/Output A[25]# AC6 Source Synch Input/Output D[15]# C25 Source Synch Input/Output A[26]# AD5 Source Synch Input/Output D[16]# H23 Source Synch Input/Output A[27]# AE2 Source Synch Input/Output D[17]# G25 Source Synch Input/Output A[28]# AD6 Source Synch Input/Output D[18]# L23 Source Synch Input/Output A[29]# AF3 Source Synch Input/Output D[19]# M26 Source Synch Input/Output A[30]# AE1 Source Synch Input/Output D[20]# H24 Source Synch Input/Output A[31]# AF1 Source Synch Input/Output D[21]# F25 Source Synch Input/Output A20M# C2 CMOS Input D[22]# G24 Source Synch Input/Output ADS# N2 Common Clock Input/Output D[23]# J23 Source Synch Input/Output ADSTB[0]# U3 Source Synch Input/Output D[24]# M23 Source Synch Input/Output ADSTB[1]# AE5 Source Synch Input/Output D[25]# J25 Source Synch Input/Output BCLK[0] B15 Bus Clock Input D[26]# L26 Source Synch Input/Output BCLK[1] B14 Bus Clock Input D[27]# N24 Source Synch Input/Output BNR# L1 Common Clock Input/Output D[28]# M25 Source Synch Input/Output ® ® Intel Pentium M Processor Datasheet 49 Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Signal Buffer Pin Name Pin Name Direction Direction Number Type Number Type D[29]# H26 Source Synch Input/Output DINV[1]# J26 Source Synch Input/Output D[30]# N25 Source Synch Input/Output DINV[2]# T24 Source Synch Input/Output D[31]# K25 Source Synch Input/Output DINV[3]# AD20 Source Synch Input/Output D[32]# Y26 Source Synch Input/Output DPSLP# B7 CMOS Input D[33]# AA24 Source Synch Input/Output DPWR# C19 Common Clock Input D[34]# T25 Source Synch Input/Output DRDY# H2 Common Clock Input/Output D[35]# U23 Source Synch Input/Output DSTBN[0]# C23 Source Synch Input/Output D[36]# V23 Source Synch Input/Output DSTBN[1]# K24 Source Synch Input/Output D[37]# R24 Source Synch Input/Output DSTBN[2]# W25 Source Synch Input/Output D[38]# R26 Source Synch Input/Output DSTBN[3]# AE24 Source Synch Input/Output D[39]# R23 Source Synch Input/Output DSTBP[0]# C22 Source Synch Input/Output D[40]# AA23 Source Synch Input/Output DSTBP[1]# L24 Source Synch Input/Output D[41]# U26 Source Synch Input/Output DSTBP[2]# W24 Source Synch Input/Output D[42]# V24 Source Synch Input/Output DSTBP[3]# AE25 Source Synch Input/Output D[43]# U25 Source Synch Input/Output FERR# D3 Open Drain Output D[44]# V26 Source Synch Input/Output GTLREF AD26 Power/Other Input D[45]# Y23 Source Synch Input/Output HIT# K3 Common Clock Input/Output D[46]# AA26 Source Synch Input/Output HITM# K4 Common Clock Input/Output D[47]# Y25 Source Synch Input/Output IERR# A4 Open Drain Output D[48]# AB25 Source Synch Input/Output IGNNE# A3 CMOS Input D[49]# AC23 Source Synch Input/Output INIT# B5 CMOS Input D[50]# AB24 Source Synch Input/Output ITP_CLK[0] A16 CMOS input D[51]# AC20 Source Synch Input/Output ITP_CLK[1] A15 CMOS input D[52]# AC22 Source Synch Input/Output LINT0 D1 CMOS Input D[53]# AC25 Source Synch Input/Output LINT1 D4 CMOS Input D[54]# AD23 Source Synch Input/Output LOCK# J2 Common Clock Input/Output D[55]# AE22 Source Synch Input/Output PRDY# A10 Common Clock Output D[56]# AF23 Source Synch Input/Output PREQ# B10 Common Clock Input D[57]# AD24 Source Synch Input/Output PROCHOT# B17 Open Drain Output D[58]# AF20 Source Synch Input/Output PSI# E1 CMOS Output D[59]# AE21 Source Synch Input/Output PWRGOOD E4 CMOS Input D[60]# AD21 Source Synch Input/Output REQ[0]# R2 Source Synch Input/Output D[61]# AF25 Source Synch Input/Output REQ[1]# P3 Source Synch Input/Output D[62]# AF22 Source Synch Input/Output REQ[2]# T2 Source Synch Input/Output D[63]# AF26 Source Synch Input/Output REQ[3]# P1 Source Synch Input/Output DBR# A7 CMOS Output REQ[4]# T1 Source Synch Input/Output DBSY# M2 Common Clock Input/Output RESET# B11 Common Clock Input DEFER# L4 Common Clock Input RS[0]# H1 Common Clock Input DINV[0]# D25 Source Synch Input/Output RS[1]# K1 Common Clock Input ® ® 50 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Signal Buffer Pin Name Pin Name Direction Direction Number Type Number Type RS[2]# L2 Common Clock Input VCC G5 Power/Other RSVD AF7 Reserved VCC G21 Power/Other RSVD B2 Reserved VCC H6 Power/Other RSVD C14 Reserved VCC H22 Power/Other RSVD C3 Reserved VCC J5 Power/Other RSVD E26 Reserved VCC J21 Power/Other RSVD G1 Reserved VCC K22 Power/Other RSVD AC1 Reserved VCC U5 Power/Other SLP# A6 CMOS Input VCC V6 Power/Other SMI# B4 CMOS Input VCC V22 Power/Other STPCLK# C6 CMOS Input VCC W5 Power/Other TCK A13 CMOS Input VCC W21 Power/Other TDI C12 CMOS Input VCC Y6 Power/Other TDO A12 Open Drain Output VCC Y22 Power/Other TEST1 C5 Test VCC AA5 Power/Other TEST2 F23 Test VCC AA7 Power/Other TEST3 C16 Test VCC AA9 Power/Other THERMDA B18 Power/Other VCC AA11 Power/Other THERMDC A18 Power/Other VCC AA13 Power/Other THERMTRIP# C17 Open Drain Output VCC AA15 Power/Other TMS C11 CMOS Input VCC AA17 Power/Other TRDY# M3 Common Clock Input VCC AA19 Power/Other TRST# B13 CMOS Input VCC AA21 Power/Other VCC D6 Power/Other VCC AB6 Power/Other VCC D8 Power/Other VCC AB8 Power/Other VCC D18 Power/Other VCC AB10 Power/Other VCC D20 Power/Other VCC AB12 Power/Other VCC D22 Power/Other VCC AB14 Power/Other VCC E5 Power/Other VCC AB16 Power/Other VCC E7 Power/Other VCC AB18 Power/Other VCC E9 Power/Other VCC AB20 Power/Other VCC E17 Power/Other VCC AB22 Power/Other VCC E19 Power/Other VCC AC9 Power/Other VCC E21 Power/Other VCC AC11 Power/Other VCC F6 Power/Other VCC AC13 Power/Other VCC F8 Power/Other VCC AC15 Power/Other VCC F18 Power/Other VCC AC17 Power/Other VCC F20 Power/Other VCC AC19 Power/Other VCC F22 Power/Other VCC AD8 Power/Other ® ® Intel Pentium M Processor Datasheet 51 Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Signal Buffer Pin Name Pin Name Direction Direction Number Type Number Type VCC AD10 Power/Other VCCP P6 Power/Other VCC AD12 Power/Other VCCP P22 Power/Other VCC AD14 Power/Other VCCP R5 Power/Other VCC AD16 Power/Other VCCP R21 Power/Other VCC AD18 Power/Other VCCP T6 Power/Other VCC AE9 Power/Other VCCP T22 Power/Other VCC AE11 Power/Other VCCP U21 Power/Other VCC AE13 Power/Other VCCQ[0] P23 Power/Other VCC AE15 Power/Other VCCQ[1] W4 Power/Other VCC AE17 Power/Other VCCSENSE AE7 Power/Other Output VCC AE19 Power/Other VID[0] E2 CMOS Output VCC AF8 Power/Other VID[1] F2 CMOS Output VCC AF10 Power/Other VID[2] F3 CMOS Output VCC AF12 Power/Other VID[3] G3 CMOS Output VCC AF14 Power/Other VID[4] G4 CMOS Output VCC AF16 Power/Other VID[5] H4 CMOS Output VCC AF18 Power/Other VSS A2 Power/Other VCCA[0] F26 Power/Other VSS A5 Power/Other VCCA[1] B1 Power/Other VSS A8 Power/Other VCCA[2] N1 Power/Other VSS A11 Power/Other VCCA[3] AC26 Power/Other VSS A14 Power/Other VCCP D10 Power/Other VSS A17 Power/Other VCCP D12 Power/Other VSS A20 Power/Other VCCP D14 Power/Other VSS A23 Power/Other VCCP D16 Power/Other VSS A26 Power/Other VCCP E11 Power/Other VSS B3 Power/Other VCCP E13 Power/Other VSS B6 Power/Other VCCP E15 Power/Other VSS B9 Power/Other VCCP F10 Power/Other VSS B12 Power/Other VCCP F12 Power/Other VSS B16 Power/Other VCCP F14 Power/Other VSS B19 Power/Other VCCP F16 Power/Other VSS B22 Power/Other VCCP K6 Power/Other VSS B25 Power/Other VCCP L5 Power/Other VSS C1 Power/Other VCCP L21 Power/Other VSS C4 Power/Other VCCP M6 Power/Other VSS C7 Power/Other VCCP M22 Power/Other VSS C10 Power/Other VCCP N5 Power/Other VSS C13 Power/Other VCCP N21 Power/Other VSS C15 Power/Other ® ® 52 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Signal Buffer Pin Name Pin Name Direction Direction Number Type Number Type VSS C18 Power/Other VSS G6 Power/Other VSS C21 Power/Other VSS G22 Power/Other VSS C24 Power/Other VSS G23 Power/Other VSS D2 Power/Other VSS G26 Power/Other VSS D5 Power/Other VSS H3 Power/Other VSS D7 Power/Other VSS H5 Power/Other VSS D9 Power/Other VSS H21 Power/Other VSS D11 Power/Other VSS H25 Power/Other VSS D13 Power/Other VSS J1 Power/Other VSS D15 Power/Other VSS J4 Power/Other VSS D17 Power/Other VSS J6 Power/Other VSS D19 Power/Other VSS J22 Power/Other VSS D21 Power/Other VSS J24 Power/Other VSS D23 Power/Other VSS K2 Power/Other VSS D26 Power/Other VSS K5 Power/Other VSS E3 Power/Other VSS K21 Power/Other VSS E6 Power/Other VSS K23 Power/Other VSS E8 Power/Other VSS K26 Power/Other VSS E10 Power/Other VSS L3 Power/Other VSS E12 Power/Other VSS L6 Power/Other VSS E14 Power/Other VSS L22 Power/Other VSS E16 Power/Other VSS L25 Power/Other VSS E18 Power/Other VSS M1 Power/Other VSS E20 Power/Other VSS M4 Power/Other VSS E22 Power/Other VSS M5 Power/Other VSS E25 Power/Other VSS M21 Power/Other VSS F1 Power/Other VSS M24 Power/Other VSS F4 Power/Other VSS N3 Power/Other VSS F5 Power/Other VSS N6 Power/Other VSS F7 Power/Other VSS N22 Power/Other VSS F9 Power/Other VSS N23 Power/Other VSS F11 Power/Other VSS N26 Power/Other VSS F13 Power/Other VSS P2 Power/Other VSS F15 Power/Other VSS P5 Power/Other VSS F17 Power/Other VSS P21 Power/Other VSS F19 Power/Other VSS P24 Power/Other VSS F21 Power/Other VSS R1 Power/Other VSS F24 Power/Other VSS R4 Power/Other VSS G2 Power/Other VSS R6 Power/Other ® ® Intel Pentium M Processor Datasheet 53 Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 20. Pin Listing by Pin Name Pin Signal Buffer Pin Signal Buffer Pin Name Pin Name Direction Direction Number Type Number Type VSS R22 Power/Other VSS AB7 Power/Other VSS R25 Power/Other VSS AB9 Power/Other VSS T3 Power/Other VSS AB11 Power/Other VSS T5 Power/Other VSS AB13 Power/Other VSS T21 Power/Other VSS AB15 Power/Other VSS T23 Power/Other VSS AB17 Power/Other VSS T26 Power/Other VSS AB19 Power/Other VSS U2 Power/Other VSS AB21 Power/Other VSS U6 Power/Other VSS AB23 Power/Other VSS U22 Power/Other VSS AB26 Power/Other VSS U24 Power/Other VSS AC2 Power/Other VSS V1 Power/Other VSS AC5 Power/Other VSS V4 Power/Other VSS AC8 Power/Other VSS V5 Power/Other VSS AC10 Power/Other VSS V21 Power/Other VSS AC12 Power/Other VSS V25 Power/Other VSS AC14 Power/Other VSS W3 Power/Other VSS AC16 Power/Other VSS W6 Power/Other VSS AC18 Power/Other VSS W22 Power/Other VSS AC21 Power/Other VSS W23 Power/Other VSS AC24 Power/Other VSS W26 Power/Other VSS AD1 Power/Other VSS Y2 Power/Other VSS AD4 Power/Other VSS Y5 Power/Other VSS AD7 Power/Other VSS Y21 Power/Other VSS AD9 Power/Other VSS Y24 Power/Other VSS AD11 Power/Other VSS AA1 Power/Other VSS AD13 Power/Other VSS AA4 Power/Other VSS AD15 Power/Other VSS AA6 Power/Other VSS AD17 Power/Other VSS AA8 Power/Other VSS AD19 Power/Other VSS AA10 Power/Other VSS AD22 Power/Other VSS AA12 Power/Other VSS AD25 Power/Other VSS AA14 Power/Other VSS AE3 Power/Other VSS AA16 Power/Other VSS AE6 Power/Other VSS AA18 Power/Other VSS AE8 Power/Other VSS AA20 Power/Other VSS AE10 Power/Other VSS AA22 Power/Other VSS AE12 Power/Other VSS AA25 Power/Other VSS AE14 Power/Other VSS AB3 Power/Other VSS AE16 Power/Other VSS AB5 Power/Other VSS AE18 Power/Other ® ® 54 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 20. Pin Listing by Pin Name Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type VSS AE20 Power/Other A23 VSS Power/Other VSS AE23 Power/Other A24 D[4]# Source Synch Input/Output VSS AE26 Power/Other A25 D[1]# Source Synch Input/Output VSS AF2 Power/Other A26 VSS Power/Other VSS AF5 Power/Other AA1 VSS Power/Other VSS AF9 Power/Other AA2 A[16]# Source Synch Input/Output VSS AF11 Power/Other AA3 A[14]# Source Synch Input/Output VSS AF13 Power/Other AA4 VSS Power/Other VSS AF15 Power/Other AA5 VCC Power/Other VSS AF17 Power/Other AA6 VSS Power/Other VSS AF19 Power/Other AA7 VCC Power/Other VSS AF21 Power/Other AA8 VSS Power/Other VSS AF24 Power/Other AA9 VCC Power/Other VSSSENSE AF6 Power/Other Output AA10 VSS Power/Other AA11 VCC Power/Other Table 21. Pin Listing by Pin Number AA12 VSS Power/Other Pin Signal Buffer AA13 VCC Power/Other Pin Name Direction Number Type AA14 VSS Power/Other A2 VSS Power/Other AA15 VCC Power/Other A3 IGNNE# CMOS Input AA16 VSS Power/Other A4 IERR# Open Drain Output AA17 VCC Power/Other A5 VSS Power/Other AA18 VSS Power/Other A6 SLP# CMOS Input AA19 VCC Power/Other A7 DBR# CMOS Output AA20 VSS Power/Other A8 VSS Power/Other AA21 VCC Power/Other A9 BPM[2]# Common Clock Output AA22 VSS Power/Other A10 PRDY# Common Clock Output AA23 D[40]# Source Synch Input/Output A11 VSS Power/Other AA24 D[33]# Source Synch Input/Output A12 TDO Open Drain Output AA25 VSS Power/Other A13 TCK CMOS Input AA26 D[46]# Source Synch Input/Output A14 VSS Power/Other AB1 COMP[3] Power/Other Input/Output A15 ITP_CLK[1] CMOS input AB2 COMP[2] Power/Other Input/Output A16 ITP_CLK[0] CMOS input AB3 VSS Power/Other A17 VSS Power/Other AB4 A[24]# Source Synch Input/Output A18 THERMDC Power/Other AB5 VSS Power/Other A19 D[0]# Source Synch Input/Output AB6 VCC Power/Other A20 VSS Power/Other AB7 VSS Power/Other A21 D[6]# Source Synch Input/Output AB8 VCC Power/Other A22 D[2]# Source Synch Input/Output AB9 VSS Power/Other ® ® Intel Pentium M Processor Datasheet 55 Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type AB10 VCC Power/Other AC23 D[49]# Source Synch Input/Output AB11 VSS Power/Other AC24 VSS Power/Other AB12 VCC Power/Other AC25 D[53]# Source Synch Input/Output AB13 VSS Power/Other AC26 VCCA[3] Power/Other AB14 VCC Power/Other AD1 VSS Power/Other AB15 VSS Power/Other AD2 A[23]# Source Synch Input/Output AB16 VCC Power/Other AD3 A[21]# Source Synch Input/Output AB17 VSS Power/Other AD4 VSS Power/Other AB18 VCC Power/Other AD5 A[26]# Source Synch Input/Output AB19 VSS Power/Other AD6 A[28]# Source Synch Input/Output AB20 VCC Power/Other AD7 VSS Power/Other AB21 VSS Power/Other AD8 VCC Power/Other AB22 VCC Power/Other AD9 VSS Power/Other AB23 VSS Power/Other AD10 VCC Power/Other AB24 D[50]# Source Synch Input/Output AD11 VSS Power/Other AB25 D[48]# Source Synch Input/Output AD12 VCC Power/Other AB26 VSS Power/Other AD13 VSS Power/Other AC1 RSVD Reserved AD14 VCC Power/Other AC2 VSS Power/Other AD15 VSS Power/Other AC3 A[20]# Source Synch Input/Output AD16 VCC Power/Other AC4 A[18]# Source Synch Input/Output AD17 VSS Power/Other AC5 VSS Power/Other AD18 VCC Power/Other AC6 A[25]# Source Synch Input/Output AD19 VSS Power/Other AC7 A[19]# Source Synch Input/Output AD20 DINV[3]# Source Synch Input/Output AC8 VSS Power/Other AD21 D[60]# Source Synch Input/Output AC9 VCC Power/Other AD22 VSS Power/Other AC10 VSS Power/Other AD23 D[54]# Source Synch Input/Output AC11 VCC Power/Other AD24 D[57]# Source Synch Input/Output AC12 VSS Power/Other AD25 VSS Power/Other AC13 VCC Power/Other AD26 GTLREF Power/Other AC14 VSS Power/Other AE1 A[30]# Source Synch Input/Output AC15 VCC Power/Other AE2 A[27]# Source Synch Input/Output AC16 VSS Power/Other AE3 VSS Power/Other AC17 VCC Power/Other AE4 A[22]# Source Synch Input/Output AC18 VSS Power/Other AE5 ADSTB[1]# Source Synch Input/Output AC19 VCC Power/Other AE6 VSS Power/Other AC20 D[51]# Source Synch Input/Output AE7 VCCSENSE Power/Other Output AC21 VSS Power/Other AE8 VSS Power/Other AC22 D[52]# Source Synch Input/Output AE9 VCC Power/Other ® ® 56 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type AE10 VSS Power/Other AF23 D[56]# Source Synch Input/Output AE11 VCC Power/Other AF24 VSS Power/Other AE12 VSS Power/Other AF25 D[61]# Source Synch Input/Output AE13 VCC Power/Other AF26 D[63]# Source Synch Input/Output AE14 VSS Power/Other B1 VCCA[1] Power/Other AE15 VCC Power/Other B2 RSVD Reserved AE16 VSS Power/Other B3 VSS Power/Other AE17 VCC Power/Other B4 SMI# CMOS Input AE18 VSS Power/Other B5 INIT# CMOS Input AE19 VCC Power/Other B6 VSS Power/Other AE20 VSS Power/Other B7 DPSLP# CMOS Input AE21 D[59]# Source Synch Input/Output B8 BPM[1]# Common Clock Output AE22 D[55]# Source Synch Input/Output B9 VSS Power/Other AE23 VSS Power/Other B10 PREQ# Common Clock Input AE24 DSTBN[3]# Source Synch Input/Output B11 RESET# Common Clock Input AE25 DSTBP[3]# Source Synch Input/Output B12 VSS Power/Other AE26 VSS Power/Other B13 TRST# CMOS Input AF1 A[31]# Source Synch Input/Output B14 BCLK[1] Bus Clock Input AF2 VSS Power/Other B15 BCLK[0] Bus Clock Input AF3 A[29]# Source Synch Input/Output B16 VSS Power/Other AF4 A[17]# Source Synch Input/Output B17 PROCHOT# Open Drain Output AF5 VSS Power/Other B18 THERMDA Power/Other AF6 VSSSENSE Power/Other Output B19 VSS Power/Other AF7 RSVD Reserved B20 D[7]# Source Synch Input/Output AF8 VCC Power/Other B21 D[3]# Source Synch Input/Output AF9 VSS Power/Other B22 VSS Power/Other AF10 VCC Power/Other B23 D[13]# Source Synch Input/Output AF11 VSS Power/Other B24 D[9]# Source Synch Input/Output AF12 VCC Power/Other B25 VSS Power/Other AF13 VSS Power/Other B26 D[5]# Source Synch Input/Output AF14 VCC Power/Other C1 VSS Power/Other AF15 VSS Power/Other C2 A20M# CMOS Input AF16 VCC Power/Other C3 RSVD Reserved AF17 VSS Power/Other C4 VSS Power/Other AF18 VCC Power/Other C5 TEST1 Test AF19 VSS Power/Other C6 STPCLK# CMOS Input AF20 D[58]# Source Synch Input/Output C7 VSS Power/Other AF21 VSS Power/Other C8 BPM[0]# Common Clock Output AF22 D[62]# Source Synch Input/Output C9 BPM[3]# Common Clock Input/Output ® ® Intel Pentium M Processor Datasheet 57 Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type C10 VSS Power/Other D23 VSS Power/Other C11 TMS CMOS Input D24 D[10]# Source Synch Input/Output C12 TDI CMOS Input D25 DINV[0]# Source Synch Input/Output C13 VSS Power/Other D26 VSS Power/Other C14 RSVD Reserved E1 PSI# CMOS Output C15 VSS Power/Other E2 VID[0] CMOS Output C16 TEST3 Test E3 VSS Power/Other C17 THERMTRIP# Open Drain Output E4 PWRGOOD CMOS Input C18 VSS Power/Other E5 VCC Power/Other C19 DPWR# Common Clock Input E6 VSS Power/Other C20 D[8]# Source Synch Input/Output E7 VCC Power/Other C21 VSS Power/Other E8 VSS Power/Other C22 DSTBP[0]# Source Synch Input/Output E9 VCC Power/Other C23 DSTBN[0]# Source Synch Input/Output E10 VSS Power/Other C24 VSS Power/Other E11 VCCP Power/Other C25 D[15]# Source Synch Input/Output E12 VSS Power/Other C26 D[12]# Source Synch Input/Output E13 VCCP Power/Other D1 LINT0 CMOS Input E14 VSS Power/Other D2 VSS Power/Other E15 VCCP Power/Other D3 FERR# Open Drain Output E16 VSS Power/Other D4 LINT1 CMOS Input E17 VCC Power/Other D5 VSS Power/Other E18 VSS Power/Other D6 VCC Power/Other E19 VCC Power/Other D7 VSS Power/Other E20 VSS Power/Other D8 VCC Power/Other E21 VCC Power/Other D9 VSS Power/Other E22 VSS Power/Other D10 VCCP Power/Other E23 D[14]# Source Synch Input/Output D11 VSS Power/Other E24 D[11]# Source Synch Input/Output D12 VCCP Power/Other E25 VSS Power/Other D13 VSS Power/Other E26 RSVD Reserved D14 VCCP Power/Other F1 VSS Power/Other D15 VSS Power/Other F2 VID[1] CMOS Output D16 VCCP Power/Other F3 VID[2] CMOS Output D17 VSS Power/Other F4 VSS Power/Other D18 VCC Power/Other F5 VSS Power/Other D19 VSS Power/Other F6 VCC Power/Other D20 VCC Power/Other F7 VSS Power/Other D21 VSS Power/Other F8 VCC Power/Other D22 VCC Power/Other F9 VSS Power/Other ® ® 58 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type F10 VCCP Power/Other H25 VSS Power/Other F11 VSS Power/Other H26 D[29]# Source Synch Input/Output F12 VCCP Power/Other J1 VSS Power/Other F13 VSS Power/Other J2 LOCK# Common Clock Input/Output F14 VCCP Power/Other J3 BPRI# Common Clock Input F15 VSS Power/Other J4 VSS Power/Other F16 VCCP Power/Other J5 VCC Power/Other F17 VSS Power/Other J6 VSS Power/Other F18 VCC Power/Other J21 VCC Power/Other F19 VSS Power/Other J22 VSS Power/Other F20 VCC Power/Other J23 D[23]# Source Synch Input/Output F21 VSS Power/Other J24 VSS Power/Other F22 VCC Power/Other J25 D[25]# Source Synch Input/Output F23 TEST2 Test J26 DINV[1]# Source Synch Input/Output F24 VSS Power/Other K1 RS[1]# Common Clock Input F25 D[21]# Source Synch Input/Output K2 VSS Power/Other F26 VCCA[0] Power/Other K3 HIT# Common Clock Input/Output G1 RSVD Reserved K4 HITM# Common Clock Input/Output G2 VSS Power/Other K5 VSS Power/Other G3 VID[3] CMOS Output K6 VCCP Power/Other G4 VID[4] CMOS Output K21 VSS Power/Other G5 VCC Power/Other K22 VCC Power/Other G6 VSS Power/Other K23 VSS Power/Other G21 VCC Power/Other K24 DSTBN[1]# Source Synch Input/Output G22 VSS Power/Other K25 D[31]# Source Synch Input/Output G23 VSS Power/Other K26 VSS Power/Other G24 D[22]# Source Synch Input/Output L1 BNR# Common Clock Input/Output G25 D[17]# Source Synch Input/Output L2 RS[2]# Common Clock Input G26 VSS Power/Other L3 VSS Power/Other H1 RS[0]# Common Clock Input L4 DEFER# Common Clock Input H2 DRDY# Common Clock Input/Output L5 VCCP Power/Other H3 VSS Power/Other L6 VSS Power/Other H4 VID[5] CMOS Output L21 VCCP Power/Other H5 VSS Power/Other L22 VSS Power/Other H6 VCC Power/Other L23 D[18]# Source Synch Input/Output H21 VSS Power/Other L24 DSTBP[1]# Source Synch Input/Output H22 VCC Power/Other L25 VSS Power/Other H23 D[16]# Source Synch Input/Output L26 D[26]# Source Synch Input/Output H24 D[20]# Source Synch Input/Output M1 VSS Power/Other ® ® Intel Pentium M Processor Datasheet 59 Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Signal Buffer Pin Name Direction Pin Name Direction Number Type Number Type M2 DBSY# Common Clock Input/Output R5 VCCP Power/Other M3 TRDY# Common Clock Input R6 VSS Power/Other M4 VSS Power/Other R21 VCCP Power/Other M5 VSS Power/Other R22 VSS Power/Other M6 VCCP Power/Other R23 D[39]# Source Synch Input/Output M21 VSS Power/Other R24 D[37]# Source Synch Input/Output M22 VCCP Power/Other R25 VSS Power/Other M23 D[24]# Source Synch Input/Output R26 D[38]# Source Synch Input/Output M24 VSS Power/Other T1 REQ[4]# Source Synch Input/Output M25 D[28]# Source Synch Input/Output T2 REQ[2]# Source Synch Input/Output M26 D[19]# Source Synch Input/Output T3 VSS Power/Other N1 VCCA[2] Power/Other T4 A[9]# Source Synch Input/Output N2 ADS# Common Clock Input/Output T5 VSS Power/Other N3 VSS Power/Other T6 VCCP Power/Other N4 BR0# Common Clock Input/Output T21 VSS Power/Other N5 VCCP Power/Other T22 VCCP Power/Other N6 VSS Power/Other T23 VSS Power/Other N21 VCCP Power/Other T24 DINV[2]# CMOS Input/Output N22 VSS Power/Other T25 D[34]# Source Synch Input/Output N23 VSS Power/Other T26 VSS Power/Other N24 D[27]# Source Synch Input/Output U1 A[13]# Source Synch Input/Output N25 D[30]# Source Synch Input/Output U2 VSS Power/Other N26 VSS Power/Other U3 ADSTB[0]# Source Synch Input/Output P1 REQ[3]# Source Synch Input/Output U4 A[4]# Source Synch Input/Output P2 VSS Power/Other U5 VCC Power/Other P3 REQ[1]# Source Synch Input/Output U6 VSS Power/Other P4 A[3]# Source Synch Input/Output U21 VCCP Power/Other P5 VSS Power/Other U22 VSS Power/Other P6 VCCP Power/Other U23 D[35]# Source Synch Input/Output P21 VSS Power/Other U24 VSS Power/Other P22 VCCP Power/Other U25 D[43]# Source Synch Input/Output P23 VCCQ[0] Power/Other U26 D[41]# Source Synch Input/Output P24 VSS Power/Other V1 VSS Power/Other P25 COMP[0] Power/Other Input/Output V2 A[7]# Source Synch Input/Output P26 COMP[1] Power/Other Input/Output V3 A[5]# Source Synch Input/Output R1 VSS Power/Other V4 VSS Power/Other R2 REQ[0]# Source Synch Input/Output V5 VSS Power/Other R3 A[6]# Source Synch Input/Output V6 VCC Power/Other R4 VSS Power/Other V21 VSS Power/Other ® ® 60 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 21. Pin Listing by Pin Number Pin Signal Buffer Pin Name Direction Number Type V22 VCC Power/Other V23 D[36]# Source Synch Input/Output V24 D[42]# Source Synch Input/Output V25 VSS Power/Other V26 D[44]# Source Synch Input/Output W1 A[8]# Source Synch Input/Output W2 A[10]# Source Synch Input/Output W3 VSS Power/Other W4 VCCQ[1] Power/Other W5 VCC Power/Other W6 VSS Power/Other W21 VCC Power/Other W22 VSS Power/Other W23 VSS Power/Other W24 DSTBP[2]# Source Synch Input/Output W25 DSTBN[2]# Source Synch Input/Output W26 VSS Power/Other Y1 A[12]# Source Synch Input/Output Y2 VSS Power/Other Y3 A[15]# Source Synch Input/Output Y4 A[11]# Source Synch Input/Output Y5 VSS Power/Other Y6 VCC Power/Other Y21 VSS Power/Other Y22 VCC Power/Other Y23 D[45]# Source Synch Input/Output Y24 VSS Power/Other Y25 D[47]# Source Synch Input/Output Y26 D[32]# Source Synch Input/Output ® ® Intel Pentium M Processor Datasheet 61 Package Mechanical Specifications and Pin Information 4.2 Alphabetical Signals Reference Table 22. Signal Description (Sheet 1 of 7) Name Type Description 32 A[31:3]# (Address) define a 2 -byte physical memory address space. In sub- phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals Input/ A[31:3]# must connect the appropriate pins of both agents on the Intel Pentium M Output processor system bus. A[31:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. Address signals are used as straps which are sampled before RESET# is deasserted. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# A20M# Input is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[31:3]# and REQ[4:0]# pins. All bus agents observe the ADS# Input/ ADS# activation to begin parity checking, protocol checking, address decode, internal Output snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[31:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Input/ Signals Associated Strobe ADSTB[1:0]# Output REQ[4:0]#, A[16:3]# ADSTB[0]# A[31:17]# ADSTB[1]# The differential pair BCLK (Bus Clock) determines the system bus frequency. All BCLK[1:0] Input processor system bus agents must receive these signals to drive their outputs and latch their inputs. BNR# (Block Next Request) is used to assert a bus stall by any bus agent that is Input/ BNR# unable to accept new bus transactions. During a bus stall, the current bus owner Output cannot issue any new transactions. BPM[3:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor BPM[2:0]# Output performance. BPM[3:0]# should connect the appropriate pins of all Intel Pentium M processor system bus agents.This includes debug or performance monitoring BPM[3] Input/ tools. Output Please refer to the platform design guides and ITP700 Debug Port Design Guide for more detailed information. BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of both processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes the BPRI# Input other agent to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. BR0# is used by the processor to request the bus. The arbitration is done Input/ BR0# between the Intel Pentium M processor (Symmetric Agent) and the MCH-M Output (High Priority Agent) of the Intel 855PM or Intel 855GM chipset. ® ® 62 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 2 of 7) Name Type Description COMP[3:0] must be terminated on the system board using precision (1% COMP[3:0] Analog tolerance) resistors. Refer to the platform design guides for more implementation details. D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on both agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DINV#. Quad-Pumped Signal Groups Input/ DSTBN#/ D[63:0]# Data Group DINV# Output DSTBP# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]# 3 3 Furthermore, the DINV# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DINV# signal. When the DINV# signal is active, the corresponding data group is inverted and therefore sampled active high. DBR# (Data Bus Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer DBR# Output so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect. DBR# is not a processor signal. DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on Input/ the processor system bus to indicate that the data bus is in use. The data bus is DBSY# Output released after DBSY# is deasserted. This signal must connect the appropriate pins on both processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the DEFER# Input responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of both processor system bus agents. DINV[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals. The DINV[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DINV[3:0]# Assignment To Data Bus Input/ DINV[3:0]# Bus Signal Data Bus Signals Output DINV[3]# D[63:48]# DINV[2]# D[47:32]# DINV[1]# D[31:16]# DINV[0]# D[15:0]# ® ® Intel Pentium M Processor Datasheet 63 Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 3 of 7) Name Type Description DPSLP# when asserted on the platform causes the processor to transition from the Sleep state to the Deep Sleep state. In order to return to the Sleep state, DPSLP# Input DPSLP# must be deasserted. DPSLP# is driven by the ICH4-M component and also connects to the MCH-M component of the Intel 855PM or Intel 855GM chipset. DPWR# is a control signal from the Intel 855PM and Intel 855GM chipsets used DPWR# Input to reduce power on the Intel Pentium M data bus input buffers. DRDY# (Data Ready) is asserted by the data driver on each data transfer, Input/ indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# Output DRDY# may be deasserted to insert idle clocks. This signal must connect the appropriate pins of both processor system bus agents. Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBN[0]# Input/ DSTBN[3:0]# Output D[31:16]#, DINV[1]# DSTBN[1]# D[47:32]#, DINV[2]# DSTBN[2]# D[63:48]#, DINV[3]# DSTBN[3]# Data strobe used to latch in D[63:0]#. Signals Associated Strobe D[15:0]#, DINV[0]# DSTBP[0]# Input/ DSTBP[3:0]# Output D[31:16]#, DINV[1]# DSTBP[1]# D[47:32]#, DINV[2]# DSTBP[2]# D[63:48]#, DINV[3]# DSTBP[3]# FERR# (Floating-point Error)/PBE#(Pending Break Event) is a multiplexed signal and its meaning is qualified by STPCLK#. When STPCLK# is not asserted, FERR#/PBE# indicates a floating point when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 80387 coprocessor, and is included for compatibility with systems using MS-DOS* type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state. When FERR#/PBE# is FERR#/PBE# Output asserted, indicating a break event, it will remain asserted until STPCLK# is deasserted. Assertion of PREQ# when STPCLK# is active will also cause an FERR# break event. For additional information on the pending break event functionality, including identification of support for the feature and enable/disable  information, refer to Volume 3 of the Intel Architecture Software Developer’s  Manual and the Intel Processor Identification and CPUID Instruction application note. For termination requirements please refer to the platform design guides. GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 V . GTLREF is used by the AGTL+ receivers to determine CCP GTLREF Input if a signal is a logical 0 or logical 1. Please refer to the platform design guides for details on GTLREF implementation. ® ® 64 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 4 of 7) Name Type Description Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation HIT# Output results. Either system bus agent may assert both HIT# and HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HITM# Input/ HIT# and HITM# together. Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an IERR# Output external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. For termination requirements please refer to the platform design guides. IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# Input IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power on Reset vector configured during power on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output Write instruction, it must be valid along with INIT# Input the TRDY# assertion of the corresponding Input/Output Write bus transaction. INIT# must connect the appropriate pins of both processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST) For termination requirements please refer to the platform design guides. ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are ITP_CLK[1:0] Input used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects. These are not processor signals. LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. LINT[1:0] Input Both of these signals must be software configured using BIOS programming of the APIC register space and used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins of both processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. Input/ LOCK# Output When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. ® ® Intel Pentium M Processor Datasheet 65 Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 5 of 7) Name Type Description Probe Ready signal used by debug tools to determine processor debug readiness. PRDY# Output Please refer to the ITP700 Debug Port Design Guide and the platform design guides for more implementation details. Probe Request signal used by debug tools to request debug operation of the processor. PREQ# Input Please refer to the ITP700 Debug Port Design Guide and the platform design guides for more implementation details. PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. See Chapter 5 for more details. PROCHOT# Output For termination requirements please refer to the platform design guides. This signal may require voltage translation on the motherboard. Please refer to the platform design guides for more details. Processor Power Status Indicator signal. This signal is asserted when the PSI# Output processor is in a lower state (Deep Sleep and Deeper Sleep). See Section 2.1.3 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal as a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at PWRGOOD Input any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout the boundary scan operation. For termination requirements please refer to the platform design guides. REQ[4:0]# (Request Command) must connect the appropriate pins of both Input/ processor system bus agents. They are asserted by the current bus owner to REQ[4:0]# Output define the currently active transaction type. These signals are source synchronous to ADSTB[0]#. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least two milliseconds after VCC and BCLK have reached their proper specifications. On observing active RESET#, both system bus agents will deassert their outputs within two clocks. RESET# Input All processor straps must be valid within the specified setup time before RESET# is deasserted. Please refer to the ITP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details. There is a 55 ohm (nominal) on die pullup resistor on this signal. RS[2:0]# (Response Status) are driven by the response agent (the agent RS[2:0]# Input responsible for completion of the current transaction), and must connect the appropriate pins of both processor system bus agents. These pins are RESERVED and must be left unconnected on the board. Reserved/ However, it is recommended that routing channels to these pins on the board be RSVD No kept open for possible future use. Please refer to the platform design guides for Connect more details. ® ® 66 Intel Pentium M Processor Datasheet Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 6 of 7) Name Type Description SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and SLP# Input removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If DPSLP# is asserted while in the Sleep state, the processor will exit the Sleep state and transition to the Deep Sleep state. SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution SMI# Input from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus STPCLK# Input transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). TCK Input Please refer to the ITP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details. TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDI Input Please refer to the ITP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TDO Output Please refer to the ITP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details. TEST1, TEST1, TEST2, and TEST3 must be left unconnected but should have a stuffing TEST2, Input option connection to V separately using 1-k, pull-down resistors. Please refer SS TEST3 to the platform design guides for more details. THERMDA Other Thermal Diode Anode. THERMDC Other Thermal Diode Cathode. The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when THERMTRIP# Output the junction temperature exceeds approximately 125°C. This is signalled to the system by the THERMTRIP# (Thermal Trip) pin. For termination requirements please refer to the platform design guides. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TMS Input Please refer to the ITP700 Debug Port Design Guide and the platform design guides for termination requirements and implementation details. ® ® Intel Pentium M Processor Datasheet 67 Package Mechanical Specifications and Pin Information Table 22. Signal Description (Sheet 7 of 7) Name Type Description TRDY# (Target Ready) is asserted by the target to indicate that it is ready to TRDY# Input receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of both system bus agents. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Please refer to the ITP700 Debug Port TRST# Input Design Guide and the platform design guides for termination requirements and implementation details. V Input Processor core power supply. CC V provides isolated power for the internal processor core PLL’s. Refer to the CCA [3:0] Input V CCA platform design guides for complete implementation details. V Input Processor I/O Power Supply. CCP Quiet power supply for on die COMP circuitry. These pins should be connected V [1:0] Input to V on the motherboard. However, these connections should enable addition CCQ CCP of decoupling on the V lines if necessary. CCQ V is an isolated low impedance connection to processor core power CCSENSE (V ). It can be used to sense or measure power near the silicon with little noise. CC Output V CCSENSE Please refer to the platform design guides for termination recommendations and more details. VID[5:0] (Voltage ID) pins are used to support automatic selection of power supply voltages (Vcc). Unlike some previous generations of processors, these are CMOS signals that are driven by the Intel Pentium M processor. The voltage supply for these pins must be valid before the VR can supply Vcc to the VID[5:0] Output processor. Conversely, the VR output must be disabled until the voltage supply for the VID pins becomes valid. The VID pins are needed to support the processor voltage specification variations. See Table 3 for definitions of these pins. The VR must supply the voltage that is requested by the pins, or disable itself. V is an isolated low impedance connection to processor core V . It can SSSENSE SS be used to sense or measure ground near the silicon with little noise. Please Output V SSSENSE refer to the platform design guides for termination recommendations and more details. ® ® 68 Intel Pentium M Processor Datasheet Thermal Specifications and Design Considerations 5 Thermal Specifications and Design Considerations The Intel Pentium M processor requires a thermal solution to maintain temperatures within operating limits. A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions include active or passive heatsinks or heat exchangers attached to the processor exposed die. The solution should make firm contact with the die while maintaining processor mechanical specifications such as pressure. A typical system level thermal solution may consist of a processor fan ducted to a heat exchanger that is thermally coupled to the processor using a heat pipe or direct die attachment. A secondary fan or air from the processor fan may also be used to cool other platform components or lower the internal ambient temperature within the system. The processor must remain within the minimum and maximum junction temperature (Tj) specifications at the corresponding Thermal Design Power (TDP) value listed in Table 23. The maximum junction temperature is defined by an activation of the processor Intel Thermal Monitor. Refer to Section 5.1.2 for more details. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP) indicated in Table 23. The Intel Thermal Monitor feature is designed to help protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained period of time. For more details on the usage of this feature, refer to Section 5.1.2. In all cases the Intel Thermal Monitor feature must be enabled for the processor to remain within specification. ® ® Intel Pentium M Processor Datasheet 69 Thermal Specifications and Design Considerations Table 23. Power Specifications for the Intel Pentium M Processor Core Frequency Symbol Thermal Design Power Unit Notes & Voltage 1.70 GHz & 1.484 V 24.5 1.60 GHz & 1.484 V 24.5 1.50 GHz & 1.484 V 24.5 1.40 GHz & 1.484 V 22 1.30 GHz & 1.388 V 22 1.30 GHz & 1.180 V 12 TDP 1.20 GHz & 1.180 V 12 W At 100°C, Notes 1, 4 1.10 GHz & 1.180 V 12 1.10 GHz & 1.004 V 7 1.00 GHz & 1.004 V 7 900 MHz & 1.004V 7 600 MHz & 0.956 V 6 600 MHz & 0.844 V 4 Symbol Parameter Min Typ Max Unit Notes Auto Halt, Stop-Grant Power at: 1.484 V 7.3 1.388 V (Pentium M 1.30 GHz) P 7.3 AH, 1.180 V W At 50°C, Note 2 P 3.2 SGNT 1.004 V (ULV Pentium M) 1.7 0.956 V 1.8 0.844 V (ULV Pentium M) 0.9 Sleep Power at: 1.484 V 7.0 1.388 V (Pentium M 1.30 GHz) 7.0 P 1.180 V 3.0 W At 50°C, Note 2 SLP 1.004 V (ULV Pentium M) 1.5 0.956 V 1.7 0.844 V (ULV Pentium M) 0.8 Deep Sleep Power at: 1.484 V 5.1 1.388 V (Pentium M 1.30 GHz) 5.4 P 1.180 V 2.2 W At 35°C, Note 2 DSLP 1.004 V (ULV Pentium M) 1.0 0.956 V 1.1 0.844 V (ULV Pentium M) 0.55 P Deeper Sleep Power 0.55 W At 35°C, Note 2 DPRSLP P Deeper Sleep Power (ULV DPRSLP 0.37 W At 35°C, Note 2 Pentium M only) ULV T Junction Temperature 0 100 °C Notes 3, 4 J NOTES: 1. The Thermal Design Power (TDP) specification should be used to design the processor thermal solution. The TDP is not the maximum theoretical power the processor can dissipate. ® ® 70 Intel Pentium M Processor Datasheet Thermal Specifications and Design Considerations 2. Not 100% tested. These power specifications are determined by characterization of the processor currents at higher temperatures and extrapolating the values for the temperature indicated. 3. As measured by the on-die Intel Thermal Monitor. The Intel Thermal Monitor’s automatic mode is used to indicate that the maximum T has been reached. Refer to Section 5.1 for more details. J 4. The Intel Thermal Monitor automatic mode must be enabled for the processor to operate within specifications. 5.1 Thermal Specifications 5.1.1 Thermal Diode The Intel Pentium M processor incorporates two methods of monitoring die temperature, the Intel Thermal Monitor and the thermal diode. The Intel Thermal Monitor (detailed in Section 5.1) must be used to determine when the maximum specified processor junction temperature has been reached. The second method, the thermal diode, can be read by an off-die analog/digital converter (a thermal sensor) located on the motherboard, or a stand-alone measurement kit. The thermal diode may be used to monitor the die temperature of the processor for thermal management or instrumentation purposes but cannot be used to indicate that the maximum T of the processor has J been reached. Please see Section 5.1.2 for thermal diode usage recommendation when the PROCHOT# signal is not asserted. Table 24 and Table 25 provide the diode interface and specifications. Note: The reading of the external thermal sensor (on the motherboard) connected to the processor thermal diode signals, will not necessarily reflect the temperature of the hottest location on the die. This is due to inaccuracies in the external thermal sensor, on-die temperature gradients between the location of the thermal diode and the hottest location on the die, and time based variations in the die temperature measurement. Time based variations can occur when the sampling rate of the thermal diode (by the thermal sensor) is slower than the rate at which the T temperature can change. J The offset between the thermal diode based temperature reading and the Intel Thermal Monitor reading can be characterized using the Intel Thermal Monitor’s automatic mode activation of the thermal control circuit. This temperature offset must be taken into account when using the processor thermal diode to implement power management events. Table 24. Thermal Diode Interface Signal Name Pin/Ball Number Signal Description THERMDA B18 Thermal diode anode THERMDC A18 Thermal diode cathode Table 25. Thermal Diode Specifications Symbol Parameter Min Typ Max Unit Notes I Forward Bias Current 5 300 µA Note 1 FW n Diode Ideality Factor 1.00151 1.00220 1.00289 Notes 2, 3, 4 R Series Resistance 3.06 ohms 2, 3, 5 T NOTES: ® ® Intel Pentium M Processor Datasheet 71 Thermal Specifications and Design Considerations 1. Intel does not support or recommend operation of the thermal diode under reverse bias. Intel does not support or recommend operation of the thermal diode when the processor power supplies are not within their specified tolerance range. 2. Characterized at 100°C. 3. Not 100% tested. Specified by design/characterization. 4. The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation: (qVD/nkT) I =I *(e -1) FW s Where I = saturation current, q = electronic charge, V = voltage across the diode, k = Boltzmann Constant, S D and T = absolute temperature (Kelvin). 5. The series resistance, R , is provided to allow for a more accurate measurement of the diode junction T temperature. R as defined, includes the pins of the processor but does not include any socket resistance or T board trace resistance between the socket and the external remote diode thermal sensor. R can be used by T remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: T = [R *(N-1)*I ]/[(no/q)*ln N] error T FWmin 5.1.2 Intel Thermal Monitor The Intel Thermal Monitor helps control the processor temperature by activating the TCC when the processor silicon reaches its maximum operating temperature. The temperature at which the Intel Thermal Monitor activates the thermal control circuit (TCC) is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would not be detectable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under designed may not be capable of cooling the processor even when the TCC is active continuously. The Intel Thermal Monitor controls the processor temperature by modulating (starting and ® stopping) the processor core clocks or by initiating an Enhanced Intel SpeedStep technology transition when the processor silicon reaches its maximum operating temperature. The Intel Thermal Monitor uses two modes to activate the TCC: Automatic mode and On-Demand mode. If both modes are activated, Automatic mode takes precedence. The Intel Thermal Monitor Automatic Mode must be enabled via BIOS for the processor to be operating within specifications.There are two Automatic modes called Intel Thermal Monitor 1 and Intel Thermal Monitor 2. These modes are selected by writing values to the Model Specific Registers (MSRs) of the processor. After Automatic mode is enabled, the TCC will activate only when the internal die temperature reaches the maximum allowed value for operation. Likewise, when Intel Thermal Monitor 2 is enabled, and a high temperature situation exists, the processor will perform an Enhanced Intel SpeedStep technology transition to a lower operating point. When the processor temperature drops below the critical level, the processor will make an Enhanced Intel SpeedStep technology transition to the last requested operating point. Intel Thermal Monitor 2 is the recommended mode on the Intel Pentium M processor. If a processor load-based Enhanced Intel SpeedStep technology transition (through MSR write) is initiated when an Intel Thermal Monitor 2 period is active, there are two possible results: 1.If the processor load based Enhanced Intel SpeedStep technology transition target frequency is higher than the Intel Thermal Monitor 2 transition based target frequency, the processor load-based transition will be deferred until the Intel Thermal Monitor 2 event has been completed. ® ® 72 Intel Pentium M Processor Datasheet Thermal Specifications and Design Considerations 2.If the processor load-based Enhanced Intel SpeedStep technology transition target frequency is lower than the Intel Thermal Monitor 2 transition based target frequency, the processor will transition to the processor load-based Enhanced Intel SpeedStep technology target frequency point. When Intel Thermal Monitor 1 is enabled, and a high temperature situation exists, the clocks will be modulated by alternately turning the clocks off and on at a 50% duty cycle. Cycle times are processor speed dependent and will decrease linearly as processor core frequencies increase. After the temperature has returned to a non-critical level, modulation ceases and the TCC goes inactive. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the trip point. The duty cycle is factory configured and cannot be modified. Also, Automatic mode does not require any additional hardware, software drivers or interrupt handling routines. Processor performance will be decreased by the same amount as the duty cycle when the TCC is active, however, with a properly designed and characterized thermal solution the TCC most likely will never be activated, or will be activated only briefly during the most power intensive applications. The TCC may also be activated using On-Demand mode. If bit 4 of the ACPI Intel Thermal Monitor Control Register is written to a "1", the TCC will be activated immediately, independent of the processor temperature. When using On-Demand mode to activate the TCC, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI Intel Thermal Monitor Control Register. In Automatic mode, the duty cycle is fixed at 50% on, 50% off, in On-Demand mode, the duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode can be used at the same time Automatic mode is enabled, however, if the system tries to enable the TCC via On-Demand mode at the same time Automatic mode is enabled and a high temperature condition exists, Automatic mode will take precedence. An external signal, PROCHOT# (processor hot) is asserted when the processor detects that its temperature is above the thermal trip point. Bus snooping and interrupt latching are also active while the TCC is active. Note: PROCHOT# will not be asserted when the processor is in the Stop-Grant, Sleep, Deep Sleep, and Deeper Sleep low power states (internal clocks stopped), hence the thermal diode reading must be used as a safeguard to maintain the processor junction temperature within the 100 °C (maximum) specification. If the platform thermal solution is not able to maintain the processor junction temperature within the maximum specification, the system must initiate an orderly shutdown to prevent damage. If the processor enters one of the above low power states with PROCHOT# already asserted, PROCHOT# will remain asserted until the processor exits the low power state and the processor junction temperature drops below the thermal trip point. If Automatic mode is disabled the processor will be operating out of specification. Whether the automatic or On-Demand modes are enabled or not, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature of approximately 125 °C. At this point the system bus signal THERMTRIP# will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles. When THERMTRIP# is asserted, the processor core voltage must be shut down within the time specified in Chapter 3. ® ® Intel Pentium M Processor Datasheet 73 Thermal Specifications and Design Considerations This page intentionally left blank. ® ® 74 IIntel Pentium M Processor Datasheet Debug Tools Specifications 6 Debug Tools Specifications Please refer to the ITP700 Debug Port Design Guide and the platform design guides for information regarding debug tools specifications. 6.1 Logic Analyzer Interface (LAI) Intel is working with logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in debugging Intel Pentium M processor systems. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor. Due to the complexity of Intel Pentium M processor systems, the LAI is critical in providing the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind when designing an Intel Pentium M processor system that can make use of an LAI: mechanical and electrical. 6.1.1 Mechanical Considerations The LAI is installed between the processor socket and the Intel Pentium M processor. The LAI pins plug into the socket, while the Intel Pentium M processor pins plug into a socket on the LAI. Cabling that is part of the LAI egresses the system to allow an electrical connection between the Intel Pentium M processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. 6.1.2 Electrical Considerations The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution they provide. ® ® Intel Pentium M Processor Datasheet 75