82562ET 10/100 Mbps Platform LAN Connect (PLC) Networking Silicon Datasheet Product Features ■ IEEE 802.3 10BASE-T/100BASE-TX ■ Diagnostic loopback mode compliant physical layer interface ■ 1:1 transmit transformer ratio support ■ IEEE 802.3u Auto-Negotiation support ■ Low power (less than 300 mW in active ■ Digital Adaptive Equalization control transmit mode) ■ Link status interrupt capability ■ Reduced power in “unplugged mode” (less than 50 mW) ■ XOR tree mode support ■ Automatic detection of “unplugged mode” ■ 3-port LED support (speed, link and activity) ■ 3.3 V device ■ 10BASE-T auto-polarity correction ■ 48-pin Shrink Small Outline Package ■ LAN Connect Interface Revision 1.4 November 2006 Revision History Revision Revision Date Description 0.55 Sept. 1999 Initial release. 0.6 Nov. 1999 • Corrected Figure 4 “NRZ to MLT-3 Encoding Diagram on Pg. 11 to reflect correct signal transitions.  Removed “10BASE-T Error Detection and Reporting” section since the 82562 does not do 10BASE-T error reporting.  Updated bit 13 of Table 3 “Register 16 (10 Hexadecimal): PLC Status, Con- trol and Address Data” to reflect correct values. 1.0 May 2000 Advance Information Datasheet release (Intel Secret).  Modified Table 1 “82562ET Hardware Configuration” to add one row for XOR Tree and include column for comments.  Updated the descrition of the Activity LED signal in Section 3.6, “LED Pins”.  Revised Section 3.7, “Miscellaneous Control Pins” to reflect references to Table 1 “82562ET Hardware Configuration”.  Updated Section 6.0, “Electrical and Timing Specifications”.  Replaced diagrams in Section 7.1, “Package Information”. 1.1 June 2000 Advance Information Datasheet release (Intel Confidential).  On cover page, replaced Boundary Scan Support with XOR tree mode support. Added bullet for LAN Connect I/F.  Pg. 3, added a Solution Block Diagram as included in OR-2338 Pg. 4 but replaced EM with ET in diagram.  Pg. 11, removed Figure 4, “NRZ to MLT-3 Encoding Diagram”.  Pg. 35, changed the Rev. number on the 82562 Pinout symbol to 1.0. 1.2 Oct 2001 Removed confidential status.  Removed sections: “Physical Layer Interface Functionality” and “Platform LAN Connect”.  Changed “Electrical and Timing Specifications” section to “Voltage and Temperature Specifications” and removed timing specifications. 1.3 March 2003  Added product ordering code in Section 1.0. 1.4 Nov 2006  Corrected the TESTEN signal description. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. 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The 82562ET PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © 2006, Intel Corporation Intel® is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries. * Other brands and names are the property of their respective owners. Datasheet Networking Silicon — 82562ET Contents 1.0 Introduction.........................................................................................................................1 1.1 Overview ...............................................................................................................1 1.2 Features ................................................................................................................1 1.3 References ............................................................................................................1 1.4 Product Code ........................................................................................................2 2.0 82562ET Architectural Overview........................................................................................3 3.0 82562ET Signal Descriptions.............................................................................................5 3.1 Signal Type Definitions .........................................................................................5 3.2 Twisted Pair Ethernet (TPE) Pins .........................................................................5 3.3 External Bias Pins ................................................................................................5 3.4 Clock Pins ............................................................................................................6 3.5 Platform LAN Connect Interface Pins....................................................................6 3.6 LED Pins ..............................................................................................................7 3.7 Miscellaneous Control Pins ..................................................................................7 3.8 Power and Ground Connections ..........................................................................8 4.0 Physical Layer Interface Functionality................................................................................9 4.1 100BASE-TX Mode...............................................................................................9 4.1.1 100BASE-TX Transmit Blocks .................................................................9 4.1.2 100BASE-TX Receive Blocks ................................................................11 4.2 10BASE-T Mode .................................................................................................12 4.2.1 10BASE-T Transmit Blocks....................................................................12 4.2.2 10BASE-T Receive Blocks.....................................................................13 4.3 Analog References..............................................................................................14 4.4 Dynamic Reduced Power & Auto Plugging Detection.........................................14 4.4.1 Auto Plugging Detection.........................................................................14 4.4.2 Dynamic Reduced Power.......................................................................15 4.4.3 Configuration ..........................................................................................15 4.5 Reset...................................................................................................................15 4.6 LAN Connect Interface ........................................................................................16 4.6.1 LAN Connect Clock ................................................................................16 4.6.2 LAN Connect Reset................................................................................16 4.7 LED Functionality ...............................................................................................16 5.0 Platform LAN Connect Registers .....................................................................................17 5.1 Medium Dependent Interface Registers 0 through 7...........................................17 5.1.1 Register 0: Control Register Bit Definitions ...........................................17 5.1.2 Register 1: Status Register Bit Definitions ............................................18 5.1.3 Register 2: PHY Identifier Register Bit Definitions ................................19 5.1.4 Register 3: PHY Identifier Register Bit Definitions ................................19 5.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions ....20 5.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions . 20 5.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions ..........20 5.2 Medium Dependent Interface Registers 8 through 15.........................................21 Datasheet iii 82562ET — Networking Silicon 5.3 Medium Dependent Interface Registers 16 through 31 ......................................21 5.3.1 Register 16: PHY Status and Control Register Bit Definitions ..............21 5.3.2 Register 17: PHY Unit Special Control Bit Definitions ...........................22 5.3.3 Register 18: PHY Address Register.......................................................23 5.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions 23 5.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ... 23 5.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions . 23 5.3.7 Register 22: Receive Symbol Error Counter Bit Definitions ..................24 5.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions 24 5.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Defini- tions 24 5.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions .. 24 5.3.11 Register 27: PHY Unit Special Control Bit Definitions ...........................24 6.0 Electrical and Timing Specifications.................................................................................27 6.1 Absolute Maximum Ratings ................................................................................27 6.2 DC Characteristics .............................................................................................27 6.2.1 X1 Clock DC Specifications ...................................................................27 6.2.2 LAN Connect Interface DC Specifications .............................................28 6.2.3 LED DC Specifications ..........................................................................28 6.2.4 10BASE-T Voltage and Current DC Specifications ...............................28 6.2.5 100BASE-TX Voltage and Current DC Specifications ..........................29 6.3 AC Characteristics ..............................................................................................30 6.3.1 10BASE-T Normal Link Pulse (NLP) Timing Parameters .....................30 6.3.2 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters .................31 6.3.3 100BASE-TX Transmitter AC Specifications .........................................32 6.3.4 Reset (RSTSYNC) AC Specifications ...................................................32 7.0 Package and Pinout Information ......................................................................................33 7.1 Package Information ...........................................................................................33 7.2 Pinout Information ...............................................................................................34 7.2.1 82562ET Pin Assignments ....................................................................34 7.2.2 82562ET Shrink Small Outlying Package Diagram ...............................35 iv Datasheet Networking Silicon — 82562ET 1.0 Introduction 1.1 Overview ® The Intel 82562ET is a highly-integrated Platform LAN Connect device designed for 10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards. The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5 unshielded twisted pair cable or Type 1 shielded twisted pair cable. The 82562ET complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full Duplex Flow Control standard. The 82563ET also includes a PHY interface compliant to the current platform LAN connect interface. 1.2 Features  IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface  IEEE 802.3u Auto-Negotiation support  Digital Adaptive Equalization control  Link status interrupt capability  XOR Tree mode support for board testing  3-port LED support (speed, link and activity)  10BASE-T auto-polarity correction  Diagnostic loopback mode  1:1 transmit transformer ratio support  Low power (less than 300 mW in active transmit mode)  Reduced power in “unplugged mode” (less than 50 mW)  Automatic detection of “unplugged mode”  3.3 V device  48-pin Shrink Small Outline Package  Platform LAN connect interface support 1.3 References  IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and Electronics Engineers  82555 10/100 Mbps LAN Physical Layer Interface Datasheet, Intel Corporation  LAN Connect Interface Specification, Intel Corporation Datasheet 1 82562ET — Networking Silicon 1.4 Product Code The product ordering code for the 82562ET is: DA82562ET. 2 Datasheet Networking Silicon — 82562ET 2.0 82562ET Architectural Overview The 82562ET is a highly integrated Platform LAN Connect device that combines a 10BASE-T and 100BASE-TX physical layer interfaces. The 82562ET supports a single interface fully compliant with the IEEE 802.3 standard. Figure 1 provides a block diagram of the 82562ET architecture. Figure 1. 82562ET Block Diagram Digital LILED Equalizer Port LED ACTLED Adaptation Drivers SPEEDLED Equalizer & Digital Clock 100Base-TX RDN/RDP BLW correction Recovery (100) PCS LAN_RSTSYNC CRS/Link 10 Digital Clock 10Base-T LAN_TXD[2:0] Detection Recovery (10) PCS 3 LAN LAN_RXD[2:0] 3 Connect Transmit DAC LAN_CLK TDN/ TDP Interface 10/100 Auto- Negotiation Bias & Band- Clock Control Gap Voltage Generator Registers Circuit X1 Crystal X2 25 MHz The 8252ET is a 3.3 V device in a 48-pin Shrink Small Outline Package (SSOP). This document describes the architecture of the device in all modes of operation. Four pins, test Enable (TESTEN), Test Clock (ISOL_TCK), Test Input (ISOL_TI), and Test Execute (ISOL_EX), define the general operation of the device. Table 1 shows the pin settings for the different modes of operation. Table 1. 82562ET Hardware Configuration Mode of Operation TESTEN ISOL_TCK ISOL_TI ISOL_EX Comments Normal operating 0 0 0 0 The ISOL_TCK, ISOL_TI, mode and ISOL_EX pins can remain floating. Isolate mode The device is in tri-state 0 111 and power-down mode. (Tri-state and full power-down mode) The device is in tri-state 1 111 and the fully powered down. XOR Tree The XOR Tree is used for 1 000 board testing and tri-state mode. NOTE: Combinations not shown in Table 1 are reserved and should not be used. Datasheet 3 MDI/MDI-X 82562ET — Networking Silicon Figure 2. 82562ET Solution Overview VRM Procesor Clock Termination 2 RIMM MCH Modules IDE Primary UltraDMA/33 IDE PCI Control Bus Secondary ICH2 USB Port 1 PCI Address/Data Bus USB USB Port 2 AMC97 Audio/ AC97 Link Control 82550 LAN Modem Controller Address/Data LPC Bus SIO 82562ET PLC Keyboard Floppy Parallel Game Conn Mouse Serial 1 4 Datasheet ADDR ADDR CTRL CTRL DATA DATA PCI Connector 1 PCI Connector 2 PCI Connector 3 Networking Silicon — 82562ET 3.0 82562ET Signal Descriptions 3.1 Signal Type Definitions Type Name Description I Input Input pin to the 82562ET. O Output Output pin from the 82562ET. I/O Input/Output Multiplexed input and output pin to and from the 82562ET. Multi-level MLT Multi-level analog pin used for input and output. analog I/O Bias pin used for ground connection through a resistor or an external voltage BBias reference. Digital Power DPS Digital power or ground pin for the 82562ET. Supply Analog Power APS Analog power or ground pin for the 82562ET. Supply 3.2 Twisted Pair Ethernet (TPE) Pins Pin Pin Name Type Description Number TDP 10 MLT Transmit Differential Pair. The transmit differential pair sends serial bit streams to the unshielded twisted pair (UTP) cable. The differential pair is TDN 11 a two-level signal in 10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with the isolation transformer. RDP 15 MLT Receive Differential Pair. The receive differential pair receive the serial bit stream from an unshielded twisted pair (UTP) cable. The differential RDN 16 pair is a two-level signal in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-3). These signals directly interface with an isolation transformer. 3.3 External Bias Pins Pin Pin Name Type Description Number RBIAS10 4 B Bias Reference Resistor 10. This pin should be connected to a 549 Ω a pull-down resistor. RBIAS100 5 B Bias reference Resistor 100. This pin should be connected to a 619 Ω b pull-down resistor. a. 549 Ω for RBIAS10 is only a recommended value and should be fine tuned for various designs. b. 619 Ω for RBIAS100 is only a recommended value and should be fine tuned for various designs. Datasheet 5 82562ET — Networking Silicon 3.4 Clock Pins Pin Pin Name Type Description Number X1 46 I Crystal Input Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. Otherwise, X1 is driven by an external metal- oxide semiconductor (MOS) level 25 MHz oscillator when X2 is left floating. X2 47 O Crystal Output Clock. X1 and X2 can be driven by an external 25 MHz crystal of 50 PPM or better. 3.5 Platform LAN Connect Interface Pins Pin Pin Name Type Description Number LAN_CLK 39 O LAN Connect Clock. The LAN Connect Clock is driven by the 82562ET on two frequencies depending on operation speed. When the 82562ET is in 100BASE-TX mode, LAN_CLK drives a 50 MHz clock. Otherwise, LAN_CLK drives a 5 MHz clock for 10BASE-T. The LAN_CLK does not stop during normal operation. LAN_ 42 I Reset/Synchronize. This is a multiplexed pin and is driven by the Media Access Control (MAC) layer device. Its functions are: RSTSYNC  Reset. When this pin is asserted beyond one LAN Connect clock period, the 82562ET uses this signal Reset. To ensure reset of the 82562ET, the Reset signal should remain active for at least 500 µseconds.  Synchronize. When this pin is activated synchronously, for only one LAN Connect clock period, it is used to synchronize the MAC and PHY on LAN Connect word boundaries. LAN_ 45, 44, I LAN Connect Transmit Data. The LAN Connect transmit pins are used 43 to transfer data from the MAC device to the 82562ET. These pins are TXD[2:0] used to move transmitted data and real time control and management data. They also transmit out of band control data from the MAC to the PHY. The pins should be fully synchronous to LAN_CLK. LAN_ 37, 35, O LAN Connect Receive Data. The LAN Connect receive pins are used to 34 transfer data from the 82562ET to the MAC device. These pins are used RXD[2:0] to move received data and real time control and management data. They also move out of band control data from the PHY to the MAC. These pins are synchronous to LAN_CLK. 6 Datasheet Networking Silicon — 82562ET 3.6 LED Pins Pin Pin Name Type Description Number LILED# 27 O Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either mode, the LILED is asserted. ACTLED# 32 O Activity LED. The LED is active low and the Activity LED signal indicates either receive or transmit activity. When no activity is present, the LED is off. The Activity LED will flicker when activity is present. The flicker rate depends on the activity load. The individual address LED control bit (Word A hexadecimal, bit 4) in the ICH2 EEPROM can select the ACTLED# behavior. It controls the Activity LED (ACTLED) functionality in Wake on LAN (WOL) mode. 0 = In WOL mode, the ACTLED is activated by the transmission and reception of broadcast and individual address match packets. 1 = In WOL mode, the ACTLED is activated by the transmission and reception of individual address match packets only. This bit is configured by the OEM and is activated by a transmission and reception of individual address match packets. SPDLED# 31 O Speed LED. The LED is active low and the Speed LED signal indicates the speed of operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX operation and off in 10BASE-T mode. 3.7 Miscellaneous Control Pins Pin Pin Name Type Description Number ADV10 41 I Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and the 82562ET advertises only 10BASE-T technology during Auto-Negotiation processes in this state. Otherwise, the 82562ET advertises all of its technologies. Note: ADV10 has an internal pull-down resistor. ISOL_TCK 30 I Test Clock. The Test Clock signal sets the device into asynchronous test mode in conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1, “82562ET Hardware Configuration” on page 3). In the manufacturing test mode, it acts as the test clock. Note: ISOL_TCK has an internal pull-down resistor. ISOL_TI 28 I Test Input. The Test Input signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1, “82562ET Hardware Configuration” on page 3). In the manufacturing test mode, it acts as the test data input pin. Note: ISOL_TI has an internal pull-down resistor. Datasheet 7 82562ET — Networking Silicon Pin Pin Name Type Description Number ISOL_TEX 29 I Test Execute. The Test Execute signal sets the device into asynchronous test mode in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1, “82562ET Hardware Configuration” on page 3). In the manufacturing test mode, it places the command that was entered through the TI pin in the instruction register. Note: ISOL_TEX has an internal pull-down resistor. TOUT 26 O Test Output. The Test Output pin is used for Boundary XOR scan output. In the manufacturing test mode, it acts as the test output port. TESTEN 21 I Test Enable. The Test Enable pin is used to enable test mode and should be externally pulled up to V to enable XOR Tree test mode. CC 3.8 Power and Ground Connections Pin Pin Name Type Description Number VCC 1, 25 DPS Digital 3.3 V Power. These pins should be connected to the main digital power supply. VCCP 36, 40 VCCA 2, VCCA2 7, VCCT 9, 12, 14, 17 VSS 8, 13, 18 DPS Digital Ground. These pins should be connected to the main digital ground. 24, 48 VSSP 33, 38 VSSA 3 VSSA2 6 VCCR 19, 23 APS Analog Power. VSSR 20, 22 APS Analog Ground. These pins should not be isolated from the main digital. 8 Datasheet Networking Silicon — 82562ET 4.0 Physical Layer Interface Functionality The 82562ET is designed to work in Data Terminating Equipment (DTE) mode only. It supports a direct glueless interface to all components that comply with the LAN Connect specification. The following figure shows how the 82562ET PLC can be used in a 10/100 Mbps Ethernet switch design. Figure 3. 82562ET 10/100 Mbps Ethernet Solution Transmit Differential Pair (TDP/TDN) I/O Control Hub 2 82562ET (ICH2) LAN (LAN Connect Controller Device) Receive Differential Pair (RDP/RDN) Magnetics System Bus Interface 4.1 100BASE-TX Mode 4.1.1 100BASE-TX Transmit Blocks The transmit subsection of the 82562ET accepts 3 bit wide data from the LAN Connect unit. Another subsection passes data unconditionally to the 4B/5B encoder. The 4B/5B encoder accepts nibble-wide data (4 bits) from the CSMA unit and compiles it into 5- bit-wide parallel symbols. These symbols are scrambled and serialized into a 125 Mbps bit stream, converted by the analog transmit driver into a MLT-3 waveform format, and transmitted onto the Unshielded Twisted Pair (UTP) or Shielded Twisted Pair (STP) wire. 4.1.1.1 100BASE-TX 4B/5B Encoder The 4B/5B encoder complies with the IEEE 802.3u 100BASE-TX standard. Four bits are encoded according to the transmit 4B/5B lookup table. The lookup table matches a 5-bit code to each 4-bit code. The table below illustrates the 4B/5B encoding scheme associated with the given symbol. Table 2. 4B/5B Encoder Symbol 5B Symbol Code 4B Nibble Code 0 11110 0000 1 01001 0001 2 10100 0010 3 10101 0011 4 01010 0100 5 01011 0101 Datasheet 9 82562ET — Networking Silicon Symbol 5B Symbol Code 4B Nibble Code 6 01110 0110 7 01111 0111 8 10010 1000 9 10011 1001 A 10110 1010 B 10111 1011 C 11010 1100 D 11011 1101 E 11100 1110 F 11101 1111 Inter Packet Idle Symbol I 11111 (No 4B) 1st Start of Packet Symbol J 11000 0101 2nd Start of Packet Symbol K 10001 0101 T 01101 1st End of Packet Symbol 2nd End of Packet Symbol R 00111 and Flow Control V 00000 INVALID V 00001 INVALID V 00010 INVALID V 00011 INVALID H 00100 INVALID V 00101 INVALID V 00110 INVALID V 01000 INVALID V 01100 INVALID V 10000 Flow Control S V 11001 INVALID 4.1.1.2 100BASE-TX Scrambler and MLT-3 Encoder Data is scrambled in 100BASE-TX in order to reduce electromagnetic emissions during long transmissions of high-frequency data codes. The scrambler logic accepts 5 bits from the 4B/5B encoder block and presents the scrambled data to the MLT-3 encoder. The 82562ET implements the 11-bit stream cipher scrambler as adopted by the ANSI XT3T9.5 committee for UTP operation. The cipher equation used is: X[n] = X[n-11] + X[n-9] (mod 2) The MLT-3 encoder receives the scrambled Non-Return to Zero (NRZ) data stream from the scrambler and encodes the stream into MLT-3 for presentation to the driver. MLT-3 is similar to NRZ1 coding, but three levels are output instead of two. The three output levels are positive, 10 Datasheet Networking Silicon — 82562ET negative and zero. When an NRZ “0” arrives at the input of the encoder, the last output level is maintained (either positive, negative or zero). When an NRZ “1” arrives at the input of the encoder, the output steps to the next level. The order of steps is negative-zero-positive-zero which continues periodically. Refer to IEEE 802.3 Specification for details. 4.1.1.3 100BASE-TX Transmit Framing The 82562ET does not differentiate between the fields of the MAC frame containing preamble, start of frame delimiter, data and Cyclic Redundancy Check (CRC). The 82562 encodes the first byte of the preamble as the “JK” symbol, encodes all other pieces of data according to the 4B/5B lookup table, and adds the “TR” code after the end of the packet. The 82562 scrambles and serializes the data into a 125 Mbps stream, encodes it as MLT-3, and drives it onto the wire. 4.1.1.4 Transmit Driver The transmit differential lines are implemented with a digital slope controlled current driver that meets Twisted Pair Physical Media Device (TP-PMD) specifications. Current is sunk from the isolation transformer by the transmit differential pins. The conceptual transmit differential waveform for 100 Mbps is illustrated in the following figure. Figure 4. Conceptual Transmit Differential Waveform The magnetics module external to the 82562ET converts I and I to 2.0 V , as required by TDP TDN PP the TP-PMD specification. The same magnetics used for 100BASE-TX mode can also work in 10BASE-T mode. 4.1.2 100BASE-TX Receive Blocks The receive subsection of the 82562ET accepts 100BASE-TX MLT-3 data on the receive differential pair. Due to the advanced digital signal processing design techniques employed, the 82562ET will accurately receive valid data from Category 5 (CAT5) UTP and Type 1 STP cable of length well in excess of 100 meters. 4.1.2.1 Adaptive Equalizer The distorted MLT-3 signal at the end of the wire is restored by the equalizer. The equalizer performs adaptation based on the shape of the received signal, equalizing the signal to meet superior data dependent jitter performance. Datasheet 11 82562ET — Networking Silicon 4.1.2.2 Receive Clock and Data Recovery The clock recovery circuit uses advanced digital signal processing technology to compensate for various signal jitter causes. The circuit recovers the 125 MHz clock and data and presents the data to the MLT-3 decoder. 4.1.2.3 MLT-3 Decoder, Descrambler, and Receive Digital Section The 82562ET first decodes the MLT-3 data, and then the descrambler reproduces the 5B symbols originated in the transmitter. The descrambling is based on synchronization to the transmission of the 11-bit Linear Feedback Shift Register (LFSR) during an idle phase. The data is decoded at the 4B/5B decoder. After the 4B symbols are obtained, the 82562ET outputs the receive data to the CSMA unit. In 100BASE-TX mode, the 82562ET can detect errors in receive data in a number of ways. Any of the following conditions is considered an error:  Link integrity fails in the middle of frame reception.  The start of stream delimiter “JK” symbol is not fully detected after idle.  An invalid symbol is detected at the 4B/5B decoder.  Idle is detected in the middle of a frame (before “TR” is detected). 4.2 10BASE-T Mode 4.2.1 10BASE-T Transmit Blocks 4.2.1.1 10BASE-T Manchester Encoder After the 2.5 MHz clocked data is serialized in a 10 Mbps serial stream, the 20 MHz clock performs the Manchester encoding. The Manchester code always has a mid-bit transition. The boundary transition occurs only when the data is the same from bit to bit. For example, if the value is 11b, then the change is from low to high within the boundary. 4.2.1.2 10BASE-T Driver and Filter Since 10BASE-T and 100BASE-TX have different filtration needs, both filters are implemented inside the chip. The 82562ET supports both technologies through one pair of transmit differential pins and by externally sharing the same magnetics. In 10 Mbps mode the line drivers use a pre-distortion algorithm to improve jitter tolerance. The line drivers reduce their drive level during the second half of “wide” (100 ns) Manchester pulses and maintain a full drive level during all narrow (50 ns) pulses and the first half of the wide pulses. This reduces line overcharging during wide pulses, a major source of jitter. 12 Datasheet Networking Silicon — 82562ET 4.2.2 10BASE-T Receive Blocks 4.2.2.1 10BASE-T Manchester Decoder The 82562ET performs Manchester decoding and timing recovery in 10BASE-T mode. The Manchester encoded data stream is decoded from the receive differential pair. This data is transferred to the controller at 2.5 MHz/nibble. The high-performance circuitry of the 82562ET exceeds the IEEE 802.3 jitter requirements. 4.2.2.2 10BASE-T Twisted Pair Ethernet (TPE) Receive Buffer and Filter In 10 Mbps mode, data is expected to be received on the receive differential pair after passing through isolation transformers. The filter is implemented inside the 82562ET for supporting single magnetics that are shared with the 100BASE-TX side. The input differential voltage range for the Twisted Pair Ethernet (TPE) receiver is greater than 585 mV and less than 3.1 V. The TPE receive buffer distinguishes valid receive data, link test pulses, and the idle condition, according to the requirements of the 10BASE-T standard. The following line activity is determined to be inactive and is rejected as invalid data:  Differential pulses of peak magnitude less than 300 mV.  Continuous sinusoids with a differential amplitude less than 6.2 V and frequency less than 2 PP MHz.  Sine waves of a single cycle duration starting with 0° or 180° phase that have a differential amplitude less than 6.2 V and a frequency of at least 2 MHz and not more than 16 MHz. PP These single-cycle sine waves are discarded only if they are preceded by 4 bit times (400 ns) of silence. All other activity is determined to be either data, link test pulses, Auto-Negotiation fast link pulses, or the idle condition. Datasheet 13 82562ET — Networking Silicon 4.3 Analog References The 82562ET has two inputs, RBIAS100 and RBIAS10, that require external resistor connections to set biases for its internal analog section. The input pins are sensitive to the resistor value and experimentation is required to determine the correct values for any given layout. Resistors of 1% tolerance should be used. Figure 5. Analog References 82562 549 1% RBIAS10 619 1% RBIAS100 4.4 Dynamic Reduced Power & Auto Plugging Detection The 82562ET can be configured to support a dynamic reduced power mode. This mode reduces power consumption of the 82562ET when LAN activity is not present. The reduced power mode decreases power consumption from 300 mW to about 50 mW and is based on automatic detection of cable plugging. If the 82562ET is configured to support dynamic power reduction, it enters the reduced power mode whenever a cable is not connected to the device. In reduced power mode, the 82562ET shuts off the link circuits, except the circuit used for the automatic plugging detection. On the LAN Connect side, the entire interface remains active, including full access to all MII Management Interface (MMI) registers. In this mode, the 82562ET switches to the 10 Mbps speed interface (5 MHz for LAN Connect). Thus, the reduced power mode is fully transparent to driver. 4.4.1 Auto Plugging Detection The 82562ET senses the link all the time. If it detects loss of any link activity for more than 6.6 seconds, it indicates to the Media Access Controller (MAC) an “unplugged state” by resetting the SQL LAN Connect control bit. If the 82562ET is in reduced power mode and link activity is detected, the 82562ET notifies the MAC (in less than 1 second) that it is in a “plugged state” by setting the SQL LAN Connect control bit. Link activity detection is based on energy detection. 14 Datasheet Networking Silicon — 82562ET 4.4.2 Dynamic Reduced Power The 82562ET can be configured to support dynamic reduced power. In the dynamic reduced power mode, the 82562ET transitions to reduced power mode when an unplugged state is detected. The 82562ET will only return to full power if the reduced power bit on the LAN Connect is reset and a plugged state is detected. However, if the 82562ET is not configured to support dynamic reduced power, the 82562ET operates according to the LAN Connect power-down bit (in other words, the 82562ET will operate in reduced power mode only if the LAN Connect power-down bit is set). 4.4.3 Configuration The dynamic reduced power mode is configured through bit 13 of register 16. The default value is disabled (0). The status of the 82562ET can be read through bits 10:9 of register 16. When the 82562ET is in reduced power mode, these two bits are set to 1b. Table 3. Register 16 (10 Hexadecimal): PLC Status, Control and Address Data Bit Name Description Read/Write 0 = Automatic reduced power down enabled 13 Dynamic Reduced Power Down Read/Write 1 = Automatic reduced power down disabled (default) The 100BASE-TX Power Down bit indicates the power state. 10 100BASE-TX Power Down Read Only 0 = Normal operation (default) 1 = Power down The 10BASE-T Power Down bit indicates the power state. 9 10BASE-T Power Down Read Only 0 = Normal operation (default) 1 = Power down The 82562ET can enter a reduced power state manually through bit 11 of register 0. This bit is ORed with the LAN Connect power down bit, which allows the 82562ET to enter a reduced power state. Table 4. Register 0: Control Data Bit Name Description Read/Write 0 = Reduced power down disabled (normal operation; default) 11 Reduced Power Down Read/Write 1 = Reduced power down enabled 4.5 Reset When 82562ET’s Reset signal (RSTSYNC) is asserted for at least 500 µseconds, all internal circuits are reset. The 82562ET can also be reset through the MII management register reset bit (register 0, bit 15). Datasheet 15 82562ET — Networking Silicon 4.6 LAN Connect Interface The 82562ET supports the LAN connect interface as specified in the LAN Connect Interface Specification. The LAN Connect is the I/O Control Hub 2 (ICH2) interface to the 82562ET. The 8- pin interface incorporates all MII and MII management functionality and includes the reset functionality as well. 4.6.1 LAN Connect Clock The 82562ET drives a 50 MHz or 5 MHz clock to the MAC depending on the selected technology (100BASE-TX or 10BASE-T, respectively). The 82562ET does not stop the LAN Connect clock for any reason. During reduced power mode, the 82562ET drives a 5 MHz clock. 4.6.2 LAN Connect Reset To determine the type of signal on the PLC Reset/Synchronization pin, the 82562ET filters out pulses that are less than 200 nanoseconds. To reset the 82562ET, the pulse should be longer than 500 µseconds. 4.7 LED Functionality Table 5. LED Functionality LED Driver Function Description The driver blinks at a rate related to the utilization. The blinking occurs during ACTLED# Activity transmission or reception of a frame. SPDLED# Speed The driver is low for 100BASE-TX operation and high for 10BASE-T mode. LILED# Link valid The driver is low when a valid link is present. 16 Datasheet Networking Silicon — 82562ET 5.0 Platform LAN Connect Registers The following subsections describe PHY registers that are accessible through the LAN Connect management frame protocol. Acronyms mentioned in the registers are defined as follows: SC: Self cleared. RO: Read only. RW: Read/Write. E: EEPROM setting affects content. LL: Latch low. LH: Latch high. 5.1 Medium Dependent Interface Registers 0 through 7 5.1.1 Register 0: Control Register Bit Definitions Bit(s) Name Description Default R/W 15 Reset This bit sets the status and control register of the PHY to 0RW their default states and is self-clearing. The PHY returns SC a value of one until the reset process has completed and accepts a read or write transaction. 0 = Normal operation 1 = PHY Reset 14 Loopback This bit enables loopback of transmit data nibbles to the 0RW receive data path. The PHY receive circuitry is isolated from the network. Note that this may cause the descrambler to lose synchronization and produce 560 nanoseconds of “dead time.” Note also that the loopback configuration bit takes priority over the Loopback MDI bit. 0 = Loopback disabled (normal operation) 1 = 1 = Loopback enabled 13 Speed Selection This bit is valid on read and controls speed when Auto- 1RW Negotiation is disabled. 0 = 10 Mbps 1 = 100 Mbps 12 Auto-Negotiation This bit enables Auto-Negotiation. Bits 13 and 8, Speed 1RW Enable Selection and Duplex Mode, respectively, are ignored when Auto-Negotiation is enabled. 0 = Auto-Negotiation disabled 1 = Auto-Negotiation enabled 11 Reduced Power This bit sets the PHY into a low power mode. 0RW Down 0 = Power down disabled (normal operation) 1 = Power down enabled Datasheet 17 82562ET — Networking Silicon Bit(s) Name Description Default R/W 10 Isolate This bit allows the PHY to isolate the medium 0RW independent interface. The PHY is disconnected from the LAN Connect block on both the transmit and receive side. 0 = Normal operation 1 = Isolates internal medium independent interface 9 Restart Auto- This bit restarts the Auto-Negotiation process and is self- 0RW Negotiation clearing. SC 0 = Normal operation 1 = Restart Auto-Negotiation process 8 Duplex Mode This bit controls the duplex mode when Auto-Negotiation 0RW/ is disabled. When Auto-Negotiation is enabled this bit is RO read only and always equals 1b. When the PHY is placed in Loopback mode, the behavior of the PHY shall not be affected by the status of this bit. 0 = Half Duplex 1 = Full Duplex 7 Collision Test This bit is not used in the 82562ET and has a default 1RW value of 1b. (If it is used in other devices, it forces a collision in response to the assertion of the transmit enable signal.) 6:0 Reserved These bits are reserved and should be set to 0000000b. 0 RW 5.1.2 Register 1: Status Register Bit Definitions Bit(s) Name Description Default R/W 15 Reserved This bit is reserved and should be set to 0b. 0 RO 14 100BASE-TX This bit enables 100BASE-TX full-duplex operation 1RO Full-duplex and is dependent on ADV10. If ADV10 is active, the default value is 0. 0 = PHY unable to perform full-duplex 100BASE-TX 1 = PHY able to perform full-duplex 100BASE-TX 13 100 Mbps Half- This bit enables 100BASE-TX half-duplex operation 1RO duplex and is dependent on ADV10. If ADV10 is active, the default value is 0. 0 = PHY unable to perform half-duplex 100BASE-TX 1 = PHY able to perform half-duplex 100BASE-TX 12 10 Mbps Full- This bit enables 10BASE-T full duplex operation. 1RO duplex 0 = PHY unable to perform full-duplex 10BASE-T 1 = PHY able to perform full-duplex 10BASE-T 11 10 Mbps Half- This bit enables 10BASE-T half-duplex operation. 1RO duplex 0 = PHY unable to perform half-duplex 10BASE-T 1 = PHY able to perform half-duplex 10BASE-T 10:7 Reserved These bits are reserved and should be set to 0000b. 0 RO 18 Datasheet Networking Silicon — 82562ET Bit(s) Name Description Default R/W 6 Management This bit allows the 82562ET to receive management 0RO Frames Preamble frames with suppressed preamble. Suppression 0 = PHY will not accept management frames with preamble suppressed 1 = PHY will accept management frames with preamble suppressed 5 Auto-Negotiation This bit reflects status of the Auto-Negotiation 0RO Complete process. 0 = Auto-Negotiation process has not completed 1 = Auto-Negotiation process completed 4 Remote Fault 0 = No remote fault condition detected 0RO 1 = Remote fault condition detected 3 Auto-Negotiation This bit reflects the PHY’s Auto-Negotiation ability 1RO Ability status. 0 = PHY is unable to perform Auto-Negotiation 1 = PHY is able to perform Auto-Negotiation 2 Link Status This bit reflects link status. 0RO 0 = Invalid link detected LL 1 = Valid link established 1 Jabber Detect This bit is used only in 10BASE-T mode. 0RO 0 = No jabber condition detected LH 1 = Jabber condition detected 0 Extended This bit enables the extended register capabilities. 1RO Capability 0 = Extended register capabilities disabled 1 = Extended register capabilities enabled 5.1.3 Register 2: PHY Identifier Register Bit Definitions Bit(s) Name Description Default R/W 15:0 PHY ID (high Value: 02A8 hexadecimal -- RO byte) 5.1.4 Register 3: PHY Identifier Register Bit Definitions Bit(s) Name Description Default R/W 15:0 PHY ID (low byte) Value: 0330 hexadecimal -- RO Datasheet 19 82562ET — Networking Silicon 5.1.5 Register 4: Auto-Negotiation Advertisement Register Bit Definitions Bit(s) Name Description Default R/W 15 Next Page This bit is a constant 0, transmit primary capability 0RO data page. 14 Reserved This bit is reserved and should be set to 0b. 0 RO 13 Remote Fault 0 = No remote fault 0RW 1 = Indicate link partner’s remote fault 12:5 Technology Ability Technology Ability Field is an 8-bit field containing 00101111 RW Field information indicating supported technologies specific to the selector field value. 4:0 Selector Field The Selector Field is a 5-bit field identifying the type of 00001 RO message to be sent by Auto-Negotiation. This field is read only and contains a value of 00001b, IEEE Standard 802.3. 5.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions Bit(s) Name Description Default R/W 15 Next Page This bit reflects the PHY’s link partner’s Next Page -- RO ability. 14 Acknowledge This bit is used to indicate that the 82562ET has -- RO successfully received its link partner’s Auto- Negotiation advertising ability. 13 Remote Fault This bit reflects the PHY’s link partner’s Remote Fault -- RO condition. 12:5 Technology Ability This bit reflects the PHY’s link partner’s Technology -- RO Field Ability Field. 4:0 Selector Field This bit reflects the PHY’s link partner’s Selector -- RO Field. 5.1.7 Register 6: Auto-Negotiation Expansion Register Bit Definitions Bit(s) Name Description Default R/W 15:5 Reserved These bits are reserved and should be set to 0. 0 RO 4 Parallel Detection This bit clears itself on read. 0RO Fault 0 = No fault detected via parallel detection SC 1 = Fault detected via parallel detection (multiple link LH fault occurred) 3 Link Partner Next 0 = Link Partner is not Next Page able 0RO Page Able 1 = Link Partner is Next Page able 20 Datasheet Networking Silicon — 82562ET Bit(s) Name Description Default R/W 2 Next Page Able 0 = 0 = Local drive is not Next Page able 0RO 1 = Local drive is Next Page able 1 Page Received This bit clears itself on read. 0RO 0 = New Page not received SC 1 = New Page received LH 0 Link Partner Auto- 0 = Link Partner is not Auto-Negotiation able 0RO Negotiation Able 1 = Link Partner is Auto-Negotiation able 5.2 Medium Dependent Interface Registers 8 through 15 Registers eight through fifteen are reserved for IEEE. 5.3 Medium Dependent Interface Registers 16 through 31 5.3.1 Register 16: PHY Status and Control Register Bit Definitions Bit(s) Name Description Default R/W 15:14 Reserved These bits are reserved and should be set to 00b. 00 RW 13 Reduced Power This bit disables the automatic reduced power down. 1RW Down Disable 0 = Enable automatic reduced power down 1 = Disable automatic reduced power down 12 Reserved This bit is reserved and should be set to 0b. 0 RW 11 Receive De- This bit indicates status of the 100BASE-TX Receive -- RO Serializer In-Sync De-Serializer In-Sync. Indication 10 100BASE-TX This bit indicates the power state of 100BASE-TX 1RO Power-Down PHY unit. 0 = Normal operation 1 = Power-down 9 10BASE-T This bit indicates the power state of 10BASE-T PHY 1RO Power-Down unit. 0 = Normal operation 1 = Power-Down 8 Polarity This bit indicates 10BASE-T polarity. -- RO 0 = Normal polarity 1 = Reverse polarity 7 Reserved This bit is reserved and should be set to 0b. 0 RO Datasheet 21 82562ET — Networking Silicon Bit(s) Name Description Default R/W 6:2 PHY Address These bits contain the sampled PHY address. -- RO 1 Speed This bit indicates the Auto-Negotiation result. -- RO 0 = 10 Mbps 1 = 100 Mbps 0 Duplex Mode This bit indicates the Auto-Negotiation result. -- RO 0 = Half-duplex 1 = Full-duplex 5.3.2 Register 17: PHY Unit Special Control Bit Definitions Bit(s) Name Description Default R/W 15 Scrambler By- 0 = Normal operations 0RW pass 1 = By-pass scrambler 14 By-pass 4B/5B 0 = Normal operation 0RW 1 = 4 bit to 5 bit by-pass 13 Force Transmit H- 0 = Normal operation 0RW Pattern 1 = Force transmit H-pattern 12 Force 34 Transmit 0 = Normal operation 0RW Pattern 1 = Force 34 transmit pattern 11 Valid Link 0 = Normal operation 0RW 1 = 100BASE-TX valid link 10 Symbol Error 0 = Normal operation 0RW Enable 1 = Symbol error output is enabled 9 Carrier Sense This bit controls the receive 100 carrier sense disable 0RW Disable function. 0 = Carrier sense enabled 1 = Carrier sense disabled 8 Disable Dynamic 0 = Dynamic Power-Down enabled 0RW Power-Down 1 = Dynamic Power-Down disabled 7 Auto-Negotiation 0 = Auto-Negotiation normal mode 0RW Loopback 1 = Auto-Negotiation loopback 6 MDI Tri-State 0 = Normal operation 0RW 1 = MDI Tri-state (transmit driver tri-states) 5 Force Polarity 0 = Normal polarity 0RW 1 = Reversed polarity 4Auto Polarity 0 = Normal polarity operation 0RW Disable 1 = Auto Polarity disabled 3 Squelch Disable 0 = Normal squelch operation 0RW 1 = 10BASE-T squelch test disable 22 Datasheet Networking Silicon — 82562ET Bit(s) Name Description Default R/W 2 Extended 1 = 10BASE-T Extended Squelch control enabled 0RW Squelch 0 = 10BASE-T Extended Squelch control disabled 1 Link Integrity 0 = Normal Link Integrity operation 0RW Disable 1 = Link disabled 0 Jabber Function 0 = Normal Jabber operation 0RW Disable 1 = Jabber disabled 5.3.3 Register 18: PHY Address Register Bit(s) Name Description Default R/W 15:5 Reserved These bits are reserved and should be set to a 0RO constant 0. 4:0 PHY Address These bits are set to the PHY’s address. 00001 RO 5.3.4 Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Receive False These bits are used for the false carrier counter. -- RO Carrier SC 5.3.5 Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Disconnect Event This field contains a 16-bit counter that increments for -- RO each disconnect event. The counter stops when it is SC full and self-clears on read 5.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Receive Error This field contains a 16-bit counter that increments -- RO Frame once per frame for any receive error condition (such SC as a symbol error or premature end of frame) in that frame. The counter stops when it is full and self-clears on read. Datasheet 23 82562ET — Networking Silicon 5.3.7 Register 22: Receive Symbol Error Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Symbol Error This field contains a 16-bit counter that increments for -- RO Counter each symbol error. The counter stops when it is full SC and self-clears on read. In a frame with a bad symbol, each sequential six bad symbols count as one. 5.3.8 Register 23: 100BASE-TX Receive Premature End of Frame Error Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Premature End of This field contains a 16-bit counter that increments for -- RO Frame each premature end of frame event. The counter SC stops when it is full and self-clears on read. 5.3.9 Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 End of Frame This is a 16-bit counter that increments for each end -- RO Counter of frame event. The counter stops when it is full and SC self-clears on read. 5.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions Bit(s) Name Description Default R/W 15:0 Jabber Detect This is a 16-bit counter that increments for each -- RO Counter jabber detection event. The counter stops when it is SC full and self-clears on read. 5.3.11 Register 27: PHY Unit Special Control Bit Definitions Bit(s) Name Description Default R/W 15:6 Reserved These bits are reserved and should be set to a 0RO constant 0. 5 Switch Probe This bit switches the mapping on the LEDs. The LED 0RW Mapping mapping is described below in bits 2:0, LED Switch Control. This bit should always be set to 0b. 24 Datasheet Networking Silicon — 82562ET Bit(s) Name Description Default R/W 4 Reserved This bit is reserved and should be set to 0. 0 RO 3 100BASE-TX This bit enables the carrier sense disconnection while 0RW Receive Jabber the PHY is in jabber mode at 100 Mbps speed. Disable 2:0 LED Switch Value ACTLED LILED 000 RW Control 000 Activity Link 001 Speed Collision 010 Speed Link 011 Activity Collision 100 Off Off 101 Off On 110 On Off 111 On On Datasheet 25 82562ET — Networking Silicon Note: This page intentionally left blank. 26 Datasheet Networking Silicon — 82562ET 6.0 Electrical and Timing Specifications 6.1 Absolute Maximum Ratings Maximum ratings are listed below: Case Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to 135 C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 C to 150 C Supply Voltage with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 3.45 V SS Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50 V to 3.45 V Input Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V to 3.45 V CC Stresses above the listed absolute maximum ratings may cause permanent damage to the 82562ET device. This is a stress rating only and functional operations of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 6.2 DC Characteristics Table 6. General DC Specifications Symbol Parameter Condition Min Typical Max Units Notes V Supply Voltage 3.0 3.3 3.45 V CC Minimum/Maximum Case T Temperature 085C Temperature 10/100Mbps (transmitter 300 mW on) Power P Consumption Reduced Power 50 mW Auto-Negotiation 200 mW 6.2.1 X1 Clock DC Specifications Table 7. X1 Clock DC Specifications Symbol Parameter Condition Min Typical Max Units Notes V Input Low Voltage 0.8 V IL Input High V 2.0 V IH Voltage Input Leakage I 0 < V < V ±10 µA ILIH IN CC Currents Input C 8pF 1 I Capacitance NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only. Datasheet 27 82562ET — Networking Silicon 6.2.2 LAN Connect Interface DC Specifications Table 8. LAN Connect Interface DC Specifications Symbol Parameter Condition Min Typical Max Units Notes Input/Output V 3.0 3.45 V CCJ Supply Voltage V Input Low Voltage -0.5 0.3V V IL CCJ Input High V + CCJ V 0.6V V IH CCJ Voltage 0.5 Input Leakage I 0 < V < V ±10 µA IL IN CCJ Current Output Low V I = 1500 µA 0.1V V OL OUT CCJ Voltage Output High V I = -500 µA 0.9V V OH OUT CCJ Voltage Input Pin C 8pF 1 IN Capacitance NOTES: 1. This characteristic is only characterized, not tested. It is valid for digital pins only. 6.2.3 LED DC Specifications Table 9. LED DC Specifications Symbol Parameter Condition Min Typical Max Units Notes Output Low V I = 10 mA 0.7 V OLLED OUT Voltage Output High V I = -10 mA 2.4 V OHLED OUT Voltage 6.2.4 10BASE-T Voltage and Current DC Specifications Table 10. 10BASE-T Transmitter Symbol Parameter Condition Min Typical Max Units Notes Output Differential V R = 100 Ω 2.2 2.8 V 1 OD10 L Peak Voltage NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. R is the resistive load measured across the transmit differential pins, TDP and TDN. L 28 Datasheet Networking Silicon — 82562ET Table 11. 10BASE-T Receiver Symbol Parameter Condition Min Typical Max Units Notes Input Differential R DC 10 KΩ 1 ID10 Resistance Input Differential V Accept Peak 5 MHz ≤ f ≤ 10 MHz 585 3100 mV IDA10 Voltage Input Differential V Reject Peak 5 MHz ≤ f ≤ 10 MHz 300 mV IDR10 Voltage Input Common V V V ICM10 CC/2 Mode Voltage NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. 6.2.5 100BASE-TX Voltage and Current DC Specifications Table 12. 100BASE-TX Transmitter Symbol Parameter Condition Min Typical Max Units Notes Output Differential V R = 100 Ω 0.95 1.0 1.05 V 1 OD100 L Peak Voltage NOTES:Current is measured between the transmit differential pins (TDP and TDN) at 3.3 V. 1. R is the resistive load measured across the transmit differential pins, TDP and TDN. L Table 13. 100BASE-TX Receiver Symbol Parameter Condition Min Typical Max Units Notes Input Differential R DC 10 KΩ 1 ID100 Resistance Input Differential V Accept Peak 500 1200 mV IDA100 Voltage Input Differential V Reject Peak 100 mV IDR100 Voltage Input Common V V V ICM100 CC/2 Mode Voltage NOTES: 1. The input differential resistance is measured across the receive differential pins, RDP and RDN. Datasheet 29 82562ET — Networking Silicon 6.3 AC Characteristics Figure 6 defines the conditions for timing measurements. The design must guarantee proper operation for voltage swings and slew rates that exceed the specified test conditions. Figure 6. AC Test Level Conditions Input Levels Output Levels V = 2.0 V OH 1.4 V V = 0.8 V OL 6.3.1 10BASE-T Normal Link Pulse (NLP) Timing Parameters Table 14. Normal Link Pulse Timing Parameters Symbol Parameter Condition Min Typical Max Units Notes T6 T NLP Width 10 Mbps 100 ns NLP_WID T7 T NLP Period 10 Mbps 8 16 24 ms NLP_PER Figure 7. Normal Link Pulse Timings T7 T6 Normal Link Pulse 30 Datasheet Networking Silicon — 82562ET 6.3.2 Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Table 15. Fast Link Pulse Timing Parameters Symbol Parameter Condition Min Typical Max Units Notes FLP Width (clock T8 T 100 ns FLP_WID and data) Clock Pulse to T9 T Clock Pulse 111 125 139 µs FLP_CLK_CLK Period Clock Pulse to T10 T 55.5 62.5 69.5 µs FLP_CLK_DATA Data Pulse Period Pulses in One T11 T 17 33 # FLP_BUR_NUM Burst T12 T Burst Width 2 ms FLP_BUR_WID T13 T FLP Burst Period 8 16 24 ms FLP_BUR_PER Figure 8. Fast Link Pulse Timings T9 T10 T8 Fast Link Pulse Clock Pulse Data Pulse Clock Pulse T13 T12 FLP Bursts Datasheet 31 82562ET — Networking Silicon 6.3.3 100BASE-TX Transmitter AC Specifications Table 16. 100BASE-TX Transmitter Timing Parameters Symbol Parameter Condition Min Typical Max Units Notes TDP/TDN T14 T Differential Output HLS Data 1400 ps JIT Peak Jitter 6.3.4 Reset (RSTSYNC) AC Specifications Table 17. Reset Timing Parameters Symbol Parameter Condition Min Typical Max Units Notes Reset Pulse T58 T 500 µs RST_WID Width Power-up to T59 T Falling Edge of 1000 µs POP_RST Reset Figure 9. Reset Timing Parameters Power Up (Vcc) T59 T58 RESET 32 Datasheet Networking Silicon — 82562ET 7.0 Package and Pinout Information 7.1 Package Information The 82562ET is a 48-pin Shrink Small Outlying Package (SSOP). The Package dimensions are shown in Figure 10. More information on Intel device packaging is available in the Intel Packaging Handbook, which is available from the Intel Literature Center or your local sales office. Figure 10. Dimension Diagram for the 82562ET 48-pin SSOP Datasheet 33 82562ET — Networking Silicon 7.2 Pinout Information 7.2.1 82562ET Pin Assignments Table 18. 82562ET Pin Assignments Pin Pin Pin Pin Pin Name Pin Name Pin Name Pin Name Number Number Number Number 1 VCC 13 VSS 25 VCC 37 LAN_RXD2 2 VCCA 14 VCCT 26 TOUT 38 VSSP 3 VSSA 15 RDP 27 LILED 39 LAN_CLK 4 RBIAS10 16 RDN 28 ISOL_TI 40 VCCP 5 RBIAS100 17 VCCT 29 ISOL_TEX 41 ADV10 6 VSSA2 18 VSS 30 ISOL_TCK 42 LAN_RSTSYNC 7 VCCA2 19 VCCR 31 SPDLED 43 LAN_TXD0 8 VSS 20 VSSR 32 ACTLED 44 LAN_TXD1 9 VCCT 21 TESTEN 33 VSSP 45 LAN_TXD2 10 TDP 22 VSSR 34 LAN_RXD0 46 X1 11 TDN 23 VCCR 35LAN_RXD147 X2 12 VCCT 24 VSS 36 VCCP 48 VSS 34 Datasheet Networking Silicon — 82562ET 7.2.2 82562ET Shrink Small Outlying Package Diagram Figure 11. 82562ET Pin Out Diagram VCC (DPS) 1 48 VSS (DPS) VCCA (APS) 2 47 X2 (O) 3 VSSA (APS) 46 X1(I) RBIAS10 (B) 4 45 LAN_TXD2 (I) RBIAS100 (B) 5 44 LAN_TXD1 (I) VSSA2 (APS) 6 43 LAN_TXD0 (I) VCCA2 (APS) 7 42 LAN_RSTSYNC 8 ADV10 (I) VSS (DPS) 41 9 VCCT (APS) 40 VCCP (DPS) 10 39 TDP (MLT) LAN_CLK (O) 82562ET 11 TDN (MLT) 38 VSSP (DPS) PIN DIAGRAM 12 VCCT (APS) 37 LAN_RXD2 (O) SSOP48 13 VSS (DPS) 36 VCCP (DPS) Rev 1.0 14 VCCT (APS) 35 LAN_RXD1 (O) Top View 15 RDP (MLT) 34 LAN_RXD0 (O) 16 RDN (MLT) 33 VSSP (DPS) 17 VCCT (APS) 32 ACTLED# (O) 18 31 VSS (DPS) SPDLED# (O) VCCR (APS) 19 30 ISOL_TCK (I) VSSR (APS) 20 29 ISOL_TEX (I) TESTEN (I) 21 28 ISOL_TI (I) VSSR (APS) 22 27 LILED# (O) VCCR (APS) 23 26 TOUT (O) 24 VSS (DPS) 25 VCC (DPS) Pin Types: APS= Analog Power Supply, DPS = Digital Power Supply, I = Input, O = Output Datasheet 35 82562ET — Networking Silicon Note: This page intentionally left blank. 36 Datasheet