16-bit, 75 MHz RISC microprocessor EVA-X1630C with Ethernet and cache 1 SoC Features Board Diagram § 16-bit RISC architecture embedded microcontroller with pipeline technology § Up to 100 MHz operating frequency 2 RISC SOM § Fast Ethernet MAC with MII interface § Dual FIFO UART serial channels § 80C186 software compatibility 3 § Up to 18 programmable I/O pins RISC CE-Builder § 128-Pin PQFP § Compatible with 3.3 V I/O and 2.5 V core voltage 4 § 8K cache for I/O RISC System Platforms Introduction With the Ethernet protocol becoming the de facto network of choice for an increasing number of professional, office, industrial, and even home environments, it makes sense to develop new systems and leverage existing ones to take advantage of Ethernet connectivity. Advantech’s EVA-X1630C integrates 10/100 Ethernet and RS-232 connectivity into an economical 80C186-compatible 75 MHz RISC microprocessor with cache and 2.5 V core voltage, putting the Ethernet within reach of a host of applications. Best Performance-to-Cost The EVA-X1630C is a 16-bit, high performance, RISC architecture microprocessor with 80C186 compatibility. Additional functions integrated on the chip are: cache, SDRAM controller, non-multiplexed address bus, interrupt controller, DMA controller, timers, watchdog timer, FIFO UART serial ports, programmable I/O (PIO) pins and fast Ethernet MAC (Media AccessController). The advanced internal high-speed local bus architecture significantly increases overall system performance. High performance plus high integration enable the EVA-X1630C to increase functionality while reducing BOM system costs. This, combined with a royalty-free real-time OS, contributes to its highly advantageous performance-to-cost ratio. The EVA-X1630C has been designed to meet the communication requirements of products such as device servers, medical monitors, industrial machinery, scales, security systems, code scanners, shared IP devices, thermostats, and wireless access points. Bus Interface Solution on Chip § One non-multiplexed system bus interface 16-bit Microprocessor § Non-multiplexed address and data bus § RISC architecture with Pipeline Technology § Supports non-multiplexed address bus A [19:0] § Five-stage pipeline § 8- or 16-bit external bus dynamic access § Static design & Synthesizable design § Supports max. 512 KB, 8- or 16-bit data width Flash ROM § 1 M byte memory address space § Multiplexed with SDRAM bus interface § 64 K byte I/O address space § 64 K-byte I/O space § 8K cache for I/O § Supports memory and I/O devices § 80C186 software compatibility § 1 M-byte memory address space § Up to 100 MHz operating frequency § Supports an independent bus for slower I/O devices SDRAM Control Interface Supports an Independent Bus for I/O Devices § Supports 16-bit data bus width § Multiplexed address and data § Supports 1 Mbit x 16 and 4 Mbit x 16 SDRAM devices § External latches are needed to separate address and data bus § Only used for I/O devices to prevent throttling the performance of SDRAM & non-multiplexed system bus § Shares same pins as one of the FIFO UART channels ARM / XScale Based Embedded Computing Solutions Online Download www.advantech.com/products 1-5 * Note: All specifications are subject to change without notice. EVA-X1630C 1 SoC Features Board Diagram 2 RISC SOM 3 RISC CE-Builder 4 RISC System Platforms Dual FIFO UART Serial Channels Ordering Information § Two integrated, high performance FIFO UART ports with16 byte transmit/receive § EVA-X1630C 16-bit, 75 MHz RISC microprocessor with Ethernet and FIFO cache § Supports two 16550 UART serial channels with 16 bytes FIFO. § EVA-X1630C-DK1 Development kit based on EVA-1630C § Programmable Baud rate generator § The character options are programmable for start bit, stop bit, even/odd or no parity, 5~8 data bits § One of the FIFO UART channels shares same pins as independent I/O § bus interface 1-Port Fast Ethernet MAC Ports with MII Interface § IEEE 802.3, 802.3u specification compliant10/100 Mb/s data transfer rate § IEEE 802.3u compliant MII interface with serial management interface § Full-duplex/half duplex operations § Flow control for full-duplex operations § VLAN Supported § Automatic CRC append and check § Multicast/Broadcast address recognition § Provides loop back path on the MII interface Interrupt Controller § Provides five maskable external interrupts § Provides one non-maskable external interrupt ARM / XScale Based Embedded Computing Solutions Online Download www.advantech.com/products 1-6 * Note: All specifications are subject to change without notice.