Manufacturers
ADVANTECH 78660
Description
Advantech 78660 - 4-Channel 200 MHz, 16-bit A/D with Virtex-6 FPGA - x8 PCIe
Part Number
78660
Price
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Manufacturer
ADVANTECH
Lead Time
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Category
Data Acquisition
Specifications
A/D Converters
Type: Texas Instruments ADS5485. Sampling Rate: 10 MHz to 200 MHz. Resolution: 16 bits
Clock Dividers
External clock or VCXO can be divided by 1, 2, 4, 8, or 16 for the A/D clock
Clock Synthesizer
Clock Source: Selectable from on-board programmable VCXO (10 to 810 MHz), front panel external clock or LVPECL timing bus
Synchronization: VCXO can be locked to an external 4 to 180 MHz PLL system reference, typically 10 MHz
Custom I/O Option -104
Connects 20 pairs of LVDS signals from the FPGA on PMC P14 toa 68-pin DIL ribbon-cable header on the PCIe board for custom I/O.
Custom I/O Option -105
Connects two 4X gigabitserial links from the FPGA on XMC P16 to two 4X gigabit serial connectors along the top edge of the PCIe board
External Clock
Type: Front panel female SSMC connector, sine wave, 0 to +10 dBm, AC-coupled, 50 ohms, accepts 10 to 800 MHz divider input clock or PLL system reference
External Trigger Input
Function: Programmable functions in-clude: trigger, gate, sync and PPS
Type: Front panel female SSMC connector, LVTTL
Field Programmable Gate Array
Standard: Xilinx Virtex-6 XC6VLX130T. Optional: Xilinx Virtex-6 XC6VLX240T, XC6VLX365T, XC6VSX315T, or XC6VSX475T
Front Panel Analog Signal Inputs
Input Type: Transformer-coupled, front panel female SSMC connectors. Transformer Type: Coil Craft WBC4-6TLB. Full Scale Input: +8 dBm into 50 ohms. 3 dB Passband: 300 kHz to 700 MHz
Memory
Option 150 or 160: Two 8 MB QDRII+ SRAM memory banks, 400 MHz DDR Option 155 or 165: Two 512 MB DDR3 SDRAM memory banks, 400 MHz DDR
Operating Temp
0° to 50° C
PCI-Express Interface
PCI Express Bus: Gen. 1: x4 or x8; Gen. 2: x4
Relative Humidity
0 to 95%, non-cond.
Sample Clock Sources
On-board clock
Size
Half length PCIe card, 4.38 in. x 7.13 in.
Storage Temp
–20° to 90° C
Timing Bus
26-pin front panel connector; LVPECL bus includes, clock/sync/gate/ PPS inputs and outputs; TTL signal for gate/trigger and sync/PPS inputs
Features
- Complete radar and software radio interface solution
- Four 200 MHz 16-bit A/Ds
- LVDS connections to the Virtex-6 FPGA for custom I/O
- LVPECL clock/sync bus for multiboard synchronization
- PCI Express (Gen. 1 & 2) interface up to x8
- Sample clock synchronization to an external system reference
- Supports Xilinx Virtex-6 LXT and SXT FPGAs
- Up to 2 GB of DDR3 SDRAM or 32 MB of QDRII+ SRAM
- User-configurable gigabit serial interface
Frequently asked questions
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Why buy from GID?
Quality
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Protection
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Access
Our network of suppliers is ready and at your disposal
Savings
Maintain legacy systems to prevent costly downtime
Speed
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